691 lines
22 KiB
C
691 lines
22 KiB
C
#ifndef __RADEONFB_H__
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#define __RADEONFB_H__
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//#include "config.h"
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#include <bas_string.h>
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#include "pci.h"
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#include "mod_devicetable.h"
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#include "pci_ids.h"
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#include "fb.h"
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#include "i2c.h"
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#include "i2c-algo-bit.h"
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//#include "radeon_theatre.h"
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#include "radeon_reg.h"
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#ifndef point32_ter
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#define point32_ter void*
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef TRUE
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#define TRUE 1
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#endif
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/* Buffer are aligned on 4096 byte boundaries */
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#define RADEON_BUFFER_ALIGN 0x00000fff
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#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
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#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
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#define RADEON_MMIOSIZE 0x80000
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#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
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#define ATY_RADEON_LCD_ON 0x00000001
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#define ATY_RADEON_CRT_ON 0x00000002
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#define FBIO_RADEON_GET_MIRROR 0x80044003
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#define FBIO_RADEON_SET_MIRROR 0xC0044004
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/***************************************************************
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* Most of the definitions here are adapted right from XFree86 *
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***************************************************************/
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/*
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* Chip families. Must fit in the low 16 bits of a int32_t word
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*/
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enum radeon_family
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{
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CHIP_FAMILY_UNKNOW,
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CHIP_FAMILY_LEGACY,
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CHIP_FAMILY_RADEON,
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CHIP_FAMILY_RV100,
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CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
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CHIP_FAMILY_RV200,
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CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
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CHIP_FAMILY_R200,
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CHIP_FAMILY_RV250,
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CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
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CHIP_FAMILY_RV280,
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CHIP_FAMILY_R300,
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CHIP_FAMILY_R350,
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CHIP_FAMILY_RV350,
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CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
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CHIP_FAMILY_R420, /* R420/R423/M18 */
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CHIP_FAMILY_LAST,
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};
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#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
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((rinfo)->family == CHIP_FAMILY_RV200) || \
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((rinfo)->family == CHIP_FAMILY_RS100) || \
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((rinfo)->family == CHIP_FAMILY_RS200) || \
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((rinfo)->family == CHIP_FAMILY_RV250) || \
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((rinfo)->family == CHIP_FAMILY_RV280) || \
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((rinfo)->family == CHIP_FAMILY_RS300))
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#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
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((rinfo)->family == CHIP_FAMILY_RV350) || \
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((rinfo)->family == CHIP_FAMILY_R350) || \
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((rinfo)->family == CHIP_FAMILY_RV380) || \
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((rinfo)->family == CHIP_FAMILY_R420))
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/*
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* Chip flags
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*/
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enum radeon_chip_flags
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{
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CHIP_FAMILY_MASK = 0x0000ffffUL,
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CHIP_FLAGS_MASK = 0xffff0000UL,
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CHIP_IS_MOBILITY = 0x00010000UL,
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CHIP_IS_IGP = 0x00020000UL,
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CHIP_HAS_CRTC2 = 0x00040000UL,
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};
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/*
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* Errata workarounds
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*/
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enum radeon_errata
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{
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CHIP_ERRATA_R300_CG = 0x00000001,
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CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
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CHIP_ERRATA_PLL_DELAY = 0x00000004,
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};
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/*
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* Monitor types
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*/
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enum radeon_montype
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{
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MT_NONE = 0,
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MT_CRT, /* CRT */
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MT_LCD, /* LCD */
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MT_DFP, /* DVI */
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MT_CTV, /* composite TV */
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MT_STV /* S-Video out */
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};
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/*
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* DDC i2c ports
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*/
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enum ddc_type
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{
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ddc_none,
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ddc_monid,
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ddc_dvi,
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ddc_vga,
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ddc_crt2,
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};
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/*
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* Connector types
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*/
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enum conn_type
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{
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conn_none,
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conn_proprietary,
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conn_crt,
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conn_DVI_I,
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conn_DVI_D,
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};
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/*
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* PLL infos
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*/
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struct pll_info
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{
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int32_t ppll_max;
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int32_t ppll_min;
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int32_t sclk, mclk;
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int32_t ref_div;
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int32_t ref_clk;
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};
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/*
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* This structure contains the various registers manipulated by this
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* driver for setting or restoring a mode. It's mostly copied from
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* XFree's RADEONSaveRec structure. A few chip settings might still be
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* tweaked without beeing reflected or saved in these registers though
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*/
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struct radeon_regs
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{
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/* Common registers */
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uint32_t ovr_clr;
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uint32_t ovr_wid_left_right;
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uint32_t ovr_wid_top_bottom;
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uint32_t ov0_scale_cntl;
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uint32_t mpp_tb_config;
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uint32_t mpp_gp_config;
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uint32_t subpic_cntl;
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uint32_t viph_control;
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uint32_t i2c_cntl_1;
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uint32_t gen_int32_t_cntl;
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uint32_t cap0_trig_cntl;
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uint32_t cap1_trig_cntl;
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uint32_t bus_cntl;
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uint32_t surface_cntl;
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uint32_t bios_5_scratch;
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/* Other registers to save for VT switches or driver load/unload */
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uint32_t dp_datatype;
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uint32_t rbbm_soft_reset;
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uint32_t clock_cntl_index;
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uint32_t amcgpio_en_reg;
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uint32_t amcgpio_mask;
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/* Surface/tiling registers */
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uint32_t surf_lower_bound[8];
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uint32_t surf_upper_bound[8];
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uint32_t surf_info[8];
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/* CRTC registers */
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uint32_t crtc_gen_cntl;
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uint32_t crtc_ext_cntl;
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uint32_t dac_cntl;
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uint32_t crtc_h_total_disp;
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uint32_t crtc_h_sync_strt_wid;
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uint32_t crtc_v_total_disp;
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uint32_t crtc_v_sync_strt_wid;
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uint32_t crtc_offset;
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uint32_t crtc_offset_cntl;
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uint32_t crtc_pitch;
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uint32_t disp_merge_cntl;
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uint32_t grph_buffer_cntl;
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uint32_t crtc_more_cntl;
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/* CRTC2 registers */
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uint32_t crtc2_gen_cntl;
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uint32_t dac2_cntl;
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uint32_t disp_output_cntl;
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uint32_t disp_hw_debug;
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uint32_t disp2_merge_cntl;
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uint32_t grph2_buffer_cntl;
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uint32_t crtc2_h_total_disp;
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uint32_t crtc2_h_sync_strt_wid;
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uint32_t crtc2_v_total_disp;
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uint32_t crtc2_v_sync_strt_wid;
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uint32_t crtc2_offset;
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uint32_t crtc2_offset_cntl;
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uint32_t crtc2_pitch;
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/* Flat panel regs */
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uint32_t fp_crtc_h_total_disp;
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uint32_t fp_crtc_v_total_disp;
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uint32_t fp_gen_cntl;
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uint32_t fp2_gen_cntl;
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uint32_t fp_h_sync_strt_wid;
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uint32_t fp2_h_sync_strt_wid;
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uint32_t fp_horz_stretch;
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uint32_t fp_panel_cntl;
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uint32_t fp_v_sync_strt_wid;
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uint32_t fp2_v_sync_strt_wid;
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uint32_t fp_vert_stretch;
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uint32_t lvds_gen_cntl;
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uint32_t lvds_pll_cntl;
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uint32_t tmds_crc;
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uint32_t tmds_transmitter_cntl;
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/* Computed values for PLL */
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uint32_t dot_clock_freq;
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uint32_t pll_output_freq;
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int32_t feedback_div;
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int32_t post_div;
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/* PLL registers */
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uint32_t ppll_div_3;
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uint32_t ppll_ref_div;
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uint32_t vclk_ecp_cntl;
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uint32_t clk_cntl_index;
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uint32_t htotal_cntl;
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/* Computed values for PLL2 */
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uint32_t dot_clock_freq_2;
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uint32_t pll_output_freq_2;
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int32_t feedback_div_2;
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int32_t post_div_2;
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/* PLL2 registers */
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uint32_t p2pll_ref_div;
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uint32_t p2pll_div_0;
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uint32_t htotal_cntl2;
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};
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struct panel_info
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{
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int32_t xres, yres;
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int32_t valid;
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int32_t clock;
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int32_t hOver_plus, hSync_width, hblank;
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int32_t vOver_plus, vSync_width, vblank;
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int32_t hAct_high, vAct_high, int32_terlaced;
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int32_t pwr_delay;
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int32_t use_bios_dividers;
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int32_t ref_divider;
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int32_t post_divider;
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int32_t fbk_divider;
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};
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struct radeonfb_info;
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#ifdef CONFIG_FB_RADEON_I2C
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struct radeon_i2c_chan
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{
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struct radeonfb_info *rinfo;
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uint32_t ddc_reg;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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};
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#endif
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enum radeon_pm_mode {
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radeon_pm_none = 0, /* Nothing supported */
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radeon_pm_d2 = 0x00000001, /* Can do D2 state */
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radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
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};
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typedef struct
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{
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uint8_t table_revision;
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uint8_t table_size;
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uint8_t tuner_type;
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uint8_t audio_chip;
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uint8_t product_id;
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uint8_t tuner_voltage_teletext_fm;
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uint8_t i2s_config; /* configuration of the sound chip */
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uint8_t video_decoder_type;
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uint8_t video_decoder_host_config;
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uint8_t input[5];
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} _MM_TABLE;
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struct radeonfb_info
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{
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int32_t handle; /* PCI BIOS, must be 1st place */
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int32_t big_endian; /* PCI BIOS */
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uint32_t cursor_x;
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uint32_t cursor_y;
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int32_t cursor_show;
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uint32_t cursor_start;
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uint32_t cursor_end;
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int32_t cursor_fg;
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int32_t cursor_bg;
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int32_t fifo_slots; /* Free slots in the FIFO (64 max) */
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/* Computed values for Radeon */
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uint32_t dp_gui_master_cntl_clip;
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uint32_t trans_color;
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/* Saved values for ScreenToScreenCopy */
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int32_t xdir;
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int32_t ydir;
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/* ScanlineScreenToScreenColorExpand support */
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int32_t scanline_h;
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int32_t scanline_words;
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int32_t scanline_bpp; /* Only used for ImageWrite */
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/* Saved values for DashedTwoPoint32_tLine */
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int32_t dashLen;
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uint32_t dashPattern;
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int32_t dash_fg;
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int32_t dash_bg;
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struct fb_info *info;
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struct radeon_regs state;
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struct radeon_regs init_state;
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uint8_t name[50];
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uint32_t io_base_phys;
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uint32_t mmio_base_phys;
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uint32_t fb_base_phys;
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void *io_base;
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void *mmio_base;
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void *fb_base;
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uint32_t fb_local_base;
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uint32_t fb_offset;
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uint32_t bios_seg_phys;
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void *bios_seg;
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int32_t fp_bios_start;
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struct
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{
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uint8_t red, green, blue, pad;
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} palette[256];
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int32_t chipset;
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uint8_t family;
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uint8_t rev;
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int32_t errata;
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uint32_t video_ram;
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uint32_t mapped_vram;
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int32_t vram_width;
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int32_t vram_ddr;
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int32_t pitch, bpp, depth;
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int32_t has_CRTC2;
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int32_t is_mobility;
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int32_t is_IGP;
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int32_t reversed_DAC;
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int32_t reversed_TMDS;
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struct panel_info panel_info;
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int32_t mon1_type;
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uint8_t *mon1_EDID;
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struct fb_videomode *mon1_modedb;
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int32_t mon1_dbsize;
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int32_t mon2_type;
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uint8_t *mon2_EDID;
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uint32_t dp_gui_master_cntl;
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struct pll_info bios_pll;
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struct pll_info pll;
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uint32_t save_regs[100];
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int32_t asleep;
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int32_t lock_blank;
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int32_t dynclk;
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int32_t no_schedule;
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enum radeon_pm_mode pm_mode;
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/* Timer used for delayed LVDS operations */
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int32_t lvds_timer;
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uint32_t pending_lvds_gen_cntl;
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#ifdef CONFIG_FB_RADEON_I2C
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struct radeon_i2c_chan i2c[4];
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#endif
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/* Texture */
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int32_t RenderInited3D;
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int32_t tilingEnabled;
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void *RenderTex;
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uint32_t RenderTexOffset;
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int32_t RenderTexSize;
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void (*RenderCallback)(struct radeonfb_info *rinfo);
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uint32_t RenderTimeout;
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uint32_t dst_pitch_offset;
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#ifdef _NOT_USED_
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/* Video & theatre */
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TheatrePtr theatre;
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int32_t MM_TABLE_valid;
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_MM_TABLE MM_TABLE;
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int32_t RageTheatreCrystal;
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int32_t RageTheatreTunerPort;
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int32_t RageTheatreCompositePort;
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int32_t RageTheatreSVideoPort;
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int32_t tunerType;
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int32_t videoStatus;
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int32_t encoding;
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int32_t overlay_deint32_terlacing_method;
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int32_t video_stream_active;
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int32_t capture_vbi_data;
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int32_t v;
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void *videoLinear;
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int32_t videoLinearSize;
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struct
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{
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uint32_t y,u,v;
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} videoLinearOffset;
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#endif /* _NOT_USED_ */
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int32_t dec_hue;
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int32_t dec_saturation;
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int32_t dec_contrast;
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int32_t dec_brightness;
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};
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#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
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/*
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* IO macros
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*/
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/* Note about this function: we have some rare cases where we must not schedule,
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* this typically happen with our special "wake up early" hook which allows us to
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* wake up the graphic chip (and thus get the console back) before everything else
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* on some machines that support that mecanism. At this point32_t, int32_terrupts are off
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* and scheduling is not permitted
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*/
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static inline void _radeon_msleep(struct radeonfb_info *rinfo, uint32_t ms)
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{
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mdelay(ms);
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}
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#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
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extern void _OUTREGP(struct radeonfb_info *rinfo, uint32_t addr, uint32_t val, uint32_t mask);
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extern void radeon_pll_errata_after_index(struct radeonfb_info *rinfo);
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extern void radeon_pll_errata_after_data(struct radeonfb_info *rinfo);
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extern uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr);
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extern void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val);
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extern void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask);
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extern uint16_t _swap_int16_t(uint16_t val);
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extern uint32_t _swap_int32_t(uint32_t val);
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#define INREG8(addr) *((uint8_t *)(rinfo->mmio_base+addr))
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#define INREG16(addr) _swap_int16_t(*(uint16_t *)(rinfo->mmio_base+addr))
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#define INREG(addr) _swap_int32_t(*(uint32_t *)(rinfo->mmio_base+addr))
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#define OUTREG8(addr,val) (*((uint8_t *)(rinfo->mmio_base+addr)) = val)
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#define OUTREG16(addr,val) (*((uint16_t *)(rinfo->mmio_base+addr)) = _swap_int16_t(val))
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#define OUTREG(addr,val) (*((uint32_t *)(rinfo->mmio_base+addr)) = _swap_int32_t(val))
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extern int32_t *tab_funcs_pci;
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|
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|
#define BIOS_IN8(v) (Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v))
|
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#define BIOS_IN16(v) ((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \
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((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8))
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#define BIOS_IN32(v) ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \
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((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8) | \
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((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+2) << 16) | \
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((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+3) << 24))
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#define ADDRREG(addr) ((volatile uint32_t *)(rinfo->mmio_base + (addr)))
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#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val, mask)
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#define INPLL(addr) __INPLL(rinfo, addr)
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#define OUTPLL(index,val) __OUTPLL(rinfo, index, val)
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#define OUTPLLP(index,val,mask) __OUTPLLP(rinfo, index, val, mask)
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/*
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* Inline utilities
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|
*/
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static inline uint32_t radeon_get_dstbpp(uint16_t depth)
|
|
{
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switch(depth)
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{
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case 8: return DST_8BPP;
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case 15: return DST_15BPP;
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case 16: return DST_16BPP;
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case 32: return DST_32BPP;
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default: return 0;
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}
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}
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/* I2C Functions */
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extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
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extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
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extern int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid);
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/* PM Functions */
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/* extern int32_t radeonfb_pci_suspend(struct pci_dev *pdev, uint32_t state);
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extern int32_t radeonfb_pci_resume(struct pci_dev *pdev); */
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extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int32_t dynclk);
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extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
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/* Monitor probe functions */
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extern void radeon_probe_screens(struct radeonfb_info *rinfo,
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const uint8_t *monitor_layout, int32_t ignore_edid);
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extern void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution);
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extern int32_t radeon_match_mode(struct radeonfb_info *rinfo,
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struct fb_var_screeninfo *dest,
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const struct fb_var_screeninfo *src);
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/* Video functions */
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void RADEONResetVideo(struct radeonfb_info *rinfo);
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int32_t RADEONVIP_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
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int32_t RADEONVIP_fifo_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
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int32_t RADEONVIP_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
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int32_t RADEONVIP_fifo_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
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void RADEONVIP_reset(struct radeonfb_info *rinfo);
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void RADEONInitVideo(struct radeonfb_info *rinfo);
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void RADEONShutdownVideo(struct radeonfb_info *rinfo);
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int32_t RADEONPutVideo(struct radeonfb_info *rinfo, int32_t src_x, int32_t src_y, int32_t src_w, int32_t src_h,
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int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h);
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void RADEONStopVideo(struct radeonfb_info *rinfo, int32_t cleanup);
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|
|
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/* Theatre functions */
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//extern TheatrePtr DetectTheatre(struct radeonfb_info *rinfo);
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//extern void RT_SetTint32_t(TheatrePtr t, int32_t hue);
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//extern void RT_SetSaturation(TheatrePtr t, int32_t Saturation);
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//extern void RT_SetBrightness(TheatrePtr t, int32_t Brightness);
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//extern void RT_SetSharpness(TheatrePtr t, uint16_t wSharpness);
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//extern void RT_SetContrast(TheatrePtr t, int32_t Contrast);
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//extern void RT_SetInterlace(TheatrePtr t, uint8_t bInterlace);
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//extern void RT_SetStandard(TheatrePtr t, uint16_t wStandard);
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//extern void RT_SetCombFilter(TheatrePtr t, uint16_t wStandard, uint16_t wConnector);
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|
//extern void RT_SetOutputVideoSize(TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On);
|
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//extern void RT_SetConnector(TheatrePtr t, uint16_t wConnector, int32_t tunerFlag);
|
|
//extern void InitTheatre(TheatrePtr t);
|
|
//extern void ShutdownTheatre(TheatrePtr t);
|
|
//extern void ResetTheatreRegsForNoTVout(TheatrePtr t);
|
|
//extern void ResetTheatreRegsForTVout(TheatrePtr t);
|
|
extern void RADEONVIP_reset(struct radeonfb_info *rinfo);
|
|
|
|
/* Accel functions */
|
|
|
|
extern void RADEONWaitForFifoFunction(struct radeonfb_info *rinfo, int32_t entries);
|
|
extern void RADEONEngineFlush(struct radeonfb_info *rinfo);
|
|
extern void RADEONEngineReset(struct radeonfb_info *rinfo);
|
|
extern void RADEONEngineRestore(struct radeonfb_info *rinfo);
|
|
extern void RADEONEngineInit(struct radeonfb_info *rinfo);
|
|
extern void RADEONWaitForIdleMMIO(struct radeonfb_info *rinfo);
|
|
|
|
#define RADEONWaitForFifo(rinfo, entries) \
|
|
do { \
|
|
if(rinfo->fifo_slots < entries) \
|
|
RADEONWaitForFifoFunction(rinfo, entries); \
|
|
rinfo->fifo_slots -= entries; \
|
|
} while(0)
|
|
|
|
#define radeon_fifo_wait(entries) RADEONWaitForFifo(rinfo, entries)
|
|
#define radeon_engine_flush(rinfo) RADEONEngineFlush(rinfo)
|
|
#define radeonfb_engine_reset(rinfo) RADEONEngineReset(rinfo)
|
|
#define radeonfb_engine_init(rinfo) RADEONEngineInit(rinfo)
|
|
#define radeon_engine_idle() RADEONWaitForIdleMMIO(rinfo)
|
|
|
|
static inline int32_t radeonfb_sync(struct fb_info *info)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
radeon_engine_idle();
|
|
return 0;
|
|
}
|
|
|
|
extern void RADEONRestoreAccelStateMMIO(struct fb_info *info);
|
|
extern void RADEONSetupForSolidFillMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask);
|
|
extern void RADEONSubsequentSolidFillRectMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
|
|
extern void RADEONSetupForSolidLineMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask);
|
|
extern void RADEONSubsequentSolidHorVertLineMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);
|
|
|
|
extern void RADEONSubsequentSolidTwoPointLineMMIO(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb,
|
|
int32_t yb, int32_t flags);
|
|
extern void RADEONSetupForDashedLineMMIO(struct fb_info *info, int32_t fg, int32_t bg,
|
|
int32_t rop, int32_t planemask, int32_t length, uint8_t *pattern);
|
|
extern void RADEONSubsequentDashedTwoPointLineMMIO(struct fb_info *info,
|
|
int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);
|
|
extern void RADEONSetupForScreenToScreenCopyMMIO(struct fb_info *info,
|
|
int32_t xdir, int32_t ydir, int32_t rop, int32_t planemask, int32_t trans_color);
|
|
extern void RADEONSubsequentScreenToScreenCopyMMIO(struct fb_info *info,
|
|
int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);
|
|
extern void RADEONScreenToScreenCopyMMIO(struct fb_info *info,
|
|
int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
|
|
extern void RADEONSetupForMono8x8PatternFillMMIO(struct fb_info *info,
|
|
int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, int32_t planemask);
|
|
extern void RADEONSubsequentMono8x8PatternFillRectMMIO(struct fb_info *info,
|
|
int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
|
|
extern void RADEONSetupForScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info,
|
|
int32_t fg, int32_t bg, int32_t rop, int32_t planemask);
|
|
extern void RADEONSubsequentScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info,
|
|
int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
|
extern void RADEONSubsequentScanlineMMIO(struct fb_info *info, uint32_t *buf);
|
|
extern void RADEONSetupForScanlineImageWriteMMIO(struct fb_info *info,
|
|
int32_t rop, int32_t planemask, int32_t trans_color, int32_t bpp);
|
|
extern void RADEONSubsequentScanlineImageWriteRectMMIO(struct fb_info *info,
|
|
int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
|
extern void RADEONSetClippingRectangleMMIO(struct fb_info *info,
|
|
int32_t xa, int32_t ya, int32_t xb, int32_t yb);
|
|
extern void RADEONDisableClippingMMIO(struct fb_info *info);
|
|
|
|
#ifndef MCF5445X
|
|
extern int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info,
|
|
int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags);
|
|
extern int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info,
|
|
int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags);
|
|
extern void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info,
|
|
int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height);
|
|
#else
|
|
static __inline__ int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info,
|
|
int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags)
|
|
{ return FALSE; }
|
|
static __inline__ int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info,
|
|
int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags)
|
|
{ return FALSE; }
|
|
static __inline__ void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info,
|
|
int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height) { }
|
|
#endif /* MCF5445X */
|
|
|
|
/* Cursor functions */
|
|
extern void RADEONSetCursorColors(struct fb_info *info, int32_t bg, int32_t fg);
|
|
extern void RADEONSetCursorPosition(struct fb_info *info, int32_t x, int32_t y);
|
|
extern void RADEONLoadCursorImage(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom);
|
|
extern void RADEONHideCursor(struct fb_info *info);
|
|
extern void RADEONShowCursor(struct fb_info *info);
|
|
extern int32_t RADEONCursorInit(struct fb_info *info);
|
|
|
|
/* Other functions */
|
|
extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch);
|
|
extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only);
|
|
int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green,
|
|
uint32_t blue, uint32_t transp, struct fb_info *info);
|
|
extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent);
|
|
extern void radeonfb_pci_unregister(void);
|
|
|
|
/* global */
|
|
extern uint8_t monitor_layout[];
|
|
extern int16_t default_dynclk;
|
|
extern int16_t ignore_edid;
|
|
extern int16_t mirror;
|
|
extern int16_t virtual;
|
|
extern int16_t force_measure_pll;
|
|
extern int16_t zoom_mouse;
|
|
|
|
#endif /* __RADEONFB_H__ */
|