21401b69a3
was scanning PCI config space of all valid slot/bus combination when all needed information is already available from the initial scan.
361 lines
20 KiB
C
361 lines
20 KiB
C
#ifndef _PCI_H_
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#define _PCI_H_
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/*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Created on: 26.02.2013
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* Author: Markus Fröschle
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*/
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#include <bas_types.h>
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#include "util.h" /* for swpX() */
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#define PCI_MEMORY_OFFSET 0x80000000
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#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */
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#define PCI_IO_OFFSET 0xD0000000
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#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */
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#define PCI_LANESWAP_B(x) (x ^ 3)
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#define PCI_LANESWAP_W(x) (x ^ 2)
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#define PCI_LANESWAP_L(x) (x) /* for completeness only */
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/*
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* Note: the byte offsets are in little endian format, so for pci_xxx_config_byte()
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* accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B()
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* and for pci_xxx_config_word() into PCI_LANESWAP_W()
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*/
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#define PCIIDR 0x00 /* PCI Configuration ID Register */
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#define PCICSR 0x04 /* PCI Command/Status Register */
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#define PCICR 0x06 /* PCI Command Register */
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#define PCISR 0x04 /* PCI Status Register */
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#define PCIREV 0x0B /* PCI Revision ID Register */
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#define PCICCR 0x08 /* PCI Class Code Register */
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#define PCICLSR 0x0F /* PCI Cache Line Size Register */
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#define PCILTR 0x0E /* PCI Latency Timer Register */
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#define PCIHTR 0x0D /* PCI Header Type Register */
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#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */
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#define PCIBAR0 0x10 /* PCI Base Address Register for Memory
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Accesses to Local, Runtime, and DMA */
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#define PCIBAR1 0x14 /* PCI Base Address Register for I/O
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Accesses to Local, Runtime, and DMA */
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#define PCIBAR2 0x18 /* PCI Base Address Register for Memory
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Accesses to Local Address Space 0 */
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#define PCIBAR3 0x1C /* PCI Base Address Register for Memory
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Accesses to Local Address Space 1 */
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#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */
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#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
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#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
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#define PCISVID 0x2E /* PCI Subsystem Vendor ID */
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#define PCISID 0x2D /* PCI Subsystem ID */
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#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */
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#define CAP_PTR 0x34 /* New Capability Pointer */
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#define PCIILR 0x3F /* PCI Interrupt Line Register */
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#define PCIIPR 0x3E /* PCI Interrupt Pin Register */
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#define PCIMGR 0x3D /* PCI Min_Gnt Register */
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#define PCIMLR 0x3C /* PCI Max_Lat Register */
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#define PMCAPID 0x40 /* Power Management Capability ID */
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#define PMNEXT 0x41 /* Power Management Next Capability
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Pointer */
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#define PMC 0x42 /* Power Management Capabilities */
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#define PMCSR 0x44 /* Power Management Control/Status */
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#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */
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#define PMDATA 0x47 /* Power Management Data */
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#define HS_CNTL 0x48 /* Hot Swap Control */
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#define HS_NEXT 0x49 /* Hot Swap Next Capability Pointer */
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#define HS_CSR 0x4A /* Hot Swap Control/Status */
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#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */
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#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next
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Capability Pointer */
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#define PVPDAD 0x4E /* PCI Vital Product Data Address */
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#define PVPDATA 0x50 /* PCI VPD Data */
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/*
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* bit definitions for PCICSR lower half (Command Register)
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*/
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#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */
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#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
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#define PCICR_MASTER (1 << 2) /* if set: device is master */
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#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
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#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
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#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
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#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */
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#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */
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#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */
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#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
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#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
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/*
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* bit definitions for PCICSR upper half (Status Register)
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*/
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#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */
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#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
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#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */
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#define PCISR_UDF (1 << 6) /* UDF supported */
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#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
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#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */
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#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */
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#define PCISR_T_ABORT_R (1 << 12) /* target abort received */
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#define PCISR_M_ABORT_R (1 << 13) /* master abort received */
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#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */
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#define PCISR_PARITY_ERR (1 << 15) /* data parity error */
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/* Header type 1 (PCI-to-PCI bridges) */
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#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */
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#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */
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#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */
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#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */
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#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */
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#define PCI_IO_LIMIT 0x1D
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#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */
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#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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#define PCI_MEMORY_LIMIT 0x22
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#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
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#define PCI_PREF_MEMORY_LIMIT 0x26
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#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
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#define PCI_PREF_LIMIT_UPPER32 0x2C
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#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
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#define PCI_IO_LIMIT_UPPER16 0x32
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#define PCI_BRIDGE_CONTROL 0x3E /* Bridge Control */
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struct pci_rd /* structure of resource descriptor */
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{
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unsigned short next; /* length of the following structure */
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unsigned short flags; /* type of resource and misc. flags */
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unsigned long start; /* start-address of resource */
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unsigned long length; /* length of resource */
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unsigned long offset; /* offset PCI to phys. CPU Address */
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unsigned long dmaoffset; /* offset for DMA-transfers */
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};
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typedef struct /* structure of address conversion */
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{
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unsigned long adr; /* calculated address (CPU<->PCI) */
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unsigned long len; /* length of memory range */
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} PCI_CONV_ADR;
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/******************************************************************************/
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/* PCI-BIOS Error Codes */
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/******************************************************************************/
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#define PCI_SUCCESSFUL 0 /* everything's fine */
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#define PCI_FUNC_NOT_SUPPORTED -2 /* function not supported */
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#define PCI_BAD_VENDOR_ID -3 /* wrong Vendor ID */
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#define PCI_DEVICE_NOT_FOUND -4 /* PCI-Device not found */
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#define PCI_BAD_REGISTER_NUMBER -5 /* wrong register number */
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#define PCI_SET_FAILED -6 /* reserved for later use */
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#define PCI_BUFFER_TOO_SMALL -7 /* reserved for later use */
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#define PCI_GENERAL_ERROR -8 /* general BIOS error code */
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#define PCI_BAD_HANDLE -9 /* wrong/unknown PCI-handle */
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/******************************************************************************/
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/* Flags used in Resource-Descriptor */
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/******************************************************************************/
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#define FLG_IO 0x4000 /* Ressource in IO range */
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#define FLG_ROM 0x2000 /* Expansion ROM */
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#define FLG_LAST 0x8000 /* last ressource */
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#define FLG_8BIT 0x0100 /* 8 bit accesses allowed */
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#define FLG_16BIT 0x0200 /* 16 bit accesses allowed */
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#define FLG_32BIT 0x0400 /* 32 bit accesses allowed */
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#define FLG_ENDMASK 0x000F /* mask for byte ordering */
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/******************************************************************************/
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/* Values used in FLG_ENDMASK for Byte Ordering */
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/******************************************************************************/
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#define ORD_MOTOROLA 0 /* Motorola (big endian) */
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#define ORD_INTEL_AS 1 /* Intel (little endian), addr.swapped */
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#define ORD_INTEL_LS 2 /* Intel (little endian), lane swapped */
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#define ORD_UNKNOWN 15 /* unknown (BIOS-calls allowed only) */
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/******************************************************************************/
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/* Status Info used in Device-Descriptor */
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/******************************************************************************/
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#define DEVICE_FREE 0 /* Device is not used */
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#define DEVICE_USED 1 /* Device is used by another driver */
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#define DEVICE_CALLBACK 2 /* used, but driver can be cancelled */
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#define DEVICE_AVAILABLE 3 /* used, not available */
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#define NO_DEVICE -1 /* no device detected */
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/* PCI configuration space macros */
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/* register 0x00 macros */
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#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16)
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#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff)
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/* register 0x04 macros */
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#define PCI_STATUS(i) ((i) & 0xffff)
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#define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
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/* register 0x08 macros (use on little endian value!) */
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#define PCI_CLASS_CODE(i) (((i) & 0x00ff0000) >> 16)
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#define PCI_SUBCLASS(i) (((i) & 0x0000ff00) >> 8)
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#define PCI_PROG_IF(i) (((i) & 0x000000ff) >> 0)
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#define PCI_REVISION_ID(i) (((i) & 0xff000000) >> 24)
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/* register 0x0c macros */
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#define PCI_BIST(i) (((i) & 0xff000000) >> 24)
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#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16)
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#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8)
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#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff))
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/* register 0x2c macros */
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#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16)
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#define PCI_SUBSYS_VID(i) ((i) & 0xffff))
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/* register 0x34 macros */
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#define PCI_CAPABILITIES(i) ((i) & 0xff)
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/* register 0x3c macros */
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#define PCI_MAX_LATENCY(i) (((i) & 0xff000000) >> 24)
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#define PCI_MIN_GRANT(i) (((i) & 0xff0000) >> 16)
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#define PCI_INTERRUPT_PIN(i) (((i) & 0xff00) >> 8)
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#define PCI_INTERRUPT_LINE(i) (((i)) & 0xff)
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#define IS_PCI_MEM_BAR(i) ((i) & 1) == 0
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#define IS_PCI_IO_BAR(i) ((i) & 1) == 1
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#define PCI_MEMBAR_TYPE(i) (((i) & 0x6) >> 1)
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#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc))
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#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0))
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extern void init_eport(void);
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extern void init_xlbus_arbiter(void);
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extern void init_pci(void);
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extern int pci_handle2index(int32_t handle);
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extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
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extern int32_t pci_find_classcode(uint32_t classcode, int index);
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extern int32_t pci_get_interrupt_cause(void);
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extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
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/*
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* match bits for pci_find_classcode()
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*/
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#define PCI_FIND_BASE_CLASS (1 << 26)
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#define PCI_FIND_SUB_CLASS (1 << 25)
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#define PCI_FIND_PROG_IF (1 << 24)
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extern uint32_t pci_read_config_longword(int32_t handle, int offset);
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extern uint16_t pci_read_config_word(int32_t handle, int offset);
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extern uint8_t pci_read_config_byte(int32_t handle, int offset);
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extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value);
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extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
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extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
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typedef int (*pci_interrupt_handler)(int param);
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extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter);
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extern int32_t pci_unhook_interrupt(int32_t handle);
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extern struct pci_rd *pci_get_resource(int32_t handle);
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/*
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* Not implemented PCI_BIOS functions
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*/
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extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
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extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
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extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
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extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
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extern int32_t pci_get_routing(int32_t handle);
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extern int32_t pci_set_interrupt(int32_t handle);
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extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
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extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
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extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
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extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
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extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
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extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
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extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
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extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
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extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
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extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
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extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
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extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
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extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
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extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
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extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
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extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
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extern int32_t pci_get_machine_id(void);
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extern int32_t pci_get_pagesize(void);
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extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
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extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
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extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
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extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
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/*
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* prototypes for PCI wrapper routines
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*/
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extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
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extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
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extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
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extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
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extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
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extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
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extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
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extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
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extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
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extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
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extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
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extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
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extern int32_t wrapper_unhook_interrupt(int32_t handle);
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extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
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extern int32_t wrapper_get_routing(int32_t handle);
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extern int32_t wrapper_set_interrupt(int32_t handle);
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extern int32_t wrapper_get_resource(int32_t handle);
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extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
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extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
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extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
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extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
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extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
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extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
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extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
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extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
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extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
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extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
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extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
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extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
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extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
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extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
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extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
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extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
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extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
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extern int32_t wrapper_get_machine_id(void);
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extern int32_t wrapper_get_pagesize(void);
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extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
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extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
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extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
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extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
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#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
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((bus) << 16) | \
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((device << 8) | \
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(function))
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#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
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#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10)
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#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3)
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#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7))
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extern void pci_dump_registers(int32_t handle);
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#endif /* _PCI_H_ */
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