100 lines
4.5 KiB
Verilog
100 lines
4.5 KiB
Verilog
// Xilinx XPort Language Converter, Version 4.1 (110)
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//
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// AHDL Design Source: lpm_bustri_WORD.tdf
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// Verilog Design Output: lpm_bustri_WORD.v
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// Created 02-Mar-2014 04:36 PM
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//
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// Copyright (c) 2014, Xilinx, Inc. All Rights Reserved.
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// Xilinx Inc makes no warranty, expressed or implied, with respect to
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// the operation and/or functionality of the converted output files.
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//
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// ------------------------------------------------------------------
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// LPM_BUSTRI Parameterized Megafunction
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// Quartus II 13.1.0 Build 162 10/23/2013
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// Version 2.0
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// ------------------------------------------------------------------
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module lpm_bustri_WORD(tridata, data, enabletr, enabledt, result);
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input [15:0] data;
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input enabletr, enabledt;
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output [15:0] result;
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inout [15:0] tridata;
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// Are the enable inputs used?
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wire [15:0] dout;
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wire [15:0] dout_in;
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wire gnd, result0_1, result0_2, result1_1, result1_2, result2_1, result2_2,
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result3_1, result3_2, result4_1, result4_2, result5_1, result5_2,
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result6_1, result6_2, result7_1, result7_2, result8_1, result8_2,
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result9_1, result9_2, result10_1, result10_2, result11_1, result11_2,
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result12_1, result12_2, result13_1, result13_2, result14_1,
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result14_2, result15_1, result15_2, dout0_oe_ctrl;
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assign dout[0] = (dout0_oe_ctrl) ? dout_in[0] : 1'bz;
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assign dout[1] = (dout0_oe_ctrl) ? dout_in[1] : 1'bz;
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assign dout[2] = (dout0_oe_ctrl) ? dout_in[2] : 1'bz;
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assign dout[3] = (dout0_oe_ctrl) ? dout_in[3] : 1'bz;
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assign dout[4] = (dout0_oe_ctrl) ? dout_in[4] : 1'bz;
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assign dout[5] = (dout0_oe_ctrl) ? dout_in[5] : 1'bz;
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assign dout[6] = (dout0_oe_ctrl) ? dout_in[6] : 1'bz;
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assign dout[7] = (dout0_oe_ctrl) ? dout_in[7] : 1'bz;
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assign dout[8] = (dout0_oe_ctrl) ? dout_in[8] : 1'bz;
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assign dout[9] = (dout0_oe_ctrl) ? dout_in[9] : 1'bz;
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assign dout[10] = (dout0_oe_ctrl) ? dout_in[10] : 1'bz;
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assign dout[11] = (dout0_oe_ctrl) ? dout_in[11] : 1'bz;
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assign dout[12] = (dout0_oe_ctrl) ? dout_in[12] : 1'bz;
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assign dout[13] = (dout0_oe_ctrl) ? dout_in[13] : 1'bz;
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assign dout[14] = (dout0_oe_ctrl) ? dout_in[14] : 1'bz;
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assign dout[15] = (dout0_oe_ctrl) ? dout_in[15] : 1'bz;
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// Start of original equations
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// Connect buffers if they are used
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assign dout0_oe_ctrl = enabledt;
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assign dout_in = data;
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assign tridata = dout;
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assign {result15_1, result14_1, result13_1, result12_1, result11_1,
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result10_1, result9_1, result8_1, result7_1, result6_1, result5_1,
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result4_1, result3_1, result2_1, result1_1, result0_1} = tridata;
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assign {result15_2, result14_2, result13_2, result12_2, result11_2,
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result10_2, result9_2, result8_2, result7_2, result6_2, result5_2,
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result4_2, result3_2, result2_2, result1_2, result0_2} = {16{gnd}};
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// Assignments added to explicitly combine the
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// effects of multiple drivers in the source
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assign result[0] = result0_1 | result0_2;
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assign result[1] = result1_1 | result1_2;
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assign result[2] = result2_1 | result2_2;
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assign result[3] = result3_1 | result3_2;
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assign result[4] = result4_1 | result4_2;
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assign result[5] = result5_1 | result5_2;
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assign result[6] = result6_1 | result6_2;
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assign result[7] = result7_1 | result7_2;
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assign result[8] = result8_1 | result8_2;
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assign result[9] = result9_1 | result9_2;
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assign result[10] = result10_1 | result10_2;
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assign result[11] = result11_1 | result11_2;
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assign result[12] = result12_1 | result12_2;
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assign result[13] = result13_1 | result13_2;
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assign result[14] = result14_1 | result14_2;
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assign result[15] = result15_1 | result15_2;
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// Define power signal(s)
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assign gnd = 1'b0;
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endmodule
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