459 lines
7.8 KiB
ArmAsm
459 lines
7.8 KiB
ArmAsm
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//.include "startcf.h"
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//.extern ___MBAR
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//#define MCF_SLT0_SCNT ___MBAR+0x908
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//.global ide_test
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.text
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/*
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sd_test:
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clr.w MCF_PAD_PAR_DSPI
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lea MCF_GPIO_PPDSDR_DSPI,a2 // data in
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lea MCF_GPIO_PODR_DSPI,a1 // data out
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move.b #0x00,(a1) // alle auf 0
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lea MCF_GPIO_PDDR_DSPI,a0
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move.b #0x7d,(a0) // din = input rest output
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bsr warten_20ms
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move.b #0x7f,(a1) // alle auf 1
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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// sd idle
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sd_idle:
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bsr sd_16clk
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moveq #0x40,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x95,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x05,d5
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beq sd_test
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cmp.b #0x01,d5
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beq wait_of_aktiv
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cmp.b #0x04,d5
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beq sd_init_ok
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cmp.b #0x00,d5
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beq sd_init_ok
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bra sd_idle
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// acdm 41
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wait_of_aktiv:
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bsr sd_16clk
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moveq #0x77,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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bsr sd_16clk
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move.l #0xff,d6
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moveq #0x69,d4
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bsr sd_com
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and d5,d6
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moveq #00,d4
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bsr sd_com
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and d5,d6
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moveq #00,d4
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bsr sd_com
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and d5,d6
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moveq #0x02,d4
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bsr sd_com
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and d5,d6
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moveq #00,d4
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bsr sd_com
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and d5,d6
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moveq #0x01,d4
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bsr sd_com
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and d5,d6
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bsr sd_receive
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cmp.b #0x00,d5
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beq sd_init_ok
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cmp.b #0x05,d5
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beq sd_test
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bra wait_of_aktiv
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sd_init_ok:
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// blockgrösse 512byt
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sd_bg:
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bsr sd_16clk
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moveq #0x50,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #02,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_bg
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// read block
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sd_rb:
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bsr sd_16clk
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moveq #0x51,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x08,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_rb
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lea 0xc00000,a4
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move.l #513,d7
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rd_rb:
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bsr sd_receive
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move.b d5,(a4)+
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subq.l #1,d7
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bne rd_rb
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// write block
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sd_wb:
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bsr sd_16clk
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moveq #0x58,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x08,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_wb
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lea 0xc00000,a4
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move.l #513,d7
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moveq.l #0x66,d4
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wr_wb:
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bsr sd_com
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// subq.l #1,d4
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moveq #0x66,d4
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subq.l #1,d7
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bne wr_wb
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bsr sd_receive
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wr_wb_el:
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moveq #0xff,d4
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bsr sd_com
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cmp.b #0xff,d5
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bne wr_wb_el
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// read block 2
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sd_rb2:
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bsr sd_16clk
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moveq #0x51,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x08,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_rb2
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lea 0xc00400,a4
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move.l #513,d7
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rd_rb2:
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bsr sd_receive
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move.b d5,(a4)+
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subq.l #1,d7
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bne rd_rb2
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nop
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nop
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rts
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sd_receive:
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moveq #0xff,d4
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bsr sd_com
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cmp.b #0xff,d5
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beq sd_receive
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rts
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sd_com:
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bclr.b #6,(a1)
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sd_comb:
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bsr warten_10us
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moveq #7,d2
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clr.l d5
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sd_com_loop:
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btst d2,d4
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beq sd_com2
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bset.b #0,(a1)
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bra sd_com2_1
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sd_com2:
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bclr.b #0,(a1)
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sd_com2_1:
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bsr sd_clk
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and.l #0x02,d3
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beq sd_com3
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bset.b d2,d5
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sd_com3:
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subq.l #1,d2
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bge sd_com_loop
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bsr warten_10us
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bset.b #6,(a1)
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bset.b #0,(a1)
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bsr warten_200us
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rts
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sd_clk:
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tst.b 0xfffff700
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tst.b 0xfffff700
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bset.b #2,(a1)
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tst.b 0xfffff700
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tst.b 0xfffff700
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move.b (a2),d3
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tst.b 0xfffff700
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bclr.b #2,(a1)
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rts
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sd_15clk:
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move #15,d0
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bra sd_16clk
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sd_16clk:
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moveq #16,d0
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sd_16clk1:
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bsr sd_clk
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subq.l #1,d0
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bne sd_16clk1
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bsr warten_10us
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rts
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// warteschleife ca. 20ms
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warten_20ms:
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move.l a0,-(sp)
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move.l d6,-(sp)
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move.l d1,-(sp)
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move.l d0,-(sp)
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lea MCF_SLT0_SCNT,a0
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move.l (a0),d0
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move.l #700000,d6
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bra warten_loop
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// warteschleife ca. 200us
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warten_200us:
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move.l a0,-(sp)
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move.l d6,-(sp)
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move.l d1,-(sp)
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move.l d0,-(sp)
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lea MCF_SLT0_SCNT,a0
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move.l (a0),d0
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move.l #7000,d6
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bra warten_loop
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// warteschleife ca. 10us
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warten_10us:
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move.l a0,-(sp)
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move.l d6,-(sp)
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move.l d1,-(sp)
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move.l d0,-(sp)
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lea MCF_SLT0_SCNT,a0
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move.l (a0),d0
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move.l #333,d6
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warten_loop:
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move.l (a0),d1
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sub.l d0,d1
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add.l d6,d1
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bpl warten_loop
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move.l (sp)+,d0
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move.l (sp)+,d1
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move.l (sp)+,d6
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move.l (sp)+,a0
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rts;
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/********************************************************************/
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#define cmd_reg (0x1d)
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#define status_reg (0x1d)
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#define seccnt (0x09)
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ide_test:
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lea 0xfff00040,a0
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lea 0xc00000,a1
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move.b #0xec,cmd_reg(a0) //identify devcie cmd
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bsr wait_int
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bsr ds_rx
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// read sector normal
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move.b #1,seccnt(a0) // 1 sector
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move.b #0x20,cmd_reg(a0) // read cmd
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bsr wait_int
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bsr ds_rx
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// write testpattern sector
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move.b #1,seccnt(a0) // 1 sector
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move.b #0x30,cmd_reg(a0) // write cmd
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bsr drq_wait
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// write pattern
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move.l #256,d0
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ide_test_loop3:
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move.w #0xa55a,(a0)
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subq.l #1,d0
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bne ide_test_loop3
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bsr wait_int
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// read testpattern sector
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move.b #1,seccnt(a0) // 1 sector
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move.b #0x20,cmd_reg(a0) // read
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bsr wait_int
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bsr ds_rx
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// sector restauriern
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move.b #1,seccnt(a0) // 1 sector
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move.b #0x30,cmd_reg(a0) // write
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lea -0x400(a1),a1 // vorletzer
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bsr drq_wait
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bsr ds_tx
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bsr wait_int
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// fertig und zurück
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nop
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rts
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// wait auf int
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wait_int:
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move.b 0xfffffa01,d0
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btst #5,d0
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bne wait_int
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move.b status_reg(a0),d0
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rts
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// wait auf drq
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drq_wait:
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move.b status_reg(a0),d0
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btst #3,d0
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beq drq_wait
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rts
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// 1 sector lesen word
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ds_rx:
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move.l #256,d0
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ds_rx_loop:
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move.w (a0),(a1)+
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subq.l #1,d0
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bne ds_rx_loop
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rts
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// 1 sector lesen long
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ds_rxl:
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move.l #128,d0
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ds_rxl_loop:
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move.l (a0),(a1)+
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subq.l #1,d0
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bne ds_rxl_loop
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rts
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// 1 sector schreiben word
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ds_tx:
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move.l #256,d0
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ds_tx_loop:
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move.w (a1)+,(a0)
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subq.l #1,d0
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bne ds_tx_loop
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rts
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// 1 sector schreiben word
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ds_txl:
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move.l #128,d0
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ds_txl_loop:
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move.l (a1)+,(a0)
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subq.l #1,d0
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bne ds_txl_loop
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rts
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// warteschleife ca. 20ms
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warten_20ms:
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move.l a0,-(sp)
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move.l d6,-(sp)
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move.l d1,-(sp)
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move.l d0,-(sp)
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lea MCF_SLT0_SCNT,a0
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move.l (a0),d0
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move.l #700000,d6
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bra warten_loop
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// warteschleife ca. 200us
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warten_200us:
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move.l a0,-(sp)
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move.l d6,-(sp)
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move.l d1,-(sp)
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move.l d0,-(sp)
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lea MCF_SLT0_SCNT,a0
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move.l (a0),d0
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move.l #7000,d6
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bra warten_loop
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// warteschleife ca. 10us
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warten_10us:
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move.l a0,-(sp)
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move.l d6,-(sp)
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move.l d1,-(sp)
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move.l d0,-(sp)
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lea MCF_SLT0_SCNT,a0
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move.l (a0),d0
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move.l #333,d6
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warten_loop:
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move.l (a0),d1
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sub.l d0,d1
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add.l d6,d1
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bpl warten_loop
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move.l (sp)+,d0
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move.l (sp)+,d1
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move.l (sp)+,d6
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move.l (sp)+,a0
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rts;
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/********************************************************************/
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