83 lines
2.7 KiB
VHDL
83 lines
2.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ddr_ctlr_tb is
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end ddr_ctlr_tb;
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architecture beh of ddr_ctlr_tb is
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signal clock : std_logic := '0'; -- main clock
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signal clock_33 : std_logic := '0'; -- 33 MHz clock
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signal ddr_clk : std_logic := '0'; -- ddr clock
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signal vec : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
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signal o : std_logic_vector(31 downto 0);
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component DDR_CTRL_V1
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port(
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CLK_MAIN : in std_logic;
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DDR_SYNC_66M : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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FB_CS1n : in std_logic;
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FB_OEn : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_ALE : in std_logic;
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FB_WRn : in std_logic;
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FIFO_CLR : in std_logic;
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VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
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BLITTER_ADR : in std_logic_vector(31 downto 0);
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BLITTER_SIG : in std_logic;
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BLITTER_WR : in std_logic;
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DDRCLK0 : in std_logic;
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CLK_33M : in std_logic;
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FIFO_MW : in std_logic_vector(8 downto 0);
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VA : out std_logic_vector(12 downto 0);
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VWEn : out std_logic;
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VRASn : out std_logic;
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VCSn : out std_logic;
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VCKE : out std_logic;
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VCASn : out std_logic;
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FB_LE : out std_logic_vector(3 downto 0);
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FB_VDOE : out std_logic_vector(3 downto 0);
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SR_FIFO_WRE : out std_logic;
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SR_DDR_FB : out std_logic;
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SR_DDR_WR : out std_logic;
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SR_DDRWR_D_SEL : out std_logic;
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SR_VDMP : out std_logic_vector(7 downto 0);
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VIDEO_DDR_TA : out std_logic;
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SR_BLITTER_DACK : out std_logic;
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BA : out std_logic_vector(1 downto 0);
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DDRWR_D_SEL1 : out std_logic;
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VDM_SEL : out std_logic_vector(3 downto 0);
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DATA_IN : in std_logic_vector(31 downto 0);
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DATA_OUT : out std_logic_vector(31 downto 16);
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DATA_EN_H : out std_logic;
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DATA_EN_L : out std_logic
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);
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end component;
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begin
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t : DDR_CTRL_V1
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port map
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(
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CLK_MAIN => clock,
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vec_in => vec,
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vec_out => o
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);
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stimulate_clock : process
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begin
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wait for 5 ps;
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clock <= not clock;
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end process;
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stimulate : process
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begin
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vec <= "00000000000000000000000000000001";
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wait for 20 ps;
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vec <= "10000000000000000000000000000000";
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wait for 20 ps;
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vec <= "00000000000000000000000000000101";
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wait for 20 ps;
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end process;
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end beh;
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