214 lines
8.0 KiB
VHDL
214 lines
8.0 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- ATARI MFP compatible IP Core ----
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---- ----
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---- This file is part of the SUSKA ATARI clone project. ----
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---- http://www.experiment-s.de ----
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---- ----
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---- Description: ----
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---- MC68901 compatible multi function port core. ----
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---- ----
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---- This is the SUSKA MFP IP core top level file. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006 Wolfgang Foerster ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K6A 2006/06/03 WF
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-- Initial Release.
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-- Revision 2K6B 2006/11/07 WF
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-- Modified Source to compile with the Xilinx ISE.
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-- Revision 2K7A 2006/12/28 WF
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-- The timer is modified to work on the CLK instead
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-- of XTAL1. This modification is done to provide
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-- a synchronous design.
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-- Revision 2K8B 2008/12/24 WF
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-- Rewritten this top level file as a wrapper for the top_soc file.
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--
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use work.wf68901ip_pkg.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity WF68901IP_TOP is
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port ( -- System control:
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CLK : in bit;
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RESETn : in bit;
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-- Asynchronous bus control:
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DSn : in bit;
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CSn : in bit;
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RWn : in bit;
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DTACKn : out std_logic;
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-- Data and Adresses:
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RS : in bit_vector(5 downto 1);
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DATA : inout std_logic_vector(7 downto 0);
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GPIP : inout std_logic_vector(7 downto 0);
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-- Interrupt control:
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IACKn : in bit;
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IEIn : in bit;
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IEOn : out bit;
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IRQn : out std_logic;
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-- Timers and timer control:
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XTAL1 : in bit; -- Use an oszillator instead of a quartz.
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TAI : in bit;
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TBI : in bit;
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TAO : out bit;
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TBO : out bit;
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TCO : out bit;
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TDO : out bit;
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-- Serial I/O control:
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RC : in bit;
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TC : in bit;
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SI : in bit;
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SO : out std_logic;
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-- DMA control:
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RRn : out bit;
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TRn : out bit
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);
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end entity WF68901IP_TOP;
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architecture STRUCTURE of WF68901IP_TOP is
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component WF68901IP_TOP_SOC
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port(CLK : in bit;
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RESETn : in bit;
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DSn : in bit;
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CSn : in bit;
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RWn : in bit;
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DTACKn : out bit;
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RS : in bit_vector(5 downto 1);
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DATA_IN : in std_logic_vector(7 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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DATA_EN : out bit;
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GPIP_IN : in bit_vector(7 downto 0);
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GPIP_OUT : out bit_vector(7 downto 0);
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GPIP_EN : out bit_vector(7 downto 0);
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IACKn : in bit;
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IEIn : in bit;
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IEOn : out bit;
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IRQn : out bit;
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XTAL1 : in bit;
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TAI : in bit;
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TBI : in bit;
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TAO : out bit;
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TBO : out bit;
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TCO : out bit;
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TDO : out bit;
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RC : in bit;
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TC : in bit;
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SI : in bit;
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SO : out bit;
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SO_EN : out bit;
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RRn : out bit;
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TRn : out bit
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);
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end component;
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--
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signal DTACK_In : bit;
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signal IRQ_In : bit;
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signal DATA_OUT : std_logic_vector(7 downto 0);
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signal DATA_EN : bit;
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signal GPIP_IN : bit_vector(7 downto 0);
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signal GPIP_OUT : bit_vector(7 downto 0);
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signal GPIP_EN : bit_vector(7 downto 0);
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signal SO_I : bit;
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signal SO_EN : bit;
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begin
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DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain.
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IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
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DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
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GPIP_IN <= To_BitVector(GPIP);
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P_GPIP_OUT: process(GPIP_OUT, GPIP_EN)
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begin
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for i in 7 downto 0 loop
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if GPIP_EN(i) = '1' then
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case GPIP_OUT(i) is
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when '0' => GPIP(i) <= '0';
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when others => GPIP(i) <= '1';
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end case;
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else
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GPIP(i) <= 'Z';
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end if;
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end loop;
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end process P_GPIP_OUT;
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SO <= '0' when SO_I = '0' and SO_EN = '1' else
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'1' when SO_I = '1' and SO_EN = '1' else 'Z';
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I_MFP: WF68901IP_TOP_SOC
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port map(CLK => CLK,
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RESETn => RESETn,
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DSn => DSn,
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CSn => CSn,
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RWn => RWn,
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DTACKn => DTACK_In,
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RS => RS,
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DATA_IN => DATA,
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DATA_OUT => DATA_OUT,
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DATA_EN => DATA_EN,
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GPIP_IN => GPIP_IN,
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GPIP_OUT => GPIP_OUT,
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GPIP_EN => GPIP_EN,
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IACKn => IACKn,
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IEIn => IEIn,
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IEOn => IEOn,
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IRQn => IRQ_In,
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XTAL1 => XTAL1,
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TAI => TAI,
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TBI => TBI,
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TAO => TAO,
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TBO => TBO,
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TCO => TCO,
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TDO => TDO,
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RC => RC,
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TC => TC,
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SI => SI,
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SO => SO_I,
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SO_EN => SO_EN,
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RRn => RRn,
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TRn => TRn
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);
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end architecture STRUCTURE;
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