356 lines
11 KiB
C
356 lines
11 KiB
C
/*
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* pci.c
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*
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* Purpose: PCI configuration for the Coldfire builtin PCI bridge.
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*
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* Notes:
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Created on: 08.01.2013
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* Author: Markus Froeschle
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*/
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#include <MCF5475.h>
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#include "pci.h"
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#include "stdint.h"
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#include "bas_printf.h"
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#include "util.h"
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#include "wait.h"
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static struct pci_class
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{
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int classcode;
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char *description;
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} pci_classes[] =
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{
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{ 0x00, "device was built prior definition of the class code field" },
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{ 0x01, "Mass Storage Controller" },
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{ 0x02, "Network Controller" },
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{ 0x03, "Display Controller" },
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{ 0x04, "Multimedia Controller" },
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{ 0x05, "Memory Controller" },
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{ 0x06, "Bridge Device" },
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{ 0x07, "Simple Communication Controller" },
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{ 0x08, "Base System Peripherial" },
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{ 0x09, "Input Device" },
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{ 0x0a, "Docking Station" },
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{ 0x0b, "Processor" },
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{ 0x0c, "Serial Bus Controller" },
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{ 0x0d, "Wireless Controller" },
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{ 0x0e, "Intelligent I/O Controller" },
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{ 0x0f, "Satellite Communication Controller" },
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{ 0x10, "Encryption/Decryption Controller" },
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{ 0x11, "Data Acquisition and Signal Processing Controller" },
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{ 0xff, "Device does not fit any defined class" },
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};
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static int num_classes = sizeof(pci_classes) / sizeof(struct pci_class);
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static char *device_class(int classcode)
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{
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int i;
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for (i = 0; i < num_classes; i++)
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{
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if (pci_classes[i].classcode == classcode)
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{
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return pci_classes[i].description;
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}
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}
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return "not found";
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}
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uint32_t pci_read_config_longword(uint16_t bus, uint16_t slot, uint16_t function, uint16_t offset)
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{
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uint32_t value;
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/* clear PCI status/command register */
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MCF_PCI_PCISCR = MCF_PCI_PCISCR_PE | /* clear parity error bit */
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MCF_PCI_PCISCR_SE | /* clear system error */
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MCF_PCI_PCISCR_MA | /* clear master abort */
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MCF_PCI_PCISCR_TR | /* clear target abort */
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MCF_PCI_PCISCR_TS | /* clear target abort signalling (as target) */
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MCF_PCI_PCISCR_DP; /* clear parity error */
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//(void) MCF_PCI_PCISCR;
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wait(1000);
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//xprintf("PCISCR before config cycle: %lx\r\n", MCF_PCI_PCISCR);
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/* initiate PCI configuration access to device */
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MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
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MCF_PCI_PCICAR_BUSNUM(bus) |
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MCF_PCI_PCICAR_DEVNUM(slot) | /* device number, devices 0 - 9 are reserved */
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_DWORD(offset / 4);
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wait(1000);
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value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
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swpl(value);
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//xprintf("PCISCR after config cycle: %lx\r\n", MCF_PCI_PCISCR);
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return value;
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}
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uint16_t pci_read_config_word(uint16_t bus, uint16_t slot, uint16_t function, uint16_t offset)
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{
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uint32_t value;
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value = pci_read_config_longword(bus, slot, function, offset / 2);
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return((value >> (1 - offset % 2) * 8) & 0xffff);
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}
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uint8_t pci_read_config_byte(uint16_t bus, uint16_t slot, uint16_t function, uint16_t offset)
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{
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uint32_t value;
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value = pci_read_config_longword(bus, slot, function, offset / 4);
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return ((value >> (3 - offset % 4) * 8) & 0xff);
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}
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void pci_write_config_longword(uint16_t bus, uint16_t slot, uint16_t function, uint16_t offset, uint32_t value)
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{
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/* clear PCI status/command register */
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MCF_PCI_PCISCR = MCF_PCI_PCISCR_PE | /* clear parity error bit */
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MCF_PCI_PCISCR_SE | /* clear system error */
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MCF_PCI_PCISCR_MA | /* clear master abort */
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MCF_PCI_PCISCR_TR | /* clear target abort */
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MCF_PCI_PCISCR_TS | /* clear target abort signalling (as target) */
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MCF_PCI_PCISCR_DP; /* clear parity error */
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//(void) MCF_PCI_PCISCR;
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wait(1000);
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//xprintf("PCISCR before config cycle: %lx\r\n", MCF_PCI_PCISCR);
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/* initiate PCI configuration access to device */
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MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
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MCF_PCI_PCICAR_BUSNUM(bus) |
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MCF_PCI_PCICAR_DEVNUM(slot) | /* device number, devices 0 - 9 are reserved */
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_DWORD(offset / 4);
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wait(1000);
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swpl(value);
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* (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */
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}
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int pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
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{
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uint16_t bus;
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uint16_t slot;
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uint16_t function;
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uint16_t pos = 0;
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int handle;
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for (bus = 0; bus < 1; bus++)
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{
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for (slot = 0; slot < 32; slot++)
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{
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for (function = 0; function < 8; function++)
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{
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uint32_t value;
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value = pci_read_config_longword(bus, slot, function, 0);
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handle = bus << 16 | slot << 8 | function;
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if (value != 0xffffffff) /* we have a device at this position */
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{
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if (vendor_id == 0xffff) /* ignore vendor id */
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{
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return handle;
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}
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else if (PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id)
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{
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if (pos == index)
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return handle;
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pos++;
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}
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}
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}
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}
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}
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return PCI_DEVICE_NOT_FOUND;
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}
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static uint32_t mem_address = PCI_MEMORY_OFFSET;
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static uint32_t io_address = PCI_IO_OFFSET;
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void pci_device_config(uint16_t bus, uint16_t slot, uint16_t function)
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{
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uint32_t address;
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int i;
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for (i = 0; i < 6; i++) /* for all bars */
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{
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uint32_t value;
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value = pci_read_config_longword(bus, slot, function, 0x10 + i); /* read BAR value */
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pci_write_config_longword(bus, slot, function, 0x10 + i, 0xffffffff); /* write all bits */
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address = pci_read_config_longword(bus, slot, function, 0x10 + i); /* read back value */
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if (address) /* is bar in use? */
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{
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//xprintf("%s region found with base address %08x, size = %x\r\n",
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//(IS_PCI_MEM_BAR(value) ? "Memory" : "I/O"),
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//(IS_PCI_MEM_BAR(value) ? PCI_MEMBAR_ADR(value) : PCI_IOBAR_ADR(value)),
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//(IS_PCI_MEM_BAR(value) ? ~(address & 0xfffffff0) + 1 : ~(address & 0xfffffffc) + 1));
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/* adjust base address to alignment requirements */
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if (IS_PCI_MEM_BAR(value))
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{
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int size = ~(address & 0xfffffff0) + 1;
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mem_address = (mem_address + size - 1) & ~(size - 1);
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pci_write_config_longword(bus, slot, function, 0x10 + i, mem_address);
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value = pci_read_config_longword(bus, slot, function, 0x10 + i);
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xprintf("BAR[%d] configured to %08x, size %x\r\n", i, value, size);
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mem_address += size;
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}
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else if (IS_PCI_IO_BAR(value))
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{
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int size = ~(address & 0xfffffffc) + 1;
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io_address = (io_address + size - 1) & ~(size - 1);
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pci_write_config_longword(bus, slot, function, 0x10 + i, io_address);
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value = pci_read_config_longword(bus, slot, function, 0x10 + i);
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xprintf("BAR[%d] mapped to %08x, size %x\r\n", i, value, size);
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io_address += size;
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}
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}
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}
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}
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void pci_scan(void)
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{
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uint16_t bus;
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uint16_t slot;
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uint16_t function;
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uint16_t i;
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xprintf("\r\nPCI bus scan...\r\n\r\n");
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xprintf(" Bus|Slot|Func|Vndr|Dev |\r\n");
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xprintf("----+----+----|----+----|\r\n");
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for (bus = 0; bus < 1; bus++)
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{
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for (slot = 0; slot < 32; slot++)
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{
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for (function = 0; function < 8; function++)
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{
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uint32_t value;
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value = pci_read_config_longword(bus, slot, function, 0);
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if (value != 0xffffffff)
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{
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xprintf(" %02x | %02x | %02x |%04x|%04x| %s\r\n", bus, slot, function,
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PCI_VENDOR_ID(value),
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PCI_DEVICE_ID(value),
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device_class(pci_read_config_longword(bus, slot, function, 0x08) >> 24 & 0xff));
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if (PCI_VENDOR_ID(value) != 0x1057 && PCI_DEVICE_ID(value) != 0x5806) /* do not configure bridge */
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{
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pci_device_config(bus, slot, function);
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}
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for (i = 0; i < 0x40; i += 4)
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{
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value = pci_read_config_longword(bus, slot, function, i);
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//xprintf("register %02x value= %08x\r\n", i, value);
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}
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/* test for multi-function device to avoid ghost device detects */
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value = pci_read_config_longword(bus, slot, function, 0x0c);
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if (function == 0 && !(PCI_HEADER_TYPE(value) & 0x80)) /* no multi function device */
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function = 8;
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}
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}
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}
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}
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xprintf("\r\n...finished\r\n");
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}
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/* start of PCI initialization code */
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void init_eport(void)
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{
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/* concigure IRQ1-7 pins on EPORT falling edge triggered */
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MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA6(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA4(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA2(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA1(MCF_EPORT_EPPAR_FALLING);
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MCF_EPORT_EPDDR = 0; /* clear data direction register. All pins as input */
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MCF_EPORT_EPFR = 0; /* clear all EPORT interrupt flags */
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MCF_EPORT_EPIER = 0; /* disable all EPORT interrupts (for now) */
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}
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void init_xlbus_arbiter(void)
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{
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uint8_t clock_ratio;
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/* setup XL bus arbiter */
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clock_ratio = (MCF_PCI_PCIGSCR >> 24) & 0x07;
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if (clock_ratio == 4)
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{
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/* device errata 26: Flexbus hang up in 4:1 clock ratio */
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MCF_PCI_PCIGSCR |= 0x80000000; /* disable pipeline */
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}
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/* FIXME: Firetos (boot2.S, l. 719) looks pretty strange at this place - is this a typo? */
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}
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void init_pci(void)
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{
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xprintf("initializing PCI bridge:");
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MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI
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+ MCF_PCIARB_PACR_EXTMPRI(0x1F)
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+ MCF_PCIARB_PACR_INTMINTEN
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+ MCF_PCIARB_PACR_EXTMINTEN(0x1F);
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/* Setup burst parameters */
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MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32);
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MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16);
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/* Turn on error signaling */
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MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_REE + 32;
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MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE;
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/* Configure Initiator Windows */
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/* initiator window 0 base / translation adress register */
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MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE -1) >> 8)) & 0xffff0000;
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/* initiator window 1 base / translation adress register */
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MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000;
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/* initiator window 2 base / translation address register */
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MCF_PCI_PCIIW2BTAR = 0L; /* not used */
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/* initiator window configuration register */
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MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO;
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/* reset PCI devices */
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MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
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xprintf("finished\r\n");
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pci_scan();
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}
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