309 lines
15 KiB
VHDL
309 lines
15 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY work;
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PACKAGE ddr_ram_model_pkg IS
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COMPONENT ddr_ram_model IS
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GENERIC
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(
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick
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NBANK : INTEGER := 4;
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ADDRTOP : INTEGER := 12;
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A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10
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B : INTEGER := 16; -- number of bit (x16)
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NCOL : INTEGER := 10; -- top column address is CA9 (NCOL- 1)
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PAGEDEPTH : INTEGER := 1024;
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NDM : INTEGER := 2;
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NDQS : INTEGER := 2
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);
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PORT
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(
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dqi : INOUT std_logic_vector (B - 1 DOWNTO 0);
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ba : IN unsigned (NBANK / 2 - 1 DOWNTO 0);
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ad : IN std_logic_vector (ADDRTOP DOWNTO 0);
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rasb : IN std_logic;
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casb : IN std_logic;
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web : IN std_logic;
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clk : IN std_logic;
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clkb : IN std_logic;
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cke : IN std_logic;
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csb : IN std_logic;
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dm : IN unsigned (NDM - 1 DOWNTO 0);
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dqs : INOUT std_logic_vector (NDQS - 1 DOWNTO 0);
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qfc : OUT std_logic
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);
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END COMPONENT;
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END PACKAGE;
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PACKAGE BODY ddr_ram_model_pkg IS
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END PACKAGE BODY ddr_ram_model_pkg;
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---------------------------------------------------------------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY work;
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USE work.ddr_ram_model_pkg.ALL;
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ENTITY ddr_ram_model IS
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GENERIC
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(
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick
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NBANK : INTEGER := 4;
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ADDRTOP : INTEGER := 12;
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A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10
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B : INTEGER := 16; -- number of bit (x16)
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NCOL : INTEGER := 10; -- top column address is CA9 (NCOL - 1)
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PAGEDEPTH : INTEGER := 1024;
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NDM : INTEGER := 2;
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NDQS : INTEGER := 2
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);
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PORT
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(
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dqi : INOUT std_logic_vector (B - 1 DOWNTO 0);
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ba : IN unsigned (NBANK / 2 - 1 DOWNTO 0);
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ad : IN std_logic_vector (ADDRTOP DOWNTO 0);
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rasb : IN std_logic;
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casb : IN std_logic;
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web : IN std_logic;
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clk : IN std_logic;
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clkb : IN std_logic;
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cke : IN std_logic;
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csb : IN std_logic;
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dm : IN unsigned (NDM - 1 DOWNTO 0);
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dqs : INOUT std_logic_vector (NDQS - 1 DOWNTO 0);
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qfc : OUT std_logic
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);
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END ENTITY ddr_ram_model;
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ARCHITECTURE rtl OF ddr_ram_model IS
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-- DDR RAM timing constants
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CONSTANT TRC : TIME := 65 ps; -- row cycle time (min)
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CONSTANT TRFC : TIME := 115 ps; -- Refresh Row cycle time (min)
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CONSTANT TRASMIN : TIME := 45 ps; -- Row active minimum time
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CONSTANT TRASMAX : TIME := 120000 ps; -- Row active maximum time
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CONSTANT TRCD : TIME := 20 ps; -- Ras to cas delay (min)
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CONSTANT TRP : TIME := 20 ps; -- Row precharge time (min)
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CONSTANT TRRD : TIME := 15 ps; -- Row to row delay (min)
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CONSTANT TCCD : TIME := CLOCK_TICK; -- Col. address to col. address delay: 1 clk
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CONSTANT TCKMIN : TIME := 7.5 ps; -- Clock minimum cycle time
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CONSTANT TCKMAX : TIME := 12 ps; -- Clock maximum cycle time
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CONSTANT TCK15 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=1.5
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CONSTANT TCK2 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=2
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CONSTANT TCK25 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=2.5
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CONSTANT TCK3 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=3
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CONSTANT TCHMIN : TIME := 0.45 ps; -- Clock high pulse width (min. 0.45 tCK, max: 0.55 tCK)
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CONSTANT TCHMAX : TIME := 0.55 ps;
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CONSTANT TCLMIN : TIME := 0.45 ps; -- Clock low pulse width (min. 0.45 tCK, max: 0.55 tCK)
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CONSTANT TCLMAX : TIME := 0.55 ps;
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CONSTANT TIS : TIME := 0.9 ps; -- input setup time (old Tss)
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CONSTANT TIH : TIME := 0.9 ps; -- input hold time (old Tsh)
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CONSTANT TWR : TIME := 15 ps; -- write recovery time
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CONSTANT TDS : TIME := 0.5 ps; -- Data in & DQM setup time
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CONSTANT TDH : TIME := 0.5 ps; -- Data in & DQM hold time
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CONSTANT TDQSH : TIME := 0.6 ps; -- DQS-in high level width (min. 0.4 tCK, max. 0.6 tCK)
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CONSTANT TDQSL : TIME := 0.6 ps; --
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CONSTANT TDSC : TIME := 1 ps; -- DQS-in cycle time tCIC changed following tDSC
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CONSTANT TPDEX : TIME := 7.5 ps; -- Power down exit time
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CONSTANT TSREX : TIME := 200 ps; -- Self refresh exit time : 200 clk
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CONSTANT THZQ : TIME := 0.75 ps; -- Data out active to High-Z (min:-0.75, max: +0.75)
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CONSTANT TDQSCK : TIME := 0.75 ps; -- DQS out edge to clock edge
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CONSTANT TAC : TIME := 0.75 ps; -- Output data access time from CK/CKB (min: -0.75, max: +0.75)
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CONSTANT TQCSW : TIME := 3.5 ps; -- Delay from the clock edge of write command to QFC out on writes (max: 4ns)
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CONSTANT TQCHW : TIME := 0.5 ps; -- QFC hold time on writes (min 1.25 ns, max: 0.5 tCK)
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CONSTANT TQCH : TIME := 0.4 ps; -- QFC hold time on reads (min 0.4 tCK, max 0.6 tCK)
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CONSTANT TQCS : TIME := 0.9 ps; -- QFC setup time on reads (min: 0.9 tCK, max 1.1 tCK)
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CONSTANT K1 : INTEGER := 1024;
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CONSTANT M1 : INTEGER := 1048576;
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CONSTANT BYTE : INTEGER := 8;
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CONSTANT TBITS : INTEGER := 512 * M1;
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--SIGNAL BITs : unsigned (B - 1 DOWNTO 0);
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CONSTANT BIT_C : INTEGER := NCOL - 1;
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CONSTANT NWORD : INTEGER := TBITS / B / NBANK;
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CONSTANT BIT_T : INTEGER := NCOL + ADDRTOP;
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CONSTANT WORD : INTEGER := NWORD - 1;
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CONSTANT HB : INTEGER := B / 2;
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CONSTANT PWRUP_TIME : INTEGER := 0;
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CONSTANT PWUP_CHECK : std_logic := '1';
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CONSTANT INITIAL : INTEGER := 0;
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CONSTANT HIGH : INTEGER := 1;
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CONSTANT LOW : INTEGER := 0;
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SIGNAL addr : std_logic_vector (NBANK / 2 + ADDRTOP DOWNTO 0);
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TYPE mem_array_t IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(B - 1 DOWNTO 0);
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SIGNAL mem_a : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of a bank
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SIGNAL mem_b : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of b bank
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SIGNAL mem_c : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of c bank
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SIGNAL mem_d : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of d bank
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SIGNAL t_dqi : unsigned (B - 1 DOWNTO 0);
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SIGNAL dqsi : unsigned (NDQS - 1 DOWNTO 0);
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SIGNAL dqsi_n : unsigned (NDQS - 1 DOWNTO 0);
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SIGNAL dqo : unsigned (B - 1 DOWNTO 0); -- output temp register declaration
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SIGNAL t_tqo : unsigned (B - 1 DOWNTO 0);
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TYPE r_addr_t IS ARRAY (NATURAL RANGE <>) OF unsigned (NBANK - 1 DOWNTO 0);
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SIGNAL r_addr_n : r_addr_t (ADDRTOP DOWNTO 0);
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SIGNAL r_addr : unsigned (ADDRTOP DOWNTO 0);
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SIGNAL c_addr : unsigned (BIT_C DOWNTO 0);
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SIGNAL c_addr_delay : unsigned (BIT_C DOWNTO 0);
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SIGNAL c_addr_delay_bf : unsigned (BIT_C DOWNTO 0);
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SIGNAL m_addr : unsigned (BIT_T DOWNTO 0); -- merge row and column address
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SIGNAL m1_addr : unsigned (BIT_T DOWNTO 0); -- merge row and column address pseudo
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TYPE d_reg_t IS ARRAY (NATURAL RANGE <>) OF unsigned (PAGEDEPTH DOWNTO 0);
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SIGNAL dout_reg : unsigned (B - 1 DOWNTO 0);
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SIGNAL din_reg : unsigned (B - 1 DOWNTO 0);
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SIGNAL clk_dq : unsigned (B - 1 DOWNTO 0);
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SIGNAL ptr : std_logic;
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SIGNAL zdata : unsigned(B - 1 DOWNTO 0);
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SIGNAL zbyte : unsigned(7 DOWNTO 0);
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-- we know the phase of external signal by examining the state of its flag
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SIGNAL r_bank_addr : std_logic;
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SIGNAL c_bank_addr : unsigned (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag
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SIGNAL c_bank_addr_delay : unsigned (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag
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SIGNAL c_bank_addr_delay_bf : unsigned (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag
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SIGNAL prech_reg : unsigned (NBANK / 2 DOWNTO 0); -- precharge mode (addr (13 DOWNTO 12) AND (addr(10))
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SIGNAL auto_flag : BOOLEAN_VECTOR (NBANK - 1 DOWNTO 0);
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SIGNAL burst_type : std_logic; -- burst type flag
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SIGNAL auto_flagx : BOOLEAN; -- auto refresh flag
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SIGNAL self_flag : BOOLEAN; -- self refresh flag
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SIGNAL kill_bank : INTEGER;
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SIGNAL k : INTEGER;
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SIGNAL precharge_flag : unsigned (NBANK - 1 DOWNTO 0); -- precharge bank check flag
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SIGNAL autoprech_reg : unsigned (1 DOWNTO 0);
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SIGNAL pwrup_done : BOOLEAN;
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SIGNAL first_pre : BOOLEAN_VECTOR (NBANK - 1 DOWNTO 0);
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SIGNAL auto_cnt : INTEGER;
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SIGNAL i : INTEGER;
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SIGNAL rfu : unsigned (6 DOWNTO 0);
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SIGNAL mode : unsigned (NBANK - 1 DOWNTO 0);
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SIGNAL prdl : unsigned (NBANK - 1 DOWNTO 0);
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SIGNAL ignore_rdl : unsigned (NBANK - 1 DOWNTO 0);
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SIGNAL bl : INTEGER; -- burst_length
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SIGNAL wbl : INTEGER;
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SIGNAL cl : INTEGER; -- CAS latency
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SIGNAL cl_tmp : INTEGER;
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SIGNAL cl_org : INTEGER;
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SIGNAL cl_tmp2 : INTEGER;
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SIGNAL write_event : BOOLEAN;
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SIGNAL autoprecharge_WIRevent : BOOLEAN;
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SIGNAL write_mode_flag : BOOLEAN;
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SIGNAL dqsi_flag : BOOLEAN;
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SIGNAL dqsi_flag_u : BOOLEAN;
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SIGNAL write_start : BOOLEAN;
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SIGNAL tdss_min : INTEGER;
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SIGNAL tdss_max : INTEGER;
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SIGNAL tshz : INTEGER; -- clk to output in hi-z
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SIGNAL tsac : INTEGER; -- clk to valid output
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SIGNAL reautoprecharge : BOOLEAN;
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TYPE event_record_t IS RECORD
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kkk_event : BOOLEAN;
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read_event : BOOLEAN;
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write_event : BOOLEAN;
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write_pre_event : BOOLEAN;
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write_mode_event : BOOLEAN;
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write_mode_del_event : BOOLEAN;
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write_task_event : BOOLEAN;
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flush_write_event : BOOLEAN;
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precharge_event : BOOLEAN;
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autoprecharge_event : BOOLEAN;
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autoprecharge_a_event : BOOLEAN;
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autoprecharge_b_event : BOOLEAN;
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autoprecharge_c_event : BOOLEAN;
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autoprecharge_d_event : BOOLEAN;
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autoprecharge_write_event : BOOLEAN;
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autoprecharge_write_a_event : BOOLEAN;
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autoprecharge_write_b_event : BOOLEAN;
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autoprecharge_write_c_event : BOOLEAN;
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autoprecharge_write_d_event : BOOLEAN;
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autoprecharge_write_int_event : BOOLEAN;
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autoprecharge_write_int2_event : BOOLEAN;
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precharge_start_event : BOOLEAN;
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precharge_start_kill_event : BOOLEAN;
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autorefresh_event : BOOLEAN;
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autostart_event : BOOLEAN;
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selfrefresh_event : BOOLEAN;
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selfexit_event : BOOLEAN;
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rdl_start_a_event : BOOLEAN;
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rdl_start_b_event : BOOLEAN;
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rdl_start_c_event : BOOLEAN;
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rdl_start_d_event : BOOLEAN;
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END RECORD;
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SIGNAL events : event_record_t;
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BEGIN
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p_initial : PROCESS
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BEGIN
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FOR i IN 0 TO NDQS - 1 LOOP
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dqs(i) <= '1';
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END LOOP;
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FOR i IN 0 TO NBANK LOOP
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auto_flag(i) <= FALSE;
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END LOOP;
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auto_flagx <= FALSE;
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reautoprecharge <= FALSE;
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self_flag <= FALSE;
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events.write_event <= FALSE;
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autoprecharge_WIRevent <= FALSE;
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write_mode_flag <= FALSE;
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pwrup_done <= FALSE;
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dqsi_flag <= FALSE;
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dqsi_flag_u <= FALSE;
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mode <= TO_UNSIGNED(0, mode'LENGTH) OR TO_UNSIGNED(NBANK, 3)(0);
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prdl <= TO_UNSIGNED(0, mode'LENGTH) OR TO_UNSIGNED(NBANK, 3)(0);
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FOR i IN 0 TO NBANK LOOP
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first_pre(i) <= FALSE;
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precharge_flag(i) <= FALSE;
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END LOOP;
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zbyte <= (OTHERS => 'Z');
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FOR i IN 0 TO B LOOP
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zdata(i) <= '1';
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END LOOP;
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WAIT;
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END PROCESS p_initial;
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addr <= std_logic_vector(ba) & ad;
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rfu <= unsigned(addr(14 DOWNTO 9)) & unsigned(addr(7 DOWNTO 7));
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END rtl;
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