118 lines
3.5 KiB
VHDL
118 lines
3.5 KiB
VHDL
------------------------------------------------------------------------------
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--! @file
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--! @author Matthias Alles
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--! @date 01/2009
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--! @brief Top entity of DSP
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--!
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.parameter_pkg.all;
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use work.types_pkg.all;
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use work.constants_pkg.all;
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entity dsp56k is port (
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clk, rst : in std_logic;
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-- put register file here for synthesis!
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register_file : out register_file_type
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-- port_a_in : in port_a_in_type;
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-- port_a_out : out port_a_out_type;
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-- port_b_in : in port_b_in_type;
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-- port_b_out : out port_b_out_type;
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-- port_c_in : in port_c_in_type;
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-- port_c_out : out port_c_out_type;
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);
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end dsp56k;
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architecture rtl of dsp56k is
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component pipeline is port (
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clk, rst : in std_logic;
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register_file_out : out register_file_type;
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stall_flags_out : out std_logic_vector(PIPELINE_DEPTH-1 downto 0);
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memory_stall : in std_logic;
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data_rom_enable: out std_logic;
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pmem_ctrl_in : out mem_ctrl_type_in;
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pmem_ctrl_out : in mem_ctrl_type_out;
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pmem2_ctrl_in : out mem_ctrl_type_in;
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pmem2_ctrl_out : in mem_ctrl_type_out;
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xmem_ctrl_in : out mem_ctrl_type_in;
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xmem_ctrl_out : in mem_ctrl_type_out;
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ymem_ctrl_in : out mem_ctrl_type_in;
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ymem_ctrl_out : in mem_ctrl_type_out
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);
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end component pipeline;
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component memory_management is port (
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clk, rst : in std_logic;
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stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0);
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memory_stall : out std_logic;
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data_rom_enable: in std_logic;
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pmem_ctrl_in : in mem_ctrl_type_in;
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pmem_ctrl_out : out mem_ctrl_type_out;
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pmem2_ctrl_in : in mem_ctrl_type_in;
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pmem2_ctrl_out : out mem_ctrl_type_out;
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xmem_ctrl_in : in mem_ctrl_type_in;
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xmem_ctrl_out : out mem_ctrl_type_out;
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ymem_ctrl_in : in mem_ctrl_type_in;
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ymem_ctrl_out : out mem_ctrl_type_out
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);
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end component memory_management;
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signal stall_flags : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
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signal memory_stall : std_logic;
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signal data_rom_enable : std_logic;
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signal pmem_ctrl_in : mem_ctrl_type_in;
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signal pmem_ctrl_out : mem_ctrl_type_out;
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signal pmem2_ctrl_in : mem_ctrl_type_in;
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signal pmem2_ctrl_out : mem_ctrl_type_out;
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signal xmem_ctrl_in : mem_ctrl_type_in;
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signal xmem_ctrl_out : mem_ctrl_type_out;
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signal ymem_ctrl_in : mem_ctrl_type_in;
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signal ymem_ctrl_out : mem_ctrl_type_out;
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begin
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pipeline_inst : pipeline port map(
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clk => clk,
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rst => rst,
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register_file_out => register_file,
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stall_flags_out => stall_flags,
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memory_stall => memory_stall,
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data_rom_enable => data_rom_enable,
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pmem_ctrl_in => pmem_ctrl_in,
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pmem_ctrl_out => pmem_ctrl_out,
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pmem2_ctrl_in => pmem2_ctrl_in,
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pmem2_ctrl_out => pmem2_ctrl_out,
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xmem_ctrl_in => xmem_ctrl_in,
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xmem_ctrl_out => xmem_ctrl_out,
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ymem_ctrl_in => ymem_ctrl_in,
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ymem_ctrl_out => ymem_ctrl_out
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);
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---------------------
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-- MEMORY MANAGEMENT
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---------------------
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MMU_inst: memory_management port map (
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clk => clk,
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rst => rst,
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stall_flags => stall_flags,
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memory_stall => memory_stall,
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data_rom_enable => data_rom_enable,
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pmem_ctrl_in => pmem_ctrl_in,
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pmem_ctrl_out => pmem_ctrl_out,
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pmem2_ctrl_in => pmem2_ctrl_in,
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pmem2_ctrl_out => pmem2_ctrl_out,
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xmem_ctrl_in => xmem_ctrl_in,
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xmem_ctrl_out => xmem_ctrl_out,
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ymem_ctrl_in => ymem_ctrl_in,
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ymem_ctrl_out => ymem_ctrl_out
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);
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end architecture rtl;
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