566 lines
15 KiB
C
566 lines
15 KiB
C
/*
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* BaS
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*/
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#include <bas_types.h>
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#include "MCF5475.h"
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#include "startcf.h"
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#include "sysinit.h"
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#include "util.h"
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#include "cache.h"
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#include "bas_printf.h"
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#include "bas_string.h"
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#include "bas_types.h"
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#include "bas_utils.h"
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#include "sd_card.h"
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#include "wait.h"
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#include "diskio.h"
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#include "ff.h"
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#include "s19reader.h"
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#include "mmu.h"
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#include "dma.h"
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#include "net.h"
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#include "eth.h"
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#include "nbuf.h"
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#include "nif.h"
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#include "fec.h"
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#include "bootp.h"
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#include "interrupts.h"
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#include "exceptions.h"
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#include "net_timer.h"
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#include "pci.h"
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#include "video.h"
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// // #define DEBUG
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#include "debug.h"
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/* imported routines */
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extern int vec_init();
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/* Symbols from the linker script */
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extern uint8_t _STRAM_END[];
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#define STRAM_END ((uint32_t)_STRAM_END)
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extern uint8_t _TOS[];
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#define TOS ((uint32_t)_TOS) /* final TOS location */
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extern uint8_t _FASTRAM_END[];
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#define FASTRAM_END ((uint32_t)_FASTRAM_END)
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extern uint8_t _EMUTOS[];
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#define EMUTOS ((uint32_t)_EMUTOS) /* where EmuTOS is stored in flash */
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extern uint8_t _EMUTOS_SIZE[];
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#define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */
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/*
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* check if it is possible to transfer data to PIC
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*/
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static inline bool pic_txready(void)
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{
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if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
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{
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return true;
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}
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return false;
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}
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/*
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* check if it is possible to receive data from PIC
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*/
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static inline bool pic_rxready(void)
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{
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if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
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{
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return true;
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}
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return false;
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}
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void write_pic_byte(uint8_t value)
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{
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/*
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* Wait until the transmitter is ready or 1000us are passed
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*/
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waitfor(1000, pic_txready);
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/*
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* Transmit the byte
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*/
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*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
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}
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uint8_t read_pic_byte(void)
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{
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/*
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* Wait until a byte has been received or 1000us are passed
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*/
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waitfor(1000, pic_rxready);
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/*
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* Return the received byte
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*/
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return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
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}
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void pic_init(void)
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{
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char answer[4] = "OLD";
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xprintf("initialize the PIC: ");
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/*
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* Send the PIC initialization string
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*/
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write_pic_byte('A');
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write_pic_byte('C');
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write_pic_byte('P');
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write_pic_byte('F');
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/*
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* Read the 3-char answer string. Should be "OK!".
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*/
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answer[0] = read_pic_byte();
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answer[1] = read_pic_byte();
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answer[2] = read_pic_byte();
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answer[3] = '\0';
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if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
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{
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dbg("PIC initialization failed. Already initialized?\r\n");
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}
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else
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{
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xprintf("%s\r\n", answer);
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}
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}
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void nvram_init(void)
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{
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int i;
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xprintf("Restore the NVRAM data: ");
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/* Request for NVRAM backup data */
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write_pic_byte(0x01);
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/* Check answer type */
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if (read_pic_byte() != 0x81)
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{
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// FIXME: PIC protocol error
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xprintf("FAILED\r\n");
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return;
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}
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/* Restore the NVRAM backup to the FPGA */
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for (i = 0; i < 64; i++)
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{
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uint8_t data = read_pic_byte();
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* (volatile uint8_t*) 0xffff8961 = i;
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* (volatile uint8_t*) 0xffff8963 = data;
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}
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xprintf("finished\r\n");
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}
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#define KBD_ACIA_CONTROL * ((uint8_t *) 0xfffffc00)
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#define MIDI_ACIA_CONTROL * ((uint8_t *) 0xfffffc04)
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#define MFP_INTR_IN_SERVICE_A * ((uint8_t *) 0xfffffa0f)
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#define MFP_INTR_IN_SERVICE_B * ((uint8_t *) 0xfffffa11)
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void acia_init()
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{
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xprintf("init ACIA: ");
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/* init ACIA */
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KBD_ACIA_CONTROL = 3; /* master reset */
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NOP();
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MIDI_ACIA_CONTROL = 3; /* master reset */
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NOP();
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KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
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NOP();
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MFP_INTR_IN_SERVICE_A = 0xff;
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NOP();
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MFP_INTR_IN_SERVICE_B = 0xff;
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NOP();
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xprintf("finished\r\n");
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}
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void enable_coldfire_interrupts()
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{
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xprintf("enable interrupts: ");
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#if defined(MACHINE_FIREBEE)
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FBEE_INTR_CONTROL = 0L; /* disable all interrupts */
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#endif /* MACHINE_FIREBEE */
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MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
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#ifdef _NOT_USED_
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#if defined(MACHINE_FIREBEE)
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/*
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* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
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* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
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*/
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MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
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MCF_GPT_GMS_IEN |
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MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */
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MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
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MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 6 */
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MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
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#endif
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#endif
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xprintf("finished\r\n");
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}
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void enable_pci_interrupts()
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{
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dbg("enable PCI interrupts\r\n");
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MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
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MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
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MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
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MCF_INTC_IMRH = 0;
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#if defined(MACHINE_FIREBEE)
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FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
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FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
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FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
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FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */
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FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
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FBEE_INTR_PCI_INTB |
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FBEE_INTR_PCI_INTC |
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FBEE_INTR_PCI_INTD;
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;
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#elif defined(MACHINE_M5484LITE)
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/*
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* MCF 5484 interrupts are configured at the CPLD for the FireEngine
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*/
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/* TODO: enable PCI interrupts on the LITEKIT */
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#elif defined(MACHINE_M54455)
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/* MCF 54455 interrupts are configured at the FPGA */
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/* TODO: enable PCI interrupts on the MCF54455 */
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#else
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#error unknown machine!
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#endif
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}
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void disable_coldfire_interrupts()
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{
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#if defined(MACHINE_FIREBEE)
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FBEE_INTR_ENABLE = 0; /* disable all interrupts */
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#endif /* MACHINE_FIREBEE */
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MCF_EPORT_EPIER = 0x0;
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MCF_INTC_IMRL = 0xfffffffe;
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MCF_INTC_IMRH = 0xffffffff;
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}
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NIF nif1;
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#if defined(MACHINE_M5484LITE)
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/*
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* on the MCF 5484 LITEKIT, the second FEC interface is usable
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*/
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NIF nif2;
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#endif
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bool spurious_interrupt_handler(void *arg1, void *arg2)
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{
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err("spurious interrupt\r\n");
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err("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
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err("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
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err("IRLR=%x\r\n", MCF_INTC_IRLR);
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return true;
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}
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/*
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* initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
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*/
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void init_isr(void)
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{
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isr_init(); /* need to call that explicitely, otherwise isr table might be full */
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/*
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* register spurious interrupt handler
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*/
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if (!isr_register_handler(24, 6, 6, spurious_interrupt_handler, NULL, NULL))
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{
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dbg("unable to register spurious interrupt handler\r\n");
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}
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/*
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* register the FEC interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1))
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{
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dbg("unable to register isr for FEC0\r\n");
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}
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/*
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* Register the DMA interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL))
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{
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dbg("unable to register isr for DMA\r\n");
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}
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#if defined(MACHINE_FIREBEE)
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/*
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* register GPT0 timer interrupt vector
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*/
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if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL))
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{
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dbg("unable to register isr for GPT0 timer\r\n");
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}
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/*
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* register the PIC interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register ISR for PSC3\r\n");
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}
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#endif /* MACHINE_FIREBEE */
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/*
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* register the XLB PCI interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 3, 0, xlbpci_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register isr for XLB PCI interrupts\r\n");
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}
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MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
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MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
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MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
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MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
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MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
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MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
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MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
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if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 0, pciarb_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register isr for PCIARB interrupts\r\n");
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return;
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}
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MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
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MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
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if (!isr_register_handler(64 + INT_SOURCE_XLBARB, 7, 1, xlbarb_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register isr for XLB ARB interrupts\r\n");
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}
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}
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/* Jump into the OS */
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typedef void void_func(void);
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struct rom_header
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{
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void *initial_sp;
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void_func *initial_pc;
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};
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/*
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* fix ST RAM header (address 0x0 and 0x4). FreeMiNT uses these vectors on CTRL-ALT-DEL.
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*
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* Beware: Newer compilers refuse to dereference pointers to NULL and abort if the following
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* attribute isn't set.
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*/
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static void fix_stram_header() __attribute__((optimize("no-delete-null-pointer-checks")));
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static void fix_stram_header()
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{
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struct rom_header *bas_header = (struct rom_header *) TARGET_ADDRESS;
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struct rom_header *stram_header = (struct rom_header *) 0x0;
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*stram_header = *bas_header;
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}
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void BaS(void)
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{
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uint8_t *src;
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uint8_t *dst = (uint8_t *) TOS;
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#if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */
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pic_init();
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nvram_init();
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#endif /* MACHINE_FIREBEE */
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xprintf("initialize MMU: ");
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mmu_init();
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xprintf("finished\r\n");
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xprintf("initialize Coldfire DMA: ");
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dma_init();
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xprintf("finished\r\n");
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xprintf("copy EmuTOS: ");
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/* copy EMUTOS */
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src = (uint8_t *) EMUTOS;
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memcpy(dst, src, EMUTOS_SIZE);
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xprintf("finished\r\n");
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xprintf("initialize exception vector table: ");
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vec_init();
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xprintf("finished\r\n");
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xprintf("flush caches: ");
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flush_and_invalidate_caches();
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xprintf("finished\r\n");
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xprintf("enable MMU: ");
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MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
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NOP(); /* force pipeline sync */
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xprintf("finished\r\n");
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#if defined(MACHINE_FIREBEE)
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xprintf("IDE reset: ");
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/* IDE reset */
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* (volatile uint8_t *) (0xffff8802 - 2) = 14;
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* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
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wait(1);
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* (volatile uint8_t *) (0xffff8802 - 0) = 0;
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xprintf("finished\r\n");
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xprintf("enable video: ");
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/*
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* video setup (25MHz)
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*/
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* (volatile uint32_t *) 0xf0000410 = 0x032002ba; /* horizontal 640x480 */
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* (volatile uint32_t *) 0xf0000414 = 0x020c020a; /* vertical 640x480 */
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* (volatile uint32_t *) 0xf0000418 = 0x0190015d; /* horizontal 320x240 */
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* (volatile uint32_t *) 0xf000041c = 0x020c020a; /* vertical 320x230 */
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/* fifo on, refresh on, ddrcs and cke on, video dac on */
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* (volatile uint32_t *) 0xf0000400 = 0x01070082;
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xprintf("finished\r\n");
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#endif /* MACHINE_FIREBEE */
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sd_card_init();
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/*
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* memory setup
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*/
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// memset((void *) 0x200, 0, 0x400);
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#if defined(MACHINE_FIREBEE)
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/* set Falcon bus control register */
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/* sets bit 3 and 6. Both are undefined on an original Falcon? */
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* (volatile uint8_t *) 0xffff8007 = 0x48;
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#endif /* MACHINE_FIREBEE */
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/* ST RAM */
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* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
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* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
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* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
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* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
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/* TT-RAM */
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* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
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* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
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#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
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acia_init();
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#endif /* MACHINE_FIREBEE */
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srec_execute("BASFLASH.S19");
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xprintf("BaS initialization finished, enable interrupts\r\n");
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init_isr();
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enable_coldfire_interrupts();
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MCF_INTC_IMRH = 0;
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MCF_INTC_IMRL = 0;
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dma_irq_enable();
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fec_irq_enable(0, 5, 1);
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enable_pci_interrupts();
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init_pci();
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video_init();
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|
|
|
/* initialize USB devices */
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|
// init_usb();
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|
|
|
set_ipl(7); /* disable interrupts */
|
|
|
|
/*
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|
* start FireTOS if DIP switch is set accordingly
|
|
*/
|
|
if (!(DIP_SWITCH & (1 << 6)))
|
|
{
|
|
extern uint8_t _FIRETOS[];
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|
#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */
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|
|
|
/* make sure MMU is disabled */
|
|
MCF_MMU_MMUCR = 0; /* MMU off */
|
|
NOP(); /* force pipeline sync */
|
|
|
|
|
|
/*
|
|
* FireTOS wants to have the TOS system variables cleared
|
|
*/
|
|
memset((void *) 0x400, 0, 0x400);
|
|
|
|
/* ST RAM */
|
|
|
|
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
|
|
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
|
|
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
|
|
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
|
|
|
|
/* TT-RAM */
|
|
|
|
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
|
|
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
|
|
|
|
xprintf("call FireTOS\r\n");
|
|
/* Jump into FireTOS */
|
|
|
|
void_func* FireTOS = (void_func*) FIRETOS;
|
|
FireTOS(); // Should never return
|
|
}
|
|
|
|
/*
|
|
* fix initial pc/sp in ST RAM for FreeMiNT. It expects valid values there
|
|
* like on original STs (where these values reside in ROM) and uses them on
|
|
* CTRL-ALT-DELETE reboots.
|
|
*/
|
|
fix_stram_header();
|
|
|
|
xprintf("call EmuTOS\r\n");
|
|
struct rom_header *os_header = (struct rom_header *) TOS;
|
|
os_header->initial_pc();
|
|
}
|