543 lines
13 KiB
C
543 lines
13 KiB
C
#include "mmu.h"
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#include "acia.h"
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/*
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* mmu.c
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* derived from original assembler sources:
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2013 M. Froeschle
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*/
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#include <stdint.h>
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#include "bas_printf.h"
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#include "bas_types.h"
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#include "MCF5475.h"
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#include "pci.h"
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#include "cache.h"
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#include "util.h"
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#if defined(MACHINE_FIREBEE)
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#include "firebee.h"
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#elif defined(MACHINE_M5484LITE)
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#include "m5484l.h"
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#elif defined(MACHINE_M54455)
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#include "m54455.h"
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#else
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#error "unknown machine!"
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#endif /* MACHINE_FIREBEE */
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#define DBG_MMU
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#ifdef DBG_MMU
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#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg);} while(0)
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#else
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#define dbg(format, arg...) do {;} while (0)
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#endif /* DBG_MMU */
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/*
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* set ASID register
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* saves new value to rt_asid and returns former value
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*/
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inline uint32_t set_asid(uint32_t value)
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{
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extern long rt_asid;
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uint32_t ret = rt_asid;
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__asm__ __volatile__(
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"movec %[value],ASID\n\t"
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: /* no output */
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: [value] "r" (value)
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:
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);
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rt_asid = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr0(uint32_t value)
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{
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extern uint32_t rt_acr0;
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uint32_t ret = rt_acr0;
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__asm__ __volatile__(
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"movec %[value],ACR0\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr0 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr1(uint32_t value)
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{
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extern uint32_t rt_acr1;
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uint32_t ret = rt_acr1;
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__asm__ __volatile__(
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"movec %[value],ACR1\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr1 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr2(uint32_t value)
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{
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extern uint32_t rt_acr2;
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uint32_t ret = rt_acr2;
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__asm__ __volatile__(
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"movec %[value],ACR2\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr2 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr3(uint32_t value)
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{
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extern uint32_t rt_acr3;
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uint32_t ret = rt_acr3;
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__asm__ __volatile__(
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"movec %[value],ACR3\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr3 = value;
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return ret;
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}
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inline uint32_t set_mmubar(uint32_t value)
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{
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extern uint32_t rt_mmubar;
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uint32_t ret = rt_mmubar;
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__asm__ __volatile__(
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"movec %[value],MMUBAR\n\t"
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: /* no output */
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: [value] "r" (value)
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: /* no clobber */
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);
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rt_mmubar = value;
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NOP();
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return ret;
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}
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/*
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* TODO: this would be nicer in an include file
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*/
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extern uint8_t _SYS_SRAM[];
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#define SYS_SRAM_ADDRESS ((uint32_t) &_SYS_SRAM[0])
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extern uint8_t _SYS_SRAM_SIZE[];
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extern uint8_t _FASTRAM_END[];
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struct mmu_mapping
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{
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uint32_t phys;
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uint32_t virt;
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uint32_t length;
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uint32_t pagesize;
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struct map_flags flags;
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};
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static struct mmu_mapping locked_map[] =
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{
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{
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/* Falcon video memory. Needs special care */
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0x60d00000,
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0xd00000,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_WRITETHROUGH, SV_USER, SCA_PAGE_ID, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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};
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static int num_locked_mmu_maps = sizeof(locked_map) / sizeof(struct mmu_mapping);
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static struct mmu_mapping memory_map[] =
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{
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/* map OS system vectors supervisor-protected */
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{
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0,
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0,
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0x800,
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MMU_PAGE_SIZE_1K,
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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0x800,
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0x800,
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0x800,
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MMU_PAGE_SIZE_1K,
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* when the first 4k are filled with 1k pages, we can switch to 8k pages */
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0x1000,
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0x1000,
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0xff000,
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MMU_PAGE_SIZE_8K,
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* arrived at a 1Meg border, we can switch to 1Meg pages */
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0x100000,
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0x100000,
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0xc00000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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/* Falcon video ram left out intentionally here (see above) */
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{
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/* ROM */
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0xe00000,
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0xe00000,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_EXECUTE },
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},
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{
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/* FASTRAM */
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0x1000000,
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0x1000000,
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(uint32_t) _FASTRAM_END - 0x1000000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* MBAR */
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MBAR_ADDRESS,
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MBAR_ADDRESS,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
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},
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{
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/* RAMBAR0 */
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RAMBAR0_ADDRESS,
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RAMBAR0_ADDRESS,
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(uint32_t) _RAMBAR0_SIZE,
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MMU_PAGE_SIZE_1K,
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* RAMBAR1 */
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RAMBAR1_ADDRESS,
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RAMBAR1_ADDRESS,
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(uint32_t) _RAMBAR1_SIZE,
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MMU_PAGE_SIZE_1K,
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* SYSTEM SRAM */
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SYS_SRAM_ADDRESS,
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SYS_SRAM_ADDRESS,
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(uint32_t) _SYS_SRAM_SIZE,
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MMU_PAGE_SIZE_8K,
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* Firebee FPGA registers */
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(uint32_t) 0xf0000000,
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(uint32_t) 0xf0000000,
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(uint32_t) 0x08000000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
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},
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{
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/* Falcon I/O registers */
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(uint32_t) 0xfff00000,
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(uint32_t) 0xfff00000,
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(uint32_t) 0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
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},
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{
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/* the same, but different virtual address */
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(uint32_t) 0x00f00000,
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(uint32_t) 0xfff00000,
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(uint32_t) 0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
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},
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{
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/* PCI memory */
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(uint32_t) PCI_MEMORY_OFFSET,
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(uint32_t) PCI_MEMORY_OFFSET,
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(uint32_t) PCI_MEMORY_SIZE,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
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},
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{
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/* PCI I/O */
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(uint32_t) PCI_IO_OFFSET,
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(uint32_t) PCI_IO_OFFSET,
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(uint32_t) PCI_IO_SIZE,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
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}
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};
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static int num_mmu_maps = sizeof(memory_map) / sizeof(struct mmu_mapping);
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static struct mmu_mapping *lookup_mapping(uint32_t virt)
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{
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int i;
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/*
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* dumb, for now
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*/
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for (i = 0; i < num_mmu_maps; i++)
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{
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if (virt >= memory_map[i].virt && virt <= memory_map[i].virt + memory_map[i].length - 1)
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return &memory_map[i];
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}
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return NULL;
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}
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void mmu_init(void)
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{
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extern uint8_t _MMUBAR[];
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uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
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int i;
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set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
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/*
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* need to set data ACRs in a way that supervisor access to all memory regions
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* becomes possible. Otherways it might be that the supervisor stack ends up in an unmapped
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* region when further MMU TLB entries force a page steal. This would lead to a double
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* fault since the CPU wouldn't be able to push its exception stack frame during an access
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* exception
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*/
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/* set data access attributes in ACR0 and ACR1 */
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set_acr0(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */
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ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */
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ACR_CACHE_MODE(CACHE_NOCACHE_PRECISE) | /* cache inhibit, precise */
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ACR_ADDRESS_MASK_MODE(0) | /* region > 16 MByte */
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ACR_S(ACR_S_ALL) | /* memory visible in user and supervisor mode */
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ACR_E(1) | /* enable ACR */
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#if defined(MACHINE_FIREBEE)
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ACR_ADMSK(0x3f) | /* cover 1 GB area from 0xc0000000 to 0xffffffff */
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ACR_BA(0xc0000000)); /* equals area from 3 to 4 GB */
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#elif defined(MACHINE_M5484LITE)
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ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
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ACR_BA(0x80000000));
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#elif defined(MACHINE_M54455)
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ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
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ACR_BA(0x80000000));
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#else
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#error unknown machine
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#endif /* MACHINE_FIREBEE */
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set_acr1(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */
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ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */
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#if defined(MACHINE_FIREBEE)
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ACR_CACHE_MODE(CACHE_WRITETHROUGH) | /* video RAM on the Firebee */
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#elif defined(MACHINE_M5484LITE)
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ACR_CACHE_MODE(CACHE_NOCACHE_PRECISE) | /* Compact Flash on the M548xLITE */
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#elif defined(MACHINE_M54455)
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ACR_CACHE_MODE(CACHE_NOCACHE_PRECISE) | /* FIXME: not clear yet */
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#else
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#error unknown machine
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#endif
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ACR_ADDRESS_MASK_MODE(0) | /* region > 16 MByte */
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ACR_S(ACR_S_ALL) | /* memory visible from user and supervisor mode */
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ACR_E(1) | /* enable ACR */
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ACR_ADMSK(0x1f) |
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ACR_BA(0x60000000));
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/*
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* set instruction access attributes in ACR2 and ACR3.
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*/
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set_acr2(ACR_WRITE_PROTECT(0) |
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ACR_SUPERVISOR_PROTECT(0) |
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ACR_CACHE_MODE(CACHE_WRITETHROUGH) |
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ACR_ADDRESS_MASK_MODE(1) |
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ACR_S(ACR_S_ALL) |
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ACR_E(1) |
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ACR_ADMSK(0x07) |
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ACR_BA(0xe0000000));
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set_acr3(0); /* disable ACR3 */
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set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
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/* clear all MMU TLB entries */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
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/* map locked TLB entries */
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for (i = 0; i < num_locked_mmu_maps; i++)
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{
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mmu_map_page(locked_map[i].virt, locked_map[i].phys, locked_map->pagesize, locked_map->flags);
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if (locked_map[i].flags.page_id == SCA_PAGE_ID)
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{
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video_tlb = 0x2000;
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video_sbt = 0x0;
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}
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}
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}
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/*
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* handle an access error
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* upper level routine called from access_exception inside exceptions.S
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*/
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bool access_exception(uint32_t pc, uint32_t format_status)
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{
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int fault_status;
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uint32_t fault_address;
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uint32_t mmu_status;
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/*
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* extract fault status from format_status exception stack field
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*/
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fault_status = format_status & 0xc030000;
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mmu_status = MCF_MMU_MMUSR;
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/*
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* determine if access fault was caused by a TLB miss
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*/
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switch (fault_status)
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{
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case 0x4010000: /* TLB miss on opword of instruction fetch */
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case 0x4020000: /* TLB miss on extension word of instruction fetch */
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//fault_address = pc;
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//break;
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case 0x8020000: /* TLB miss on data write */
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case 0xc020000: /* TLB miss on data read or read-modify-write */
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fault_address = MCF_MMU_MMUAR;
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/*
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* the following line must stay commented or we risk a double fault (debugging
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* output requiring itself a page mapping):
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*/
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// dbg("access fault - TLB miss at %p. Fault status = 0x0%x\r\n", pc, fault_status);
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break;
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default:
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return false;
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}
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if (mmu_status & MCF_MMU_MMUSR_HIT) /* did the last fault hit in TLB? */
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{
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/*
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* if yes, then we already mapped that page during a previous turn and this is in fact a bus error
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*/
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return false;
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}
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else
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{
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struct mmu_mapping *map;
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if ((map = lookup_mapping(fault_address)) != NULL)
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{
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uint32_t mask;
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switch (map->pagesize)
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{
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case MMU_PAGE_SIZE_1M:
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mask = ~(0x100000 - 1);
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break;
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case MMU_PAGE_SIZE_4K:
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mask = ~(0x1000 - 1);
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break;
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case MMU_PAGE_SIZE_8K:
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mask = ~(0x2000 - 1);
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break;
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case MMU_PAGE_SIZE_1K:
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mask = ~(0x400 - 1);
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break;
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}
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mmu_map_page(fault_address & mask, fault_address & mask, map->pagesize, map->flags);
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return true;
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}
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}
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return false;
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}
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void mmu_map_page(uint32_t virt, uint32_t phys, uint32_t map_size, struct map_flags flags)
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{
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/*
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* add page to TLB
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*/
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MCF_MMU_MMUTR = virt | /* virtual address */
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MCF_MMU_MMUTR_ID(flags.page_id) |
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = phys | /* physical address */
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MCF_MMU_MMUDR_SZ(map_size) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(flags.cache_mode) |
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(flags.access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
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(flags.access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
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(flags.access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0); /* execute access enable */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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dbg("mapped virt=%p to phys=%p\r\n", virt, phys);
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}
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