49 lines
1.1 KiB
ArmAsm
49 lines
1.1 KiB
ArmAsm
.equ MCF_MMU_MMUCR, __MMUBAR + 0
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_startup:
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.extern _initialize_hardware
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.extern _rt_mbar
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bra.s warmstart
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jmp ___BOOT_FLASH + 8 /* that's also our reset vector */
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/* disable interrupts */
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warmstart:
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move.w #0x2700,sr
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/* Initialize MBAR */
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move.l #__MBAR,d0
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movec d0,MBAR
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move.l d0,_rt_mbar
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/* mmu off */
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move.l #__MMUBAR+1,d0
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movec d0,MMUBAR
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clr.l d0
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move.l d0,MCF_MMU_MMUCR
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/* Initialize RAMBARs: locate SRAM and validate it */
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move.l #__RAMBAR0 + 0x7,d0 /* supervisor only */
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movec d0,RAMBAR0
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move.l #__RAMBAR1 + 0x1,d0
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movec d0,RAMBAR1
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/* set stack pointer to end of SRAM1 */
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lea __SUP_SP,a7
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/* Initialize the processor caches.
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* The instruction cache is fully enabled.
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* The data cache is enabled, but cache-inhibited by default.
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* Later, the MMU will fully activate the data cache for specific areas.
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* It is important to enable both caches now, otherwise cpushl would hang.
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*/
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move.l #0xa50c8120,d0
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movec d0,cacr
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andi.l #0xfefbfeff,d0 // Clear invalidate bits
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move.l d0,_rt_cacr
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/* initialize any hardware specific issues */
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bra _initialize_hardware
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