412 lines
11 KiB
C
412 lines
11 KiB
C
#define RINFO_ONLY
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#include "radeonfb.h"
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#include "bas_printf.h"
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#include "bas_string.h"
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#include "util.h"
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#include "driver_mem.h"
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#include "x86emu.h"
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#include "x86emu_regs.h"
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#include "pci.h"
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#include "pci_ids.h"
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#include "x86pcibios.h"
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#define DEBUG
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#include "debug.h"
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#define USE_SDRAM
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#define DIRECT_ACCESS
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#define MEM_WB(where, what) emu->emu_wrb(emu, where, what)
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#define MEM_WW(where, what) emu->emu_wrw(emu, where, what)
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#define MEM_WL(where, what) emu->emu_wrl(emu, where, what)
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#define MEM_RB(where) emu->emu_rdb(emu, where)
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#define MEM_RW(where) emu->emu_rdw(emu, where)
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#define MEM_RL(where) emu->emu_rdl(emu, where)
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#define PCI_VGA_RAM_IMAGE_START 0xC0000
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#define PCI_RAM_IMAGE_START 0xD0000
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#define SYS_BIOS 0xF0000
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#define SIZE_EMU 0x100000
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typedef struct
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{
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long ident;
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union
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{
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long l;
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short i[2];
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char c[4];
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} v;
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} COOKIE;
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struct rom_header
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{
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uint16_t signature;
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uint8_t size;
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uint8_t init[3];
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uint8_t reserved[0x12];
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uint16_t data;
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};
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struct pci_data
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{
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uint32_t signature;
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uint16_t vendor;
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uint16_t device;
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uint16_t reserved_1;
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uint16_t dlen;
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uint8_t drevision;
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uint8_t class_lo;
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uint16_t class_hi;
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uint16_t ilen;
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uint16_t irevision;
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uint8_t type;
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uint8_t indicator;
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uint16_t reserved_2;
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};
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static struct radeonfb_info *rinfo_biosemu;
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uint16_t offset_port;
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uint32_t offset_mem;
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static uint32_t offset_io;
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static uint32_t config_address_reg;
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//X86EMU_sysEnv _X86EMU_env;
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/* general software interrupt handler */
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uint32_t getIntVect(struct X86EMU *emu, int num)
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{
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return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4);
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}
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/* FixME: There is already a push_word() in the emulator */
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void pushw(struct X86EMU *emu, uint16_t val)
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{
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emu->x86.R_ESP -= 2;
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MEM_WW(((uint32_t) emu->x86.R_SS << 4) + emu->x86.R_SP, val);
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}
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int run_bios_int(struct X86EMU *emu, int num)
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{
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uint32_t eflags;
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eflags = emu->x86.R_EFLG;
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pushw(emu, eflags);
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pushw(emu, emu->x86.R_CS);
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pushw(emu, emu->x86.R_IP);
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emu->x86.R_CS = MEM_RW((num << 2) + 2);
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emu->x86.R_IP = MEM_RW(num << 2);
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return 1;
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}
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static uint8_t inb(struct X86EMU *emu, uint16_t port)
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{
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uint8_t val = 0;
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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val = * (uint8_t *) (offset_io + (uint32_t) port);
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}
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return val;
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}
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uint16_t inw(struct X86EMU *emu, uint16_t port)
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{
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uint16_t val = 0;
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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val = swpw(*(uint16_t *)(offset_io + (uint32_t) port));
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}
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return val;
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}
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uint32_t inl(struct X86EMU *emu, uint16_t port)
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{
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uint32_t val = 0;
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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val = swpl(*(uint32_t *)(offset_io + (uint32_t) port));
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}
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else if (port == 0xCF8)
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{
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val = config_address_reg;
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}
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else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) != 0))
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{
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dbg("PCI BIOS access to register %x\r\n", config_address_reg);
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switch (config_address_reg & 0xFC)
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{
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case PCIIDR:
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val = ((uint32_t) rinfo_biosemu->chipset << 16) + PCI_VENDOR_ID_ATI;
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break;
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case PCIBAR1:
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val = (uint32_t) offset_port + 1;
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break;
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default:
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val = pci_read_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC);
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break;
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}
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dbg("inl(0x%x) = 0x%x\r\n", port, val);
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}
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return val;
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}
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void outb(struct X86EMU *emu, uint16_t port, uint8_t val)
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{
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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*(uint8_t *)(offset_io + (uint32_t) port) = val;
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}
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}
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void outw(struct X86EMU *emu, uint16_t port, uint16_t val)
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{
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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*(uint16_t *)(offset_io + (uint32_t) port) = swpw(val);
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}
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}
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void outl(struct X86EMU *emu, uint16_t port, uint32_t val)
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{
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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*(uint32_t *)(offset_io + (uint32_t) port) = swpl(val);
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}
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else if (port == 0xCF8)
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{
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config_address_reg = val;
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}
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else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) !=0))
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{
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if ((config_address_reg & 0xFC) == PCIBAR1)
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offset_port = (uint16_t)val & 0xFFFC;
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else
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{
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dbg("outl(0x%x, 0x%x) to PCI config space\r\n", port, val);
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pci_write_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC, val);
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}
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}
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}
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/* Interrupt multiplexer */
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void do_int(struct X86EMU *emu, int num)
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{
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int ret = 0;
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dbg("int %02xh\r\n", num);
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switch (num)
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{
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#ifndef _PC
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case 0x10:
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case 0x42:
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case 0x6D:
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if (getIntVect(emu, num) == 0x0000)
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dbg("uninitialised int vector\r\n");
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if (getIntVect(emu, num) == 0xFF065)
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{
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//ret = int42_handler();
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ret = 1;
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}
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break;
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#endif
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case 0x15:
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//ret = int15_handler();
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ret = 1;
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break;
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case 0x16:
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//ret = int16_handler();
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ret = 0;
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break;
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case 0x1A:
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ret = x86_pcibios_handler(emu);
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ret = 1;
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break;
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case 0xe6:
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//ret = intE6_handler();
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ret = 0;
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break;
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default:
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break;
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}
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if (!ret)
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ret = run_bios_int(emu, num);
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}
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static int setup_system_bios(void *base_addr)
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{
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char *base = (char *) base_addr;
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int i;
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/*
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* we trap the "industry standard entry points" to the BIOS
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* and all other locations by filling them with "hlt"
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* TODO: implement hlt-handler for these
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*/
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for(i = 0; i < SIZE_EMU + 4; base[i++] = 0xF4);
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return(1);
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}
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void run_bios(struct radeonfb_info *rinfo)
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{
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long i, j;
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unsigned char *ptr;
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struct rom_header *rom_header;
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struct pci_data *rom_data;
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unsigned long rom_size=0;
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unsigned long image_size=0;
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void *biosmem = (void *) 0x0100000; /* when run_bios() is called, SDRAM is valid but not added to the system */
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unsigned long addr;
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unsigned short initialcs;
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unsigned short initialip;
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unsigned short devfn = (unsigned short) rinfo->handle;
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struct X86EMU emu = {0};
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X86EMU_init_default(&emu);
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emu.emu_inb = inb;
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emu.emu_inw = inw;
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emu.emu_inl = inl;
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emu.emu_outb = outb;
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emu.emu_outw = outw;
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emu.emu_outl = outl;
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if ((rinfo->mmio_base == NULL) || (rinfo->io_base == NULL))
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{
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dbg("rinfo->mmio_base = %p, rinfo->io_base = %p\r\n", rinfo->mmio_base, rinfo->io_base);
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return;
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}
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rinfo_biosemu = rinfo;
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config_address_reg = 0;
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offset_port = 0x300;
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offset_io = (uint32_t) rinfo->io_base - (uint32_t) offset_port;
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offset_mem = (uint32_t) rinfo->fb_base - 0xA0000;
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rom_header = NULL;
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do
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{
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rom_header = (struct rom_header *) ((unsigned long) rom_header + image_size); // get next image
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rom_data = (struct pci_data *) ((unsigned long)rom_header + (unsigned long) BIOS_IN16((long) &rom_header->data));
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image_size = (unsigned long) BIOS_IN16((long) &rom_data->ilen) * 512;
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} while ((BIOS_IN8((long) &rom_data->type) != 0) && (BIOS_IN8((long) &rom_data->indicator) != 0)); // make sure we got x86 version
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if (BIOS_IN8((long) &rom_data->type) != 0)
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{
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dbg("unknown ROM data type = 0x%x\r\n", BIOS_IN8((long) &rom_data->type));
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return;
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}
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rom_size = (unsigned long) BIOS_IN8((long) &rom_header->size) * 512;
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dbg("ROM size = 0x%lx\r\n", rom_size);
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if (PCI_CLASS_DISPLAY_VGA == BIOS_IN16((long) &rom_data->class_hi))
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{
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memset((char *) biosmem, 0, SIZE_EMU);
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setup_system_bios((char *) biosmem);
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dbg("Copying VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
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(long) rinfo->bios_seg + (long) rom_header,
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biosmem + PCI_VGA_RAM_IMAGE_START, rom_size);
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{
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long bytes_align = (long) rom_header & 3;
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ptr = (unsigned char *) biosmem;
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i = (long) rom_header;
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j = PCI_VGA_RAM_IMAGE_START;
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if (bytes_align)
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for(; i < 4 - bytes_align; ptr[j++] = BIOS_IN8(i++));
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for(; i < (long) rom_header + rom_size; i += 4, j += 4)
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*((unsigned long *) &ptr[j]) = swpl(BIOS_IN32(i));
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}
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addr = PCI_VGA_RAM_IMAGE_START;
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}
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else
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{
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memset((char *) biosmem, 0, SIZE_EMU);
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setup_system_bios((char *) biosmem);
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dbg("Copying non-VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
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(long) rinfo->bios_seg + (long) rom_header,
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biosmem + PCI_RAM_IMAGE_START,
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rom_size);
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ptr = (unsigned char *) biosmem;
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for (i = (long) rom_header, j = PCI_RAM_IMAGE_START; i < (long) rom_header+rom_size; ptr[j++] = BIOS_IN8(i++));
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addr = PCI_RAM_IMAGE_START;
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}
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initialcs = (addr & 0xF0000) >> 4;
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initialip = (addr + 3) & 0xFFFF;
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/*
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* set emulator memory
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*/
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emu.mem_base = (void *) biosmem;
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emu.mem_size = SIZE_EMU;
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for (i = 0; i < 256; i++)
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{
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emu._X86EMU_intrTab[i] = do_int;
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}
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{
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char *date = "01/01/99";
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for (i = 0; date[i]; i++)
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emu.emu_wrb(&emu, 0xffff5 + i, date[i]);
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emu.emu_wrb(&emu, 0xffff7, '/');
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emu.emu_wrb(&emu, 0xffffa, '/');
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}
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{
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/* FixME: move PIT init to its own file */
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outb(&emu, 0x36, 0x43);
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outb(&emu, 0x00, 0x40);
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outb(&emu, 0x00, 0x40);
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}
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// setup_int_vect();
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/* cpu setup */
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emu.x86.R_AX = devfn ? devfn : 0xff;
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emu.x86.R_DX = 0x80;
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emu.x86.R_IP = initialip;
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emu.x86.R_CS = initialcs;
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/* Initialize stack and data segment */
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emu.x86.R_SS = initialcs;
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emu.x86.R_SP = 0xfffe;
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emu.x86.R_DS = 0x0040;
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emu.x86.R_ES = 0x0000;
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/*
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* We need a sane way to return from bios
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* execution. A hlt instruction and a pointer
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* to it, both kept on the stack, will do.
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*/
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pushw(&emu, 0xf4f4); /* hlt; hlt */
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// pushw(0x10cd); /* int #0x10 */
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// pushw(0x0013); /* 320 x 200 x 256 colors */
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// // pushw(0x000F); /* 640 x 350 x mono */
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// pushw(0xb890); /* nop, mov ax,#0x13 */
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pushw(&emu, emu.x86.R_SS);
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pushw(&emu, emu.x86.R_SP + 2);
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dbg("X86EMU entering emulator\r\n");
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//*vblsem = 0;
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X86EMU_exec(&emu);
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//*vblsem = 1;
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dbg("X86EMU halted\r\n");
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// biosfn_set_video_mode(0x13); /* 320 x 200 x 256 colors */
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memset((char *) biosmem, 0, SIZE_EMU);
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}
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