53 lines
1.7 KiB
C
53 lines
1.7 KiB
C
/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/05/23 Revision: 0.81
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*
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* (c) Copyright UNIS, a.s. 1997-2008
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* UNIS, a.s.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF5475_SIU_H__
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#define __MCF5475_SIU_H__
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/*********************************************************************
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*
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* System Integration Unit (SIU)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10]))
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#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38]))
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#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44]))
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#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50]))
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/* Bit definitions and macros for MCF_SIU_SBCR */
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#define MCF_SIU_SBCR_PIN2DSPI (0x8000000)
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#define MCF_SIU_SBCR_DMA2CPU (0x10000000)
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#define MCF_SIU_SBCR_CPU2DMA (0x20000000)
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#define MCF_SIU_SBCR_PIN2DMA (0x40000000)
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#define MCF_SIU_SBCR_PIN2CPU (0x80000000)
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/* Bit definitions and macros for MCF_SIU_SECSACR */
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#define MCF_SIU_SECSACR_SEQEN (0x1)
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/* Bit definitions and macros for MCF_SIU_RSR */
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#define MCF_SIU_RSR_RST (0x1)
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#define MCF_SIU_RSR_RSTWD (0x2)
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#define MCF_SIU_RSR_RSTJTG (0x8)
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/* Bit definitions and macros for MCF_SIU_JTAGID */
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#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0)
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#endif /* __MCF5475_SIU_H__ */
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