82 lines
3.2 KiB
VHDL
82 lines
3.2 KiB
VHDL
-- WARNING: Do NOT edit the input and output ports in this file in a text
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-- editor if you plan to continue editing the block that represents it in
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-- the Block Editor! File corruption is VERY likely to occur.
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-- Copyright (C) 1991-2008 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
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-- Created on Tue Sep 08 16:24:57 2009
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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-- Entity Declaration
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ENTITY DSP IS
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port(
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CLK_33M : in std_logic;
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CLK_MAIN : in std_logic;
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fb_oe_n : in std_logic;
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FB_WRn : in std_logic;
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FB_CS1n : in std_logic;
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FB_CS2n : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_BURSTn : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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RESETn : in std_logic;
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FB_CS3n : in std_logic;
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SRCSn : buffer std_logic;
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SRBLEn : out std_logic;
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SRBHEn : out std_logic;
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SRWEn : out std_logic;
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SROEn : out std_logic;
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DSP_INT : out std_logic;
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DSP_TA : out std_logic;
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FB_AD_IN : in std_logic_vector(31 downto 0);
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FB_AD_OUT : out std_logic_vector(31 downto 0);
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FB_AD_EN : out std_logic;
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IO_IN : in std_logic_vector(17 downto 0);
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IO_OUT : out std_logic_vector(17 downto 0);
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IO_EN : out std_logic;
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SRD_IN : in std_logic_vector(15 downto 0);
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SRD_OUT : out std_logic_vector(15 downto 0);
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SRD_EN : out std_logic
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);
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END DSP;
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-- Architecture Body
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ARCHITECTURE DSP_architecture OF DSP IS
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BEGIN
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SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n;
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SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1';
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SRBLEn <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
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SRWEn <= '0' when FB_WRn = '0' and SRCSn = '0' and CLK_MAIN = '0' else '1';
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SROEn <= '0' when fb_oe_n = '0' and SRCSn = '0' else '1';
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DSP_INT <= '0';
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DSP_TA <= '0';
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IO_OUT(17 downto 0) <= FB_ADR(18 downto 1);
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IO_EN <= '1';
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SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when FB_WRn = '0' and SRCSn = '0' else x"0000";
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SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0';
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FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000";
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FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000";
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FB_AD_EN <= '1' when fb_oe_n = '0' and SRCSn = '0' else '0';
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END DSP_architecture;
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