135 lines
6.0 KiB
VHDL
135 lines
6.0 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- 6850 compatible IP Core ----
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---- ----
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---- This file is part of the SUSKA ATARI clone project. ----
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---- http://www.experiment-s.de ----
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---- ----
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---- Description: ----
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---- UART 6850 compatible IP core ----
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---- ----
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---- This is the top level file. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006 Wolfgang Foerster ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K6A 2006/06/03 WF
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-- Initial Release.
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-- Revision 2K6B 2006/11/07 WF
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-- Modified Source to compile with the Xilinx ISE.
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-- Revision 2K8B 2008/12/24 WF
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-- Rewritten this top level file as a wrapper for the top_soc file.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity WF6850IP_TOP is
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port (
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CLK : in std_logic;
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RESETn : in std_logic;
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CS2n, CS1, CS0 : in std_logic;
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E : in std_logic;
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RWn : in std_logic;
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RS : in std_logic;
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DATA : inout std_logic_vector(7 downto 0);
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TXCLK : in std_logic;
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RXCLK : in std_logic;
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RXDATA : in std_logic;
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CTSn : in std_logic;
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DCDn : in std_logic;
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irq_n : out std_logic;
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TXDATA : out std_logic;
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RTSn : out std_logic
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);
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end entity WF6850IP_TOP;
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architecture STRUCTURE of WF6850IP_TOP is
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component WF6850IP_TOP_SOC
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port (
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CLK : in std_logic;
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RESETn : in std_logic;
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CS2n, CS1, CS0 : in std_logic;
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E : in std_logic;
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RWn : in std_logic;
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RS : in std_logic;
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DATA_IN : in std_logic_vector(7 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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DATA_EN : out std_logic;
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TXCLK : in std_logic;
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RXCLK : in std_logic;
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RXDATA : in std_logic;
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CTSn : in std_logic;
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DCDn : in std_logic;
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irq_n : out std_logic;
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TXDATA : out std_logic;
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RTSn : out std_logic
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);
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end component;
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signal DATA_OUT : std_logic_vector(7 downto 0);
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signal DATA_EN : std_logic;
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signal IRQ_In : std_logic;
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begin
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DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
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irq_n <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
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I_UART: WF6850IP_TOP_SOC
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port map(CLK => CLK,
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RESETn => RESETn,
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CS2n => CS2n,
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CS1 => CS1,
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CS0 => CS0,
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E => E,
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RWn => RWn,
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RS => RS,
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DATA_IN => DATA,
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DATA_OUT => DATA_OUT,
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DATA_EN => DATA_EN,
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TXCLK => TXCLK,
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RXCLK => RXCLK,
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RXDATA => RXDATA,
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CTSn => CTSn,
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DCDn => DCDn,
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irq_n => IRQ_In,
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TXDATA => TXDATA,
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RTSn => RTSn
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);
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end architecture STRUCTURE; |