101 lines
4.7 KiB
VHDL
101 lines
4.7 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- This file is part of the 'Firebee' project. ----
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---- http://acp.atari.org ----
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---- ----
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---- Description: ----
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---- This design unit provides the std_logic block transfer processor ----
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---- (BLITTER) of the 'Firebee' computer. ----
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---- It is optimized for the use of an Altera Cyclone ----
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---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----
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---- tion of the Firebee configware originally provided by Fredi ----
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---- Ashwanden and Wolfgang Förster. This release is in compa- ----
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---- rision to the first edition completely written in VHDL. ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2012 Wolfgang Förster ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 2 of the License, or (at your option) any later ----
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---- version. ----
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---- ----
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---- This program is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU General Public ----
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---- License along with this program; if not, write to the Free ----
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---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
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---- Boston, MA 02110-1301, USA. ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K12B 20120801 WF
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-- Initial Release of the second edition.
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY fbee_blitter IS
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PORT(
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reset_n : IN std_logic;
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clk_main : IN std_logic;
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clk_ddr0 : IN std_logic;
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fb_adr : IN std_logic_vector(31 DOWNTO 0);
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fb_ale : IN std_logic;
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fb_size1 : IN std_logic;
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fb_size0 : IN std_logic;
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fb_cs_n : IN std_logic_vector(3 DOWNTO 1);
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fb_oe_n : IN std_logic;
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fb_wr_n : IN std_logic;
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data_in : IN std_logic_vector(31 DOWNTO 0);
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data_out : OUT std_logic_vector(31 DOWNTO 0);
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data_en : OUT std_logic;
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blitter_on : IN std_logic;
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blitter_din : IN std_logic_vector(127 DOWNTO 0);
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blitter_dack_sr : IN std_logic;
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blitter_run : OUT std_logic;
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blitter_dout : OUT std_logic_vector(127 DOWNTO 0);
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blitter_adr : OUT std_logic_vector(31 DOWNTO 0);
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blitter_sig : OUT std_logic;
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blitter_wr : OUT std_logic;
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blitter_ta : OUT std_logic
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);
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END ENTITY fbee_blitter;
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architecture BEHAVIOUR of FBEE_BLITTER is
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signal BLITTER_DACK : std_logic_vector(4 DOWNTO 0);
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signal BLITTER_DIN_I : std_logic_vector(127 DOWNTO 0);
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begIN
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P_BLITTER_DACK: process
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begIN
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wait until CLK_DDR0 = '1' and CLK_DDR0' event;
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BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 DOWNTO 1);
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if BLITTER_DACK(0) = '1' then
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BLITTER_DIN_I <= BLITTER_DIN;
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end if;
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end process P_BLITTER_DACK;
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BLITTER_RUN <= '0';
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BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
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DATA_OUT <= x"FEDCBA98";
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BLITTER_ADR <= x"76543210";
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BLITTER_SIG <= '0';
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BLITTER_WR <= '0';
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BLITTER_TA <= '0';
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DATA_EN <= '0';
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END BEHAVIOUR;
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