62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/*
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* cache handling
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*/
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#include "cache.h"
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void flushDataCacheRegion(void *adr, uint32_t length)
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{
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asm volatile
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(
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" move.l %0,d0 | start address\n\t"
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" move.l d0,a1\n\t"
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" add.l %1,a1 | add length\n\t"
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" clr.l d1 | way counter\n\t"
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" and.l #0xfffffff0,d0 | align start address\n\t"
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".flush_dregion_way_loop:\n\t"
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" move.l d0,a0 | initialize a0\n\t"
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" add.l d1,a0 | set way index\n\t"
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".flush_dregion_loop:\n\t"
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" cpushl DC,(a0) | flush and invalidate the cache line\n\t"
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" add.l #0x10,a0 | increment to next cache line\n\t"
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" cmp.l a0,a1 | done with region?\n\t"
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" bgt .flush_dregion_loop\n\t"
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" addq.l #1,d1 | increment way counter\n\t"
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" addq.l #1,a1 | update stop address to reflect new way value\n\t"
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" cmp.l #4,d1 | cache way\n\t"
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" bne .flush_dregion_way_loop\n\t"
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/* output */ :
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/* input */ : "g" (adr),
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"g" (length)
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/* clobber */: "d0", "d1", "a0", "a1"
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);
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}
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void flushInstructionCacheRegion(void *adr, uint32_t length)
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{
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asm volatile
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(
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" move.l %0,d0 | start address\n\t"
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" move.l d0,a1\n\t"
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" add.l %1,a1 | add length\n\t"
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" clr.l d1 | way counter\n\t"
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" and.l #0xfffffff0,d0 | align start address\n\t"
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".flush_iregion_way_loop:\n\t"
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" move.l d0,a0 | initialize a0\n\t"
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" add.l d1,a0 | set way index\n\t"
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".flush_iregion_loop:\n\t"
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" cpushl IC,(a0) | flush and invalidate the cache line\n\t"
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" add.l #0x10,a0 | increment to next cache line\n\t"
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" cmp.l a0,a1 | done with region?\n\t"
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" bgt .flush_iregion_loop\n\t"
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" addq.l #1,d1 | increment way counter\n\t"
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" addq.l #1,a1 | update stop address to reflect new way value\n\t"
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" cmp.l #4,d1 | cache way\n\t"
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" bne .flush_iregion_way_loop\n\t"
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/* output */ :
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/* input */ : "g" (adr),
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"g" (length)
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/* clobber */: "d0", "d1", "a0", "a1"
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);
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}
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