661 lines
21 KiB
Plaintext
661 lines
21 KiB
Plaintext
TITLE "DDR_CTR";
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-- CREATED BY FREDI ASCHWANDEN
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INCLUDE "lpm_bustri_BYT.inc";
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-- FIFO WATER MARK
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CONSTANT FIFO_LWM = 0;
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CONSTANT FIFO_MWM = 200;
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CONSTANT FIFO_HWM = 500;
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-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
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SUBDESIGN DDR_CTR
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(
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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FB_ADR[31..0] : INPUT;
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nFB_CS1 : INPUT;
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nFB_CS2 : INPUT;
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nFB_CS3 : INPUT;
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nFB_OE : INPUT;
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FB_SIZE0 : INPUT;
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FB_SIZE1 : INPUT;
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nRSTO : INPUT;
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MAIN_CLK : INPUT;
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FB_ALE : INPUT;
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nFB_WR : INPUT;
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DDR_SYNC_66M : INPUT;
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CLR_FIFO : INPUT;
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VIDEO_RAM_CTR[15..0] : INPUT;
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BLITTER_ADR[31..0] : INPUT;
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BLITTER_SIG : INPUT;
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BLITTER_WR : INPUT;
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DDRCLK0 : INPUT;
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CLK33M : INPUT;
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FIFO_MW[8..0] : INPUT;
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VA[12..0] : OUTPUT;
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nVWE : OUTPUT;
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nVRAS : OUTPUT;
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nVCS : OUTPUT;
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VCKE : OUTPUT;
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nVCAS : OUTPUT;
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FB_LE[3..0] : OUTPUT;
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FB_VDOE[3..0] : OUTPUT;
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CLEAR_FIFO_CNT : OUTPUT;
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SR_FIFO_WRE : OUTPUT;
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SR_DDR_FB : OUTPUT;
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SR_DDR_WR : OUTPUT;
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SR_DDRWR_D_SEL : OUTPUT;
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SR_VDMP[7..0] : OUTPUT;
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VIDEO_DDR_TA : OUTPUT;
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SR_BLITTER_DACK : OUTPUT;
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BA[1..0] : OUTPUT;
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DDRWR_D_SEL1 : OUTPUT;
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VDM_SEL[3..0] : OUTPUT;
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FB_AD[31..0] : BIDIR;
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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)
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VARIABLE
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FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
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DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns)
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DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG
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DS_T4R,DS_T5R, -- READ CPU UND BLITTER,
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DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER
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DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO
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DS_CB6, DS_CB8, -- CLOSE FIFO BANK
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DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS
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LINE :NODE;
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FB_B[3..0] :NODE;
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VCAS :NODE;
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VRAS :NODE;
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VWE :NODE;
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VA_P[12..0] :DFF;
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BA_P[1..0] :DFF;
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VA_S[12..0] :DFF;
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BA_S[1..0] :DFF;
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MCS[1..0] :DFF;
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CPU_DDR_SYNC :DFF;
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DDR_SEL :NODE;
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DDR_CS :DFFE;
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DDR_CONFIG :NODE;
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SR_DDR_WR :DFF;
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SR_DDRWR_D_SEL :DFF;
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SR_VDMP[7..0] :DFF;
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CPU_ROW_ADR[12..0] :NODE;
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CPU_BA[1..0] :NODE;
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CPU_COL_ADR[9..0] :NODE;
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CPU_SIG :NODE;
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CPU_REQ :DFF;
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CPU_AC :DFF;
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BUS_CYC :DFF;
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BUS_CYC_END :NODE;
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BLITTER_REQ :DFF;
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BLITTER_AC :DFF;
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BLITTER_ROW_ADR[12..0] :NODE;
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BLITTER_BA[1..0] :NODE;
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BLITTER_COL_ADR[9..0] :NODE;
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FIFO_REQ :DFF;
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FIFO_AC :DFF;
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FIFO_ROW_ADR[12..0] :NODE;
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FIFO_BA[1..0] :NODE;
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FIFO_COL_ADR[9..0] :NODE;
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FIFO_ACTIVE :NODE;
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CLR_FIFO_SYNC :DFF;
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CLEAR_FIFO_CNT :DFF;
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STOP :DFF;
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SR_FIFO_WRE :DFF;
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FIFO_BANK_OK :DFF;
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FIFO_BANK_NOT_OK :NODE;
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DDR_REFRESH_ON :NODE;
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DDR_REFRESH_CNT[10..0] :DFF;
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DDR_REFRESH_REQ :DFF;
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DDR_REFRESH_SIG[3..0] :DFFE;
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REFRESH_TIME :DFF;
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VIDEO_BASE_L_D[7..0] :DFFE;
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VIDEO_BASE_L :NODE;
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VIDEO_BASE_M_D[7..0] :DFFE;
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VIDEO_BASE_M :NODE;
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VIDEO_BASE_H_D[7..0] :DFFE;
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VIDEO_BASE_H :NODE;
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VIDEO_BASE_X_D[2..0] :DFFE;
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VIDEO_ADR_CNT[22..0] :DFFE;
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VIDEO_CNT_L :NODE;
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VIDEO_CNT_M :NODE;
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VIDEO_CNT_H :NODE;
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VIDEO_BASE_ADR[22..0] :NODE;
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VIDEO_ACT_ADR[26..0] :NODE;
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BEGIN
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LINE = FB_SIZE0 & FB_SIZE1;
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-- BYT SELECT
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FB_B0 = FB_ADR[1..0]==0 -- ADR==0
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B1 = FB_ADR[1..0]==1 -- ADR==1
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# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B2 = FB_ADR[1..0]==2 -- ADR==2
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B3 = FB_ADR[1..0]==3 -- ADR==3
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# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
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FB_REGDDR.CLK = MAIN_CLK;
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CASE FB_REGDDR IS
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WHEN FR_WAIT =>
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FB_LE0 = !nFB_WR;
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IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
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FB_REGDDR = FR_S0;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S0 =>
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IF DDR_CS THEN
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FB_LE0 = !nFB_WR;
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VIDEO_DDR_TA = VCC;
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IF LINE THEN
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FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
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FB_REGDDR = FR_S1;
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ELSE
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BUS_CYC_END = VCC;
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FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
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FB_REGDDR = FR_WAIT;
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END IF;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S1 =>
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IF DDR_CS THEN
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FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
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FB_LE1 = !nFB_WR;
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VIDEO_DDR_TA = VCC;
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FB_REGDDR = FR_S2;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S2 =>
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IF DDR_CS THEN
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FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
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FB_LE2 = !nFB_WR;
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IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN
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FB_REGDDR = FR_S2;
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ELSE
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VIDEO_DDR_TA = VCC;
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FB_REGDDR = FR_S3;
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END IF;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S3 =>
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IF DDR_CS THEN
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FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
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FB_LE3 = !nFB_WR;
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VIDEO_DDR_TA = VCC;
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BUS_CYC_END = VCC;
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FB_REGDDR = FR_WAIT;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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END CASE;
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-- DDR STEUERUNG -----------------------------------------------------
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-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
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VCKE = VIDEO_RAM_CTR0;
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nVCS = !VIDEO_RAM_CTR1;
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DDR_REFRESH_ON = VIDEO_RAM_CTR2;
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DDR_CONFIG = VIDEO_RAM_CTR3;
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FIFO_ACTIVE = VIDEO_RAM_CTR8;
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--------------------------------
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CPU_ROW_ADR[] = FB_ADR[26..14];
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CPU_BA[] = FB_ADR[13..12];
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CPU_COL_ADR[] = FB_ADR[11..2];
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nVRAS = !VRAS;
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nVCAS = !VCAS;
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nVWE = !VWE;
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SR_DDR_WR.CLK = DDRCLK0;
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SR_DDRWR_D_SEL.CLK = DDRCLK0;
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SR_VDMP[7..0].CLK = DDRCLK0;
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SR_FIFO_WRE.CLK = DDRCLK0;
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CPU_AC.CLK = DDRCLK0;
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FIFO_AC.CLK = DDRCLK0;
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BLITTER_AC.CLK = DDRCLK0;
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DDRWR_D_SEL1 = BLITTER_AC;
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-- SELECT LOGIC
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DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
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DDR_CS.CLK = MAIN_CLK;
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DDR_CS.ENA = FB_ALE;
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DDR_CS = DDR_SEL;
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-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
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CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
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# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
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# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
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CPU_REQ.CLK = DDR_SYNC_66M;
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CPU_REQ = CPU_SIG
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# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
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BUS_CYC.CLK = DDRCLK0;
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BUS_CYC = BUS_CYC & !BUS_CYC_END;
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-- STATE MACHINE SYNCHRONISIEREN -----------------
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MCS[].CLK = DDRCLK0;
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MCS0 = MAIN_CLK;
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MCS1 = MCS0;
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CPU_DDR_SYNC.CLK = DDRCLK0;
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CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN
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---------------------------------------------------
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VA_S[].CLK = DDRCLK0;
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BA_S[].CLK = DDRCLK0;
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VA[] = VA_S[];
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BA[] = BA_S[];
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VA_P[].CLK = DDRCLK0;
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BA_P[].CLK = DDRCLK0;
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-- DDR STATE MACHINE -----------------------------------------------
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DDR_SM.CLK = DDRCLK0;
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CASE DDR_SM IS
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WHEN DS_T1 =>
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IF DDR_REFRESH_REQ THEN
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DDR_SM = DS_R2;
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ELSE
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IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN?
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IF DDR_CONFIG THEN -- JA
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DDR_SM = DS_C2;
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ELSE
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IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE
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VA_S[] = CPU_ROW_ADR[];
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BA_S[] = CPU_BA[];
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CPU_AC = VCC;
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BUS_CYC = VCC;
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DDR_SM = DS_T2B;
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ELSE
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IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT
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VA_P[] = FIFO_ROW_ADR[];
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BA_P[] = FIFO_BA[];
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FIFO_AC = VCC; -- VORBESETZEN
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ELSE
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VA_P[] = BLITTER_ROW_ADR[];
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BA_P[] = BLITTER_BA[];
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BLITTER_AC = VCC; -- VORBESETZEN
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END IF;
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DDR_SM = DS_T2A;
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END IF;
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END IF;
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ELSE
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DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN
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END IF;
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END IF;
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WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
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IF DDR_SEL & (nFB_WR # !LINE) THEN
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VRAS = VCC;
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VA[] = FB_AD[26..14];
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BA[] = FB_AD[13..12];
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VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE
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CPU_AC = VCC;
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BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
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ELSE
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VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
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VA[] = VA_P[];
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BA[] = BA_P[];
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VA_S[10] = !(FIFO_AC & FIFO_REQ);
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FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
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FIFO_AC = FIFO_AC & FIFO_REQ;
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BLITTER_AC = BLITTER_AC & BLITTER_REQ;
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END IF;
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DDR_SM = DS_T3;
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WHEN DS_T2B =>
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VRAS = VCC;
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FIFO_BANK_NOT_OK = VCC;
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CPU_AC = VCC;
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BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
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DDR_SM = DS_T3;
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WHEN DS_T3 =>
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CPU_AC = CPU_AC;
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FIFO_AC = FIFO_AC;
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BLITTER_AC = BLITTER_AC;
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VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
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IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
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DDR_SM = DS_T4W;
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ELSE
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IF CPU_AC THEN -- CPU?
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VA_S[9..0] = CPU_COL_ADR[];
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BA_S[] = CPU_BA[];
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DDR_SM = DS_T4R;
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ELSE
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IF FIFO_AC THEN -- FIFO?
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VA_S[9..0] = FIFO_COL_ADR[];
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BA_S[] = FIFO_BA[];
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DDR_SM = DS_T4F;
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ELSE
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IF BLITTER_AC THEN
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VA_S[9..0] = BLITTER_COL_ADR[];
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BA_S[] = BLITTER_BA[];
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DDR_SM = DS_T4R;
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ELSE
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DDR_SM = DS_N8;
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END IF;
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END IF;
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END IF;
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END IF;
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-- READ
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WHEN DS_T4R =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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VCAS = VCC;
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SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
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SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
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DDR_SM = DS_T5R;
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WHEN DS_T5R =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
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VA_S[9..0] = FIFO_COL_ADR[];
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VA_S[10] = GND; -- MANUEL PRECHARGE
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BA_S[] = FIFO_BA[];
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DDR_SM = DS_T6F;
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ELSE
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VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
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DDR_SM = DS_CB6;
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END IF;
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-- WRITE
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WHEN DS_T4W =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN
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VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
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DDR_SM = DS_T5W;
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WHEN DS_T5W =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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VA_S[9..0] = CPU_AC & CPU_COL_ADR[]
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# BLITTER_AC & BLITTER_COL_ADR[];
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VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
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BA_S[] = CPU_AC & CPU_BA[]
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# BLITTER_AC & BLITTER_BA[];
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SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
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SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
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DDR_SM = DS_T6W;
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WHEN DS_T6W =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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VCAS = VCC;
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VWE = VCC;
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SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
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SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
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SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
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DDR_SM = DS_T7W;
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WHEN DS_T7W =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
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SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
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DDR_SM = DS_T8W;
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WHEN DS_T8W =>
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DDR_SM = DS_T9W;
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WHEN DS_T9W =>
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IF FIFO_REQ & FIFO_BANK_OK THEN
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VA_S[9..0] = FIFO_COL_ADR[];
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VA_S[10] = GND; -- NON AUTO PRECHARGE
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BA_S[] = FIFO_BA[];
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DDR_SM = DS_T6F;
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ELSE
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VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
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DDR_SM = DS_CB6;
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END IF;
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-- FIFO READ
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WHEN DS_T4F =>
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VCAS = VCC;
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SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
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DDR_SM = DS_T5F;
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WHEN DS_T5F =>
|
||
IF FIFO_REQ THEN
|
||
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
|
||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
|
||
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
|
||
ELSE
|
||
VA_S[9..0] = FIFO_COL_ADR[]+4;
|
||
VA_S[10] = GND; -- NON AUTO PRECHARGE
|
||
BA_S[] = FIFO_BA[];
|
||
DDR_SM = DS_T6F;
|
||
END IF;
|
||
ELSE
|
||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
|
||
DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN
|
||
END IF;
|
||
|
||
WHEN DS_T6F =>
|
||
VCAS = VCC;
|
||
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
|
||
DDR_SM = DS_T7F;
|
||
|
||
WHEN DS_T7F =>
|
||
IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN
|
||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
|
||
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
|
||
ELSE
|
||
IF FIFO_REQ THEN
|
||
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
|
||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
|
||
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
|
||
ELSE
|
||
VA_S[9..0] = FIFO_COL_ADR[]+4;
|
||
VA_S[10] = GND; -- NON AUTO PRECHARGE
|
||
BA_S[] = FIFO_BA[];
|
||
DDR_SM = DS_T8F;
|
||
END IF;
|
||
ELSE
|
||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
|
||
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
|
||
END IF;
|
||
END IF;
|
||
|
||
WHEN DS_T8F =>
|
||
VCAS = VCC;
|
||
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
|
||
IF FIFO_MW[]<FIFO_LWM THEN -- NOTFALL?
|
||
DDR_SM = DS_T5F; -- JA->
|
||
ELSE
|
||
DDR_SM = DS_T9F;
|
||
END IF;
|
||
|
||
WHEN DS_T9F =>
|
||
IF FIFO_REQ THEN
|
||
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
|
||
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
|
||
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
|
||
ELSE
|
||
VA_P[9..0] = FIFO_COL_ADR[]+4;
|
||
VA_P[10] = GND; -- NON AUTO PRECHARGE
|
||
BA_P[] = FIFO_BA[];
|
||
DDR_SM = DS_T10F;
|
||
END IF;
|
||
ELSE
|
||
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
|
||
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
|
||
END IF;
|
||
|
||
WHEN DS_T10F =>
|
||
IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
|
||
VRAS = VCC;
|
||
VA[] = FB_AD[26..14];
|
||
BA[] = FB_AD[13..12];
|
||
CPU_AC = VCC;
|
||
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
|
||
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK
|
||
DDR_SM = DS_T3;
|
||
ELSE
|
||
VCAS = VCC;
|
||
VA[] = VA_P[];
|
||
BA[] = BA_P[];
|
||
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
|
||
DDR_SM = DS_T7F;
|
||
END IF;
|
||
|
||
-- CONFIG CYCLUS
|
||
WHEN DS_C2 =>
|
||
DDR_SM = DS_C3;
|
||
WHEN DS_C3 =>
|
||
BUS_CYC = CPU_REQ;
|
||
DDR_SM = DS_C4;
|
||
WHEN DS_C4 =>
|
||
IF CPU_REQ THEN
|
||
DDR_SM = DS_C5;
|
||
ELSE
|
||
DDR_SM = DS_T1;
|
||
END IF;
|
||
WHEN DS_C5 =>
|
||
DDR_SM = DS_C6;
|
||
WHEN DS_C6 =>
|
||
VA_S[] = FB_AD[12..0];
|
||
BA_S[] = FB_AD[14..13];
|
||
DDR_SM = DS_C7;
|
||
WHEN DS_C7 =>
|
||
VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
|
||
VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
|
||
VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
|
||
DDR_SM = DS_N8;
|
||
-- CLOSE FIFO BANK
|
||
WHEN DS_CB6 =>
|
||
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
|
||
VRAS = VCC; -- B<>NKE SCHLIESSEN
|
||
VWE = VCC;
|
||
DDR_SM = DS_N7;
|
||
WHEN DS_CB8 =>
|
||
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
|
||
VRAS = VCC; -- B<>NKE SCHLIESSEN
|
||
VWE = VCC;
|
||
DDR_SM = DS_T1;
|
||
-- REFRESH 70NS = 10 ZYCLEN
|
||
WHEN DS_R2 =>
|
||
IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
|
||
VRAS = VCC; -- ALLE BANKS SCHLIESSEN
|
||
VWE = VCC;
|
||
VA[10] = VCC;
|
||
FIFO_BANK_NOT_OK = VCC;
|
||
DDR_SM = DS_R4;
|
||
ELSE
|
||
VCAS = VCC;
|
||
VRAS = VCC;
|
||
DDR_SM = DS_R3;
|
||
END IF;
|
||
WHEN DS_R3 =>
|
||
DDR_SM = DS_R4;
|
||
WHEN DS_R4 =>
|
||
DDR_SM = DS_R5;
|
||
WHEN DS_R5 =>
|
||
DDR_SM = DS_R6;
|
||
WHEN DS_R6 =>
|
||
DDR_SM = DS_N5;
|
||
-- LEERSCHLAUFE
|
||
WHEN DS_N5 =>
|
||
DDR_SM = DS_N6;
|
||
WHEN DS_N6 =>
|
||
DDR_SM = DS_N7;
|
||
WHEN DS_N7 =>
|
||
DDR_SM = DS_N8;
|
||
WHEN DS_N8 =>
|
||
DDR_SM = DS_T1;
|
||
END CASE;
|
||
|
||
---------------------------------------------------------------
|
||
-- BLITTER ----------------------
|
||
-----------------------------------------
|
||
BLITTER_REQ.CLK = DDRCLK0;
|
||
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
|
||
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
|
||
BLITTER_BA1 = BLITTER_ADR13;
|
||
BLITTER_BA0 = BLITTER_ADR12;
|
||
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
|
||
------------------------------------------------------------------------------
|
||
-- FIFO ---------------------------------
|
||
--------------------------------------------------------
|
||
FIFO_REQ.CLK = DDRCLK0;
|
||
FIFO_REQ = (FIFO_MW[]<FIFO_MWM
|
||
# FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
|
||
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
|
||
FIFO_BA1 = VIDEO_ADR_CNT9;
|
||
FIFO_BA0 = VIDEO_ADR_CNT8;
|
||
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
|
||
FIFO_BANK_OK.CLK = DDRCLK0;
|
||
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
|
||
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
|
||
CLR_FIFO_SYNC.CLK =DDRCLK0;
|
||
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
|
||
CLEAR_FIFO_CNT.CLK = DDRCLK0;
|
||
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
|
||
STOP.CLK = DDRCLK0;
|
||
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
|
||
-- Z<>HLEN -----------------------------------------------
|
||
VIDEO_ADR_CNT[].CLK = DDRCLK0;
|
||
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
|
||
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
|
||
# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;
|
||
VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
|
||
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
|
||
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
|
||
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[7..4];
|
||
VDM_SEL[] = VIDEO_BASE_L_D[3..0];
|
||
-- AKTUELLE VIDEO ADRESSE
|
||
VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
|
||
VIDEO_ACT_ADR[3..0] = VDM_SEL[];
|
||
-----------------------------------------------------------------------------------------
|
||
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
|
||
-----------------------------------------------------------------------------------------
|
||
DDR_REFRESH_CNT[].CLK = CLK33M;
|
||
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
|
||
REFRESH_TIME.CLK = DDRCLK0;
|
||
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
|
||
DDR_REFRESH_SIG[].CLK = DDRCLK0;
|
||
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
|
||
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
|
||
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
|
||
DDR_REFRESH_REQ.CLK = DDRCLK0;
|
||
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
|
||
-----------------------------------------------------------
|
||
-- VIDEO REGISTER -----------------------
|
||
---------------------------------------------------------------------------------------------------------------------
|
||
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
|
||
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2
|
||
VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN
|
||
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
|
||
|
||
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
|
||
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2
|
||
VIDEO_BASE_M_D[] = FB_AD[23..16];
|
||
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
|
||
|
||
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
|
||
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2
|
||
VIDEO_BASE_H_D[] = FB_AD[23..16];
|
||
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
|
||
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
|
||
VIDEO_BASE_X_D[] = FB_AD[26..24];
|
||
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
|
||
|
||
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2
|
||
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
|
||
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
|
||
|
||
FB_AD[31..24] = lpm_bustri_BYT(
|
||
VIDEO_BASE_H & (0,VIDEO_BASE_X_D[])
|
||
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24])
|
||
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
|
||
|
||
FB_AD[23..16] = lpm_bustri_BYT(
|
||
VIDEO_BASE_L & VIDEO_BASE_L_D[]
|
||
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
|
||
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
|
||
# VIDEO_CNT_L & VIDEO_ACT_ADR[7..0]
|
||
# VIDEO_CNT_M & VIDEO_ACT_ADR[15..8]
|
||
# VIDEO_CNT_H & VIDEO_ACT_ADR[23..16]
|
||
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
|
||
END;
|
||
|