111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
/*
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* init_fpga.c
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*
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*/
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#include <MCF5475.h>
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#include "sysinit.h"
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#include <bas_printf.h>
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#define FPGA_STATUS (1 << 0)
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#define FPGA_CLOCK (1 << 1)
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#define FPGA_CONFIG (1 << 2)
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#define FPGA_DATA0 (1 << 3)
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#define FPGA_CONF_DONE (1 << 5)
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/*
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* load FPGA
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*/
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void init_fpga(void)
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{
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uint8_t *fpga_data;
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int i;
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xprintf("FPGA load config... ");
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MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
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MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
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while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
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MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high */
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while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */
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/*
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* excerpt from an Altera configuration manual:
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*
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* The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
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* configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
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* While nCONFIG is low, the device is in reset. When the device comes out of reset,
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* nCONFIG must be at a logic high level in order for the device to release the open-drain
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* nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
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* is ready to receive configuration data. Before and during configuration, all user I/O pins
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* are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
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* on the I/O pins which are on, before and during configuration.
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*
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* To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
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* configuration by holding the nCONFIG low. The device receives configuration data on its
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* DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
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* the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
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* which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
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* configuration is complete and initialization of the device can begin.
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*/
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fpga_data = (uint8_t *) FPGA_FLASH_DATA;
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do
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{
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uint8_t value = *fpga_data++;
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for (i = 0; i < 8; i++, value >>= 1)
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{
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if (value & 1)
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{
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/* bit set -> toggle DATA0 to high */
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MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
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}
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else
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{
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/* bit is cleared -> toggle DATA0 to low */
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MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
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}
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/* toggle DCLK -> FPGA reads the bit */
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MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
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MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
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}
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} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END));
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if (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END)
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{
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while (fpga_data++ < (uint8_t *) FPGA_FLASH_DATA_END)
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{
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/* toggle a little more since it's fun ;) */
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MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
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MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
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}
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xprintf("finished\r\n");
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}
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else
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{
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xprintf("FAILED!\r\n");
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}
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}
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