56 lines
1.5 KiB
Plaintext
Executable File
56 lines
1.5 KiB
Plaintext
Executable File
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
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#
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# firebee board initialization for bdmctrl
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#
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open $1
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reset
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sleep 1
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wait
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# set VBR
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write-ctrl 0x0801 0x00000000
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dump-register VBR
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# Turn on MBAR at 0x1000_0000
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write-ctrl 0x0C0F 0x10000000
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dump-register MBAR
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# Turn on RAMBAR0 at address 20000000
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write-ctrl 0x0C04 0x20000021
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# Turn on RAMBAR1 at address 20001000
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write-ctrl 0x0C05 0x20001021
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# Init CS0 (BootFLASH @ ff80_0000 - ff8F_FFFF 8Mbytes)
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write 0x10000500 0xff800000 4
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write 0x10000508 0x00041180 4
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write 0x10000504 0x003F0001 4
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wait
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# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 MBytes
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write 0x10000004 0x000002AA 4 # SDRAMDS configuration
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write 0x10000020 0x00000019 4 # SDRAM CS0 configuration (64Mbytes 0000_0000 - 03FF_FFFF)
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write 0x10000024 0x00000000 4 # SDRAM CS1 configuration
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write 0x10000028 0x00000000 4 # SDRAM CS2 configuration
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write 0x1000002C 0x00000000 4 # SDRAM CS3 configuration
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write 0x10000108 0x73711630 4 # SDCFG1
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write 0x1000010C 0x46370000 4 # SDCFG2
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write 0x10000104 0xE10B0002 4 # SDCR + IPALL
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write 0x10000100 0x40010000 4 # SDMR (write to LEMR)
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write 0x10000100 0x058D0000 4 # SDMR (write to LMR)
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sleep 100
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write 0x10000104 0xE10D0002 4 # SDCR + IPALL
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write 0x10000104 0xE10D0004 4 # SDCR + IREF (first refresh)
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write 0x10000104 0xE10D0004 4 # SDCR + IREF (first refresh)
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write 0x10000100 0x018D0000 4 # SDMR (write to LMR)
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write 0x10000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
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sleep 100
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load m548xlite_dbug_ram.elf
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execute
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wait
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