Markus Fröschle 132f136d3a relaxed timing and uncommented unneeded components in toplevel until timing issues are solved ...

added lots of set_false_path statements to sort out timing problems

2014-12-20 12:26:32 +00:00

..

backend/Altera/Firebee

relaxed timing and uncommented unneeded components in toplevel until timing issues are solved

2014-12-20 12:26:32 +00:00

rtl/vhdl

relaxed timing and uncommented unneeded components in toplevel until timing issues are solved

2014-12-20 12:26:32 +00:00

testbenches

started simulator for DDR RAM

2014-06-16 14:35:54 +00:00