147 lines
5.1 KiB
VHDL
147 lines
5.1 KiB
VHDL
-- megafunction wizard: %ALTDDIO_OUT%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altddio_out
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-- ============================================================
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-- File Name: altddio_out0.vhd
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-- Megafunction Name(s):
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-- altddio_out
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 8.1 Build 163 10/28/2008 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2008 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY altddio_out0 IS
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PORT
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(
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datain_h : IN STD_LOGIC ;
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datain_l : IN STD_LOGIC ;
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outclock : IN STD_LOGIC ;
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dataout : OUT STD_LOGIC
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);
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END altddio_out0;
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ARCHITECTURE SYN OF altddio_out0 IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC ;
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SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire4 : STD_LOGIC ;
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SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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COMPONENT altddio_out
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GENERIC (
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extend_oe_disable : STRING;
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intended_device_family : STRING;
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invert_output : STRING;
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lpm_type : STRING;
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oe_reg : STRING;
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power_up_high : STRING;
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width : NATURAL
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);
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PORT (
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dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
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outclock : IN STD_LOGIC ;
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datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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sub_wire1 <= sub_wire0(0);
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dataout <= sub_wire1;
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sub_wire2 <= datain_h;
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sub_wire3(0) <= sub_wire2;
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sub_wire4 <= datain_l;
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sub_wire5(0) <= sub_wire4;
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altddio_out_component : altddio_out
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GENERIC MAP (
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extend_oe_disable => "UNUSED",
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intended_device_family => "Cyclone III",
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invert_output => "OFF",
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lpm_type => "altddio_out",
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oe_reg => "UNUSED",
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power_up_high => "OFF",
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width => 1
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)
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PORT MAP (
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outclock => outclock,
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datain_h => sub_wire3,
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datain_l => sub_wire5,
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dataout => sub_wire0
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
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-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
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-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: PRIVATE: OE NUMERIC "0"
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-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
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-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
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-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
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-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
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-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
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-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
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-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
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-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
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-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
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-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
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-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
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-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
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-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
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-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
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-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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