50 lines
696 B
VHDL
50 lines
696 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.parameter_pkg.all;
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use work.types_pkg.all;
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entity tb_pipeline is generic (
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clk_period : time := 10 ns
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);
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end entity tb_pipeline;
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architecture uut of tb_pipeline is
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signal clk : std_logic := '0';
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signal rst : std_logic;
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component pipeline is port(
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clk, rst : std_logic
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);
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end component pipeline;
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begin
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uut: pipeline port map(
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clk => clk,
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rst => rst
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);
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clk_gen: process
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begin
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wait for clk_period/2;
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clk <= not clk;
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end process clk_gen;
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rst_gen : process
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begin
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rst <= '1';
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wait for 10 * clk_period;
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rst <= '0';
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wait;
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end process rst_gen;
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end architecture uut;
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