708 lines
12 KiB
Verilog
708 lines
12 KiB
Verilog
// Copyright (C) 1991-2009 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 9.1 Build 222 10/21/2009 SJ Full Version"
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// CREATED "Sat Mar 01 09:20:47 2014"
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module firebee1(
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FB_ALE,
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nFB_WR,
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CLK33M,
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nFB_CS1,
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nFB_CS2,
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nFB_CS3,
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FB_SIZE0,
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FB_SIZE1,
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nFB_BURST,
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LP_BUSY,
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nACSI_DRQ,
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nACSI_INT,
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RxD,
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CTS,
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RI,
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DCD,
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AMKB_RX,
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PIC_AMKB_RX,
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IDE_RDY,
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IDE_INT,
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WP_CF_CARD,
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TRACK00,
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nWP,
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nDCHG,
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SD_DATA0,
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SD_DATA1,
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SD_DATA2,
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SD_CARD_DEDECT,
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MIDI_IN,
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nSCSI_DRQ,
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SD_WP,
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nRD_DATA,
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nSCSI_C_D,
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nSCSI_I_O,
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nSCSI_MSG,
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nDACK0,
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PIC_INT,
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nFB_OE,
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TOUT0,
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nMASTER,
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DVI_INT,
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nDACK1,
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nPCI_INTD,
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nPCI_INTC,
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nPCI_INTB,
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nPCI_INTA,
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E0_INT,
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nINDEX,
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HD_DD,
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MAIN_CLK,
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nRSTO_MCF,
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CLK24M576,
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LP_STR,
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nACSI_ACK,
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nACSI_RESET,
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nACSI_CS,
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ACSI_DIR,
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ACSI_A1,
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nSCSI_ACK,
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nSCSI_ATN,
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SCSI_DIR,
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MIDI_OLR,
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MIDI_TLR,
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TxD,
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RTS,
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DTR,
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AMKB_TX,
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IDE_RES,
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nIDE_CS0,
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nIDE_CS1,
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nIDE_WR,
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nIDE_RD,
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nCF_CS0,
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nCF_CS1,
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nROM3,
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nROM4,
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nRP_UDS,
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nRP_LDS,
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nSDSEL,
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nWR_GATE,
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nWR,
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YM_QA,
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YM_QB,
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YM_QC,
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SD_CLK,
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DSA_D,
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nVWE,
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nVCAS,
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nVRAS,
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nVCS,
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nPD_VGA,
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CLK25M,
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TIN0,
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nSRCS,
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nSRBLE,
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nSRBHE,
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nSRWE,
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nDREQ1,
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LED_FPGA_OK,
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nSROE,
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VCKE,
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nFB_TA,
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nDDR_CLK,
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DDR_CLK,
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VSYNC_PAD,
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HSYNC_PAD,
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nBLANK_PAD,
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PIXEL_CLK_PAD,
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nSYNC,
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nMOT_ON,
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nSTEP_DIR,
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nSTEP,
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CLKUSB,
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LPDIR,
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SCSI_PAR,
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nSCSI_RST,
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nSCSI_SEL,
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nSCSI_BUSY,
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SD_CD_DATA3,
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SD_CMD_D1,
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ACSI_D,
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BA,
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FB_AD,
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IO,
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LP_D,
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nIRQ,
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SCSI_D,
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SRD,
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VA,
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VB,
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VD,
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VDM,
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VDQS,
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VG,
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VR
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);
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input FB_ALE;
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input nFB_WR;
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input CLK33M;
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input nFB_CS1;
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input nFB_CS2;
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input nFB_CS3;
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input FB_SIZE0;
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input FB_SIZE1;
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input nFB_BURST;
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input LP_BUSY;
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input nACSI_DRQ;
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input nACSI_INT;
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input RxD;
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input CTS;
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input RI;
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input DCD;
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input AMKB_RX;
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input PIC_AMKB_RX;
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input IDE_RDY;
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input IDE_INT;
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input WP_CF_CARD;
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input TRACK00;
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input nWP;
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input nDCHG;
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input SD_DATA0;
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input SD_DATA1;
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input SD_DATA2;
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input SD_CARD_DEDECT;
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input MIDI_IN;
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input nSCSI_DRQ;
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input SD_WP;
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input nRD_DATA;
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input nSCSI_C_D;
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input nSCSI_I_O;
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input nSCSI_MSG;
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input nDACK0;
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input PIC_INT;
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input nFB_OE;
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input TOUT0;
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input nMASTER;
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input DVI_INT;
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input nDACK1;
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input nPCI_INTD;
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input nPCI_INTC;
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input nPCI_INTB;
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input nPCI_INTA;
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input E0_INT;
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input nINDEX;
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input HD_DD;
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input MAIN_CLK;
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input nRSTO_MCF;
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output CLK24M576;
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output LP_STR;
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output nACSI_ACK;
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output nACSI_RESET;
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output nACSI_CS;
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output ACSI_DIR;
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output ACSI_A1;
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output nSCSI_ACK;
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output nSCSI_ATN;
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output SCSI_DIR;
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output MIDI_OLR;
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output MIDI_TLR;
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output TxD;
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output RTS;
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output DTR;
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output AMKB_TX;
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output IDE_RES;
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output nIDE_CS0;
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output nIDE_CS1;
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output nIDE_WR;
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output nIDE_RD;
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output nCF_CS0;
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output nCF_CS1;
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output nROM3;
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output nROM4;
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output nRP_UDS;
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output nRP_LDS;
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output nSDSEL;
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output nWR_GATE;
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output nWR;
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output YM_QA;
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output YM_QB;
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output YM_QC;
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output SD_CLK;
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output DSA_D;
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output nVWE;
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output nVCAS;
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output nVRAS;
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output nVCS;
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output nPD_VGA;
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output CLK25M;
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output TIN0;
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output nSRCS;
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output nSRBLE;
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output nSRBHE;
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output nSRWE;
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output nDREQ1;
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output LED_FPGA_OK;
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output nSROE;
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output VCKE;
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output nFB_TA;
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output nDDR_CLK;
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output DDR_CLK;
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output VSYNC_PAD;
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output HSYNC_PAD;
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output nBLANK_PAD;
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output PIXEL_CLK_PAD;
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output nSYNC;
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output nMOT_ON;
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output nSTEP_DIR;
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output nSTEP;
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output CLKUSB;
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output LPDIR;
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inout SCSI_PAR;
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inout nSCSI_RST;
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inout nSCSI_SEL;
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inout nSCSI_BUSY;
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inout SD_CD_DATA3;
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inout SD_CMD_D1;
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inout [7:0] ACSI_D;
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output [1:0] BA;
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inout [31:0] FB_AD;
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inout [17:0] IO;
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inout [7:0] LP_D;
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output [7:2] nIRQ;
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inout [7:0] SCSI_D;
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inout [15:0] SRD;
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output [12:0] VA;
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output [7:0] VB;
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inout [31:0] VD;
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output [3:0] VDM;
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inout [3:0] VDQS;
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output [7:0] VG;
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output [7:0] VR;
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wire [31:0] ACP_CONF;
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wire CLK25M_ALTERA_SYNTHESIZED;
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wire CLK2M;
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wire CLK2M4576;
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wire CLK48M;
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wire CLK500k;
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wire CLK_VIDEO;
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wire DDR_SYNC_66M;
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wire [3:0] DDRCLK;
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wire DMA_DRQ;
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wire DSP_INT;
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wire DSP_TA;
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wire FALCON_IO_TA;
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//GE wire [31:0] FB_ADR;
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reg [31:0] FB_ADR;
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wire FDC_CLK;
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wire HSYNC;
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wire INT_HANDLER_TA;
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wire LP_DIR;
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wire MOT_ON;
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wire nBLANK;
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wire nDREQ0;
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wire nMFP_INT;
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wire nRSTO;
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wire PIXEL_CLK;
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wire SD_CDM_D1;
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wire STEP;
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wire STEP_DIR;
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wire [17:0] TIMEBASE;
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wire VIDEO_RECONFIG;
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wire Video_TA;
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wire VR_BUSY;
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wire [8:0] VR_D;
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wire VR_RD;
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wire VR_WR;
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wire VSYNC;
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wire WR_DATA;
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wire WR_GATE;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_6;
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wire SYNTHESIZED_WIRE_7;
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wire SYNTHESIZED_WIRE_8;
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wire SYNTHESIZED_WIRE_9;
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wire SYNTHESIZED_WIRE_10;
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assign nDREQ1 = nDACK1;
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assign SYNTHESIZED_WIRE_9 = 0;
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assign SYNTHESIZED_WIRE_10 = 1;
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wire w_MAIN_CLK;
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assign w_MAIN_CLK = CLK33M;
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video b2v_Fredi_Aschwanden(
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.MAIN_CLK(w_MAIN_CLK),
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.nFB_CS1(nFB_CS1),
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.nFB_CS2(nFB_CS2),
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.nFB_CS3(nFB_CS3),
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.nFB_WR(nFB_WR),
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.FB_SIZE0(FB_SIZE0),
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.FB_SIZE1(FB_SIZE1),
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.nRSTO(nRSTO),
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.nFB_OE(nFB_OE),
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.FB_ALE(FB_ALE),
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.DDR_SYNC_66M(DDR_SYNC_66M),
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.CLK33M(CLK33M),
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.CLK25M(CLK25M_ALTERA_SYNTHESIZED),
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.CLK_VIDEO(CLK_VIDEO),
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.VR_BUSY(VR_BUSY),
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.DDRCLK(DDRCLK),
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.FB_AD(FB_AD),
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.FB_ADR(FB_ADR),
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.VD(VD),
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.VDQS(VDQS),
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.VR_D(VR_D),
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.VR_RD(VR_RD),
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.nBLANK(nBLANK),
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.nVWE(nVWE),
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.nVCAS(nVCAS),
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.nVRAS(nVRAS),
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.nVCS(nVCS),
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.nPD_VGA(nPD_VGA),
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.VCKE(VCKE),
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.VSYNC(VSYNC),
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.HSYNC(HSYNC),
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.nSYNC(nSYNC),
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.VIDEO_TA(Video_TA),
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.PIXEL_CLK(PIXEL_CLK),
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.VIDEO_RECONFIG(VIDEO_RECONFIG),
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.VR_WR(VR_WR),
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.BA(BA),
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.VA(VA),
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.VB(VB),
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.VDM(VDM),
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.VG(VG),
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.VR(VR));
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altpll1 b2v_inst(
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.inclk0(CLK33M),
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.c0(CLK500k),
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.c1(CLK2M4576),
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.c2(CLK24M576),
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.locked(SYNTHESIZED_WIRE_5));
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/*lpm_ff0 b2v_inst1(
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.clock(DDR_SYNC_66M),
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.enable(FB_ALE),
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.data(FB_AD),
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.q(FB_ADR));*/
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always @(posedge DDR_SYNC_66M)
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begin
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if (FB_ALE)
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FB_ADR <= FB_AD;
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end
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altpll2 b2v_inst12(
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.inclk0(w_MAIN_CLK),
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.c0(DDRCLK[0]),
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.c1(DDRCLK[1]),
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.c2(DDRCLK[2]),
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.c3(DDRCLK[3]),
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.c4(DDR_SYNC_66M));
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altpll3 b2v_inst13(
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.inclk0(CLK33M),
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.c0(CLK2M),
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.c1(FDC_CLK),
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.c2(CLK25M_ALTERA_SYNTHESIZED),
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.c3(CLK48M));
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assign nMOT_ON = ~MOT_ON;
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assign nSTEP_DIR = ~STEP_DIR;
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assign nSTEP = ~STEP;
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assign nWR = ~WR_DATA;
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lpm_counter0 b2v_inst18(
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.clock(CLK500k),
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.q(TIMEBASE));
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assign nWR_GATE = ~WR_GATE;
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assign nFB_TA = ~(Video_TA | INT_HANDLER_TA | DSP_TA | FALCON_IO_TA);
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altpll4 b2v_inst22(
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.inclk0(CLK48M),
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.areset(SYNTHESIZED_WIRE_0),
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.scanclk(SYNTHESIZED_WIRE_1),
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.scandata(SYNTHESIZED_WIRE_2),
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.scanclkena(SYNTHESIZED_WIRE_3),
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.configupdate(SYNTHESIZED_WIRE_4),
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.c0(CLK_VIDEO),
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.scandataout(SYNTHESIZED_WIRE_6),
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.scandone(SYNTHESIZED_WIRE_7)
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);
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assign SYNTHESIZED_WIRE_8 = ~nRSTO;
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assign nRSTO = SYNTHESIZED_WIRE_5 & nRSTO_MCF;
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assign LED_FPGA_OK = TIMEBASE[17];
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assign nDDR_CLK = ~DDRCLK[0];
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altddio_out3 b2v_inst5(
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.datain_h(VSYNC),
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.datain_l(VSYNC),
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.outclock(PIXEL_CLK),
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.dataout(VSYNC_PAD));
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altddio_out3 b2v_inst6(
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.datain_h(HSYNC),
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.datain_l(HSYNC),
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.outclock(PIXEL_CLK),
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.dataout(HSYNC_PAD));
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altpll_reconfig1 b2v_inst7(
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.reconfig(VIDEO_RECONFIG),
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.read_param(VR_RD),
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.write_param(VR_WR),
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.pll_scandataout(SYNTHESIZED_WIRE_6),
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.pll_scandone(SYNTHESIZED_WIRE_7),
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.clock(w_MAIN_CLK),
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.reset(SYNTHESIZED_WIRE_8),
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.counter_param(FB_ADR[8:6]),
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.counter_type(FB_ADR[5:2]),
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.data_in(FB_AD[24:16]),
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.busy(VR_BUSY),
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.pll_scandata(SYNTHESIZED_WIRE_2),
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.pll_scanclk(SYNTHESIZED_WIRE_1),
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.pll_scanclkena(SYNTHESIZED_WIRE_3),
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.pll_configupdate(SYNTHESIZED_WIRE_4),
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.pll_areset(SYNTHESIZED_WIRE_0),
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.data_out(VR_D));
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altddio_out3 b2v_inst8(
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.datain_h(nBLANK),
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.datain_l(nBLANK),
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.outclock(PIXEL_CLK),
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.dataout(nBLANK_PAD));
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altddio_out3 b2v_inst9(
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.datain_h(SYNTHESIZED_WIRE_9),
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.datain_l(SYNTHESIZED_WIRE_10),
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.outclock(PIXEL_CLK),
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.dataout(PIXEL_CLK_PAD));
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DSP b2v_Mathias_Alles(
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.CLK33M(CLK33M),
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.MAIN_CLK(w_MAIN_CLK),
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.nFB_OE(nFB_OE),
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.nFB_WR(nFB_WR),
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.nFB_CS1(nFB_CS1),
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.nFB_CS2(nFB_CS2),
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.FB_SIZE0(FB_SIZE0),
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.FB_SIZE1(FB_SIZE1),
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.nFB_BURST(nFB_BURST),
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.nRSTO(nRSTO),
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.nFB_CS3(nFB_CS3),
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.FB_AD(FB_AD),
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.FB_ADR(FB_ADR),
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.IO(IO),
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.SRD(SRD),
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.nSRCS(nSRCS),
|
|
.nSRBLE(nSRBLE),
|
|
.nSRBHE(nSRBHE),
|
|
.nSRWE(nSRWE),
|
|
.nSROE(nSROE),
|
|
.DSP_INT(DSP_INT),
|
|
.DSP_TA(DSP_TA)
|
|
|
|
|
|
);
|
|
|
|
|
|
interrupt_handler b2v_nobody(
|
|
.MAIN_CLK(w_MAIN_CLK),
|
|
.nFB_WR(nFB_WR),
|
|
.nFB_CS1(nFB_CS1),
|
|
.nFB_CS2(nFB_CS2),
|
|
.FB_SIZE0(FB_SIZE0),
|
|
.FB_SIZE1(FB_SIZE1),
|
|
.PIC_INT(PIC_INT),
|
|
.E0_INT(E0_INT),
|
|
.DVI_INT(DVI_INT),
|
|
.nPCI_INTA(nPCI_INTA),
|
|
.nPCI_INTB(nPCI_INTB),
|
|
.nPCI_INTC(nPCI_INTC),
|
|
.nPCI_INTD(nPCI_INTD),
|
|
.nMFP_INT(nMFP_INT),
|
|
.nFB_OE(nFB_OE),
|
|
.DSP_INT(DSP_INT),
|
|
.VSYNC(VSYNC),
|
|
.HSYNC(HSYNC),
|
|
.DMA_DRQ(DMA_DRQ),
|
|
.FB_AD(FB_AD),
|
|
.FB_ADR(FB_ADR),
|
|
.INT_HANDLER_TA(INT_HANDLER_TA),
|
|
.TIN0(TIN0),
|
|
.ACP_CONF(ACP_CONF),
|
|
.nRST(nRSTO), //GE
|
|
.nIRQ(nIRQ));
|
|
|
|
|
|
FalconIO_SDCard_IDE_CF b2v_Wolfgang_Foerster_and_Fredi_Aschwanden(
|
|
.CLK33M(CLK33M),
|
|
.MAIN_CLK(w_MAIN_CLK),
|
|
.CLK2M(CLK2M),
|
|
.CLK500k(CLK500k),
|
|
.nFB_CS1(nFB_CS1),
|
|
.FB_SIZE0(FB_SIZE0),
|
|
.FB_SIZE1(FB_SIZE1),
|
|
.nFB_BURST(nFB_BURST),
|
|
.LP_BUSY(LP_BUSY),
|
|
.nACSI_DRQ(nACSI_DRQ),
|
|
.nACSI_INT(nACSI_INT),
|
|
.nSCSI_DRQ(nSCSI_DRQ),
|
|
.nSCSI_MSG(nSCSI_MSG),
|
|
.MIDI_IN(MIDI_IN),
|
|
.RxD(RxD),
|
|
.CTS(CTS),
|
|
.RI(RI),
|
|
.DCD(DCD),
|
|
.AMKB_RX(AMKB_RX),
|
|
.PIC_AMKB_RX(PIC_AMKB_RX),
|
|
.IDE_RDY(IDE_RDY),
|
|
.IDE_INT(IDE_INT),
|
|
|
|
.nINDEX(nINDEX),
|
|
.TRACK00(TRACK00),
|
|
.nRD_DATA(nRD_DATA),
|
|
.nDCHG(nDCHG),
|
|
.SD_DATA0(SD_DATA0),
|
|
.SD_DATA1(SD_DATA1),
|
|
.SD_DATA2(SD_DATA2),
|
|
.SD_CARD_DEDECT(SD_CARD_DEDECT),
|
|
.SD_WP(SD_WP),
|
|
.nDACK0(nDACK0),
|
|
.nFB_WR(nFB_WR),
|
|
.WP_CF_CARD(WP_CF_CARD),
|
|
.nWP(nWP),
|
|
.nFB_CS2(nFB_CS2),
|
|
.nRSTO(nRSTO),
|
|
.nSCSI_C_D(nSCSI_C_D),
|
|
.nSCSI_I_O(nSCSI_I_O),
|
|
.CLK2M4576(CLK2M4576),
|
|
.nFB_OE(nFB_OE),
|
|
.VSYNC(VSYNC),
|
|
.HSYNC(HSYNC),
|
|
.DSP_INT(DSP_INT),
|
|
.nBLANK(nBLANK),
|
|
.FDC_CLK(FDC_CLK),
|
|
.FB_ALE(FB_ALE),
|
|
.HD_DD(HD_DD),
|
|
.SCSI_PAR(SCSI_PAR),
|
|
.nSCSI_SEL(nSCSI_SEL),
|
|
.nSCSI_BUSY(nSCSI_BUSY),
|
|
.nSCSI_RST(nSCSI_RST),
|
|
.SD_CD_DATA3(SD_CD_DATA3),
|
|
.SD_CDM_D1(SD_CDM_D1),
|
|
.ACP_CONF(ACP_CONF[31:24]),
|
|
.ACSI_D(ACSI_D),
|
|
.FB_AD(FB_AD),
|
|
.FB_ADR(FB_ADR),
|
|
.LP_D(LP_D),
|
|
.SCSI_D(SCSI_D),
|
|
.nIDE_CS1(nIDE_CS1),
|
|
.nIDE_CS0(nIDE_CS0),
|
|
.LP_STR(LP_STR),
|
|
.LP_DIR(LP_DIR),
|
|
.nACSI_ACK(nACSI_ACK),
|
|
.nACSI_RESET(nACSI_RESET),
|
|
.nACSI_CS(nACSI_CS),
|
|
.ACSI_DIR(ACSI_DIR),
|
|
.ACSI_A1(ACSI_A1),
|
|
.nSCSI_ACK(nSCSI_ACK),
|
|
.nSCSI_ATN(nSCSI_ATN),
|
|
.SCSI_DIR(SCSI_DIR),
|
|
.SD_CLK(SD_CLK),
|
|
.YM_QA(YM_QA),
|
|
.YM_QC(YM_QC),
|
|
.YM_QB(YM_QB),
|
|
.nSDSEL(nSDSEL),
|
|
.STEP(STEP),
|
|
.MOT_ON(MOT_ON),
|
|
.nRP_LDS(nRP_LDS),
|
|
.nRP_UDS(nRP_UDS),
|
|
.nROM4(nROM4),
|
|
.nROM3(nROM3),
|
|
.nCF_CS1(nCF_CS1),
|
|
.nCF_CS0(nCF_CS0),
|
|
.nIDE_RD(nIDE_RD),
|
|
.nIDE_WR(nIDE_WR),
|
|
.AMKB_TX(AMKB_TX),
|
|
.IDE_RES(IDE_RES),
|
|
.DTR(DTR),
|
|
.RTS(RTS),
|
|
.TxD(TxD),
|
|
.MIDI_OLR(MIDI_OLR),
|
|
.MIDI_TLR(MIDI_TLR),
|
|
|
|
.DSA_D(DSA_D),
|
|
.nMFP_INT(nMFP_INT),
|
|
.FALCON_IO_TA(FALCON_IO_TA),
|
|
.STEP_DIR(STEP_DIR),
|
|
.WR_DATA(WR_DATA),
|
|
.WR_GATE(WR_GATE),
|
|
.DMA_DRQ(DMA_DRQ)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
);
|
|
|
|
assign SD_CMD_D1 = SD_CDM_D1;
|
|
assign CLK25M = CLK25M_ALTERA_SYNTHESIZED;
|
|
assign DDR_CLK = DDRCLK[0];
|
|
assign CLKUSB = CLK48M;
|
|
assign LPDIR = LP_DIR;
|
|
|
|
endmodule
|