MEMORY { code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 } SECTIONS { _Bas_base = ABSOLUTE(0x1FE00000); _tos_base = ABSOLUTE(0xe00000); /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ ___BOOT_FLASH = ABSOLUTE(0xE0000000); ___BOOT_FLASH_SIZE = ABSOLUTE(0x00800000); /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ ___SDRAM = ABSOLUTE(0x00000000); ___SDRAM_SIZE = ABSOLUTE(0x20000000); /* VIDEO RAM BASIS */ __VRAM = ABSOLUTE(0x60000000); /* Memory mapped registers */ __MBAR = ABSOLUTE(0xFF000000); __MMUBAR = ABSOLUTE(0xFF040000); /* * 4KB on-chip Core SRAM0: -> exception table and exception stack */ __RAMBAR0 = ABSOLUTE(0xFF100000); __RAMBAR0_SIZE = ABSOLUTE(0x00001000); __SUP_SP = ABSOLUTE(__RAMBAR0 + __RAMBAR0_SIZE - 4); /* 4KB on-chip Core SRAM1: -> modified code */ __RAMBAR1 = ABSOLUTE(0xFF101000); __RAMBAR1_SIZE = ABSOLUTE(0x00001000); /* Systemveriablem:****************************************** */ /* RAMBAR0 0 bis 0x7FF -> exception vectoren */ _rt_mod = __RAMBAR0 + 0x800; _rt_ssp = __RAMBAR0 + 0x804; _rt_usp = __RAMBAR0 + 0x808; _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ _rt_asid = __RAMBAR0 + 0x814; /* 003 */ _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ _rt_sr = __RAMBAR0 + 0x82c; _d0_save = __RAMBAR0 + 0x830; _a7_save = __RAMBAR0 + 0x834; _video_tlb = __RAMBAR0 + 0x838; _video_sbt = __RAMBAR0 + 0x83C; _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ /**********************************************************/ /* 32KB on-chip System SRAM */ __SYS_SRAM = ABSOLUTE(0xFF010000); __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); .code : {} > code .text : { objs/startcf.o(.text) objs/sysinit.o(.text) objs/BaS.o(.text) objs/sd_card.o(.text) objs/cache.o(.text) objs/mmu.o(.text) objs/exceptions.o(.text) objs/supervisor.o(.text) objs/ewf.o(.text) objs/illegal_instruction.o(.text) objs/last.o(.text) } > code }