#!/usr/local/bin/bdmctrl -D2 -v9 -d9
#
# firebee board initialization for bdmctrl 
#
open $1
reset
sleep 1

wait



# Turn on MBAR at 0x1000_0000
write-ctrl 0x0C0F 0x10000000
dump-register MBAR

# Turn on RAMBAR0 at address 20000000 
write-ctrl 0x0C04 0x20000021

# Turn on RAMBAR1 at address 20001000
write-ctrl 0x0C05 0x20001021

# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes)
write 0x10000500 0xE0000000 4
write 0x10000508 0x00041180 4
write 0x10000504 0x003F0001 4
wait

# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 MBytes
write 0x10000004 0x000002AA 4	# SDRAMDS configuration
write 0x10000020 0x00000019 4	# SDRAM CS0 configuration (64Mbytes 0000_0000 - 03FF_FFFF)
write 0x10000024 0x00000000 4	# SDRAM CS1 configuration
write 0x10000028 0x00000000 4	# SDRAM CS2 configuration
write 0x1000002C 0x00000000 4	# SDRAM CS3 configuration

write 0x10000108 0x73711630 4	# SDCFG1
write 0x1000010C 0x46370000 4	# SDCFG2

write 0x10000104 0xE10B0002 4	# SDCR + IPALL
write 0x10000100 0x40010000 4	# SDMR (write to LEMR)
write 0x10000100 0x058D0000 4	# SDMR (write to LMR)
sleep 100
write 0x10000104 0xE10D0002 4	# SDCR + IPALL
write 0x10000104 0xE10D0004 4	# SDCR + IREF (first refresh)
write 0x10000104 0xE10D0004 4	# SDCR + IREF (first refresh)
write 0x10000100 0x018D0000 4	# SDMR (write to LMR)
write 0x10000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
sleep 100

load m548xlite_dbug_ram.elf .sec1 .sec2 .sec3

# set VBR
write-ctrl 0x0801 0x00000000
dump-register VBR

execute
wait