Markus Fröschle
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cbff11f5d8
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renamed files
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2014-12-20 08:22:10 +00:00 |
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Markus Fröschle
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91ea8fc622
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reformatted
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2014-12-20 01:21:36 +00:00 |
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Markus Fröschle
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3b0e69127f
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now gets accepted by Modelsim
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2014-09-01 14:24:55 +00:00 |
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Markus Fröschle
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bc33af04ab
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fixed various "comparison with different length" errors
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2014-08-20 05:44:46 +00:00 |
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Markus Fröschle
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27824cd8e6
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fixed wrong chip select for video frequency timer (VFT) register
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2014-08-17 08:47:35 +00:00 |
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Markus Fröschle
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9b1cb2255b
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fixed missing (not "translated" from the original .tdf) statements
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2014-08-14 05:33:56 +00:00 |
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Markus Fröschle
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cf659204c8
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fixed formatting
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2014-08-09 19:17:09 +00:00 |
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Markus Fröschle
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2aee4d9c45
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fixed a bug in wiring of I_RECONFIG (data_in was connected to FB_ADR(24 downto 16) instead ot FB_AD(24 downto 16) and reformatted files
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2014-08-08 17:48:19 +00:00 |
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Markus Fröschle
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cf56eece67
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fixed a few more problems resulting from changing libraries
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2014-08-06 19:49:32 +00:00 |
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Markus Fröschle
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4c5b6d02e9
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fixed formatting
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2014-08-04 20:50:39 +00:00 |
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Markus Fröschle
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b40ddd37fc
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2014-08-04 20:27:57 +00:00 |
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Markus Fröschle
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4c2be14e28
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removed all dependencies to obsolete ieee.std_logic_arith and ieee.std_logic_unsigned in favour of ieee.numeric_std. There are a few things that still need to be fixed because of that, however.
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2014-08-04 17:23:47 +00:00 |
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Markus Fröschle
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fe7d35a212
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fixed typo
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2014-07-09 19:14:40 +00:00 |
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Markus Fröschle
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90bc4c409e
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more testbench code
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2014-06-15 06:05:23 +00:00 |
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Markus Fröschle
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8d0ede14c8
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worked on testbench
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2014-06-11 16:41:25 +00:00 |
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Markus Fröschle
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2c29f6a232
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tried less restrictive option to speed up synthesis
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2014-06-10 06:52:16 +00:00 |
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Markus Fröschle
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727aa5bce9
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initial import after removal of FPGA_quartus
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2014-06-09 20:35:29 +00:00 |
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