Markus Fröschle
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2157aad3c4
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fix assignment vector length
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2016-04-27 05:24:49 +00:00 |
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Markus Fröschle
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ad11bc7f96
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fix number of bits to compare
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2016-04-26 19:58:21 +00:00 |
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Markus Fröschle
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85e924cc44
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reformatting
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2016-04-26 19:34:39 +00:00 |
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Markus Fröschle
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f58bbb5f6d
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simplify and fix errors
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2016-04-26 16:39:22 +00:00 |
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Markus Fröschle
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676422b0c4
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add function f_addr_cmp()
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2016-04-26 06:14:03 +00:00 |
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Markus Fröschle
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52c7e4a4a1
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change formatting
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2016-04-25 19:09:52 +00:00 |
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Markus Fröschle
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6bd7bf2a0b
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fix timing violation at border color assignment
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2016-04-14 18:11:14 +00:00 |
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Markus Fröschle
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848f101ea1
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fix hsync len calculation for Firebee mode
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2016-04-14 05:56:39 +00:00 |
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Markus Fröschle
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0d3c010348
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make it compile again
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2016-02-10 17:06:57 +00:00 |
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Markus Fröschle
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bdeeaa2746
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cast to std_logic_vector
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2016-01-19 17:36:29 +00:00 |
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Markus Fröschle
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90a4b52bf3
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modify to use WHEN statements instead of binary logic
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2016-01-19 15:50:36 +00:00 |
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Markus Fröschle
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5c01dc00b2
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remove specialised clocks
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2016-01-19 07:27:27 +00:00 |
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Markus Fröschle
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06fe2148cf
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removed more "indirect" clocks
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2016-01-19 07:07:31 +00:00 |
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Markus Fröschle
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d531d35825
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get rid of BUFFER parameters
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2016-01-18 18:32:50 +00:00 |
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Markus Fröschle
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8758f9d374
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hold time fix test
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2016-01-18 18:15:02 +00:00 |
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Markus Fröschle
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ef585d16c2
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start of flexbus_register implementation to simplify that
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2016-01-17 20:28:18 +00:00 |
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Markus Fröschle
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5a0a331c09
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fix 13MHz clock sdc
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2016-01-17 08:43:20 +00:00 |
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Markus Fröschle
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694d5386d1
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fix timing
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2016-01-16 21:38:17 +00:00 |
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Markus Fröschle
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e6cc4daf5c
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reformat
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2016-01-14 16:49:11 +00:00 |
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Markus Fröschle
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30227f5f4e
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reactivated delay chain
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2016-01-13 15:04:24 +00:00 |
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Markus Fröschle
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014d28e80f
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reformat
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2016-01-13 13:23:46 +00:00 |
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Markus Fröschle
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d3e950cb42
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finish conversion to vhdl
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2016-01-13 12:53:03 +00:00 |
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