Markus Fröschle
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40e6a71e47
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started testbench bus transaction implementation
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2014-06-13 06:26:42 +00:00 |
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Markus Fröschle
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05a13bdf16
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added clock signals
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2014-06-11 17:52:44 +00:00 |
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Markus Fröschle
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8d0ede14c8
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worked on testbench
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2014-06-11 16:41:25 +00:00 |
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Markus Fröschle
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2c29f6a232
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tried less restrictive option to speed up synthesis
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2014-06-10 06:52:16 +00:00 |
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Markus Fröschle
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3b6fc36db1
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removed dsp56k
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2014-06-09 20:37:34 +00:00 |
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Markus Fröschle
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727aa5bce9
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initial import after removal of FPGA_quartus
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2014-06-09 20:35:29 +00:00 |
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Matthias Alles
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af014dc0d6
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Initial checkin of DSP 56k VHDL code.
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2010-11-02 07:29:43 +00:00 |
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