fix ACP web address

altpll1.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2010 Altera Corporation
+Copyright (C) 1991-2014 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,83 +18,83 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
 (symbol
-	(rect 0 0 272 184)
+	(rect 0 0 272 176)
-	(text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10)))
+	(text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+	(text "inst" (rect 8 161 26 172)(font "Arial" ))
 	(port
 		(pt 0 64)
 		(input)
-		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 40 64)(line_width 1))
+		(line (pt 0 64)(pt 40 64))
 	)
 	(port
 		(pt 272 64)
 		(output)
-		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
+		(text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
-		(line (pt 272 64)(pt 224 64)(line_width 1))
 	)
 	(port
 		(pt 272 80)
 		(output)
-		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
-		(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
+		(text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
-		(line (pt 272 80)(pt 224 80)(line_width 1))
 	)
 	(port
 		(pt 272 96)
 		(output)
-		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
+		(text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
-		(line (pt 272 96)(pt 224 96)(line_width 1))
 	)
 	(port
 		(pt 272 112)
 		(output)
-		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
-		(text "locked" (rect 238 99 268 112)(font "Arial" (font_size 8)))
+		(text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
-		(line (pt 272 112)(pt 224 112)(line_width 1))
 	)
 	(drawing
-		(text "Cyclone III" (rect 211 169 258 181)(font "Arial" ))
+		(text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
-		(text "Clk " (rect 51 96 68 108)(font "Arial" ))
+		(text "Clk " (rect 51 91 117 192)(font "Arial" ))
-		(text "Ratio" (rect 83 96 105 108)(font "Arial" ))
+		(text "Ratio" (rect 82 91 187 192)(font "Arial" ))
-		(text "Ph (dg)" (rect 121 96 151 108)(font "Arial" ))
+		(text "Ph (dg)" (rect 119 91 269 192)(font "Arial" ))
-		(text "DC (%)" (rect 156 96 187 108)(font "Arial" ))
+		(text "DC (%)" (rect 154 91 340 192)(font "Arial" ))
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-		(text "50.00" (rect 160 111 183 123)(font "Arial" ))
+		(text "50.00" (rect 158 104 340 218)(font "Arial" ))
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+		(text "c1" (rect 54 117 118 244)(font "Arial" ))
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+		(text "50.00" (rect 158 117 340 244)(font "Arial" ))
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+		(text "c2" (rect 54 130 119 270)(font "Arial" ))
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 	)
 )

altpll1.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll1.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll1.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]

altpll1.vhd

@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -131,22 +131,22 @@ ARCHITECTURE SYN OF altpll1 IS
 		width_clock		: NATURAL
 	);
 	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
 			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC ;
+			locked	: OUT STD_LOGIC 
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
 	);
 	END COMPONENT;
 
 BEGIN
 	sub_wire7_bv(0 DOWNTO 0) <= "0";
 	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire3    <= sub_wire0(2);
+	sub_wire4    <= sub_wire0(2);
-	sub_wire2    <= sub_wire0(1);
+	sub_wire3    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
-	c0    <= sub_wire1;
+	c1    <= sub_wire1;
-	c1    <= sub_wire2;
+	locked    <= sub_wire2;
-	c2    <= sub_wire3;
+	c0    <= sub_wire3;
-	locked    <= sub_wire4;
+	c2    <= sub_wire4;
 	sub_wire5    <= inclk0;
 	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
 
@@ -218,7 +218,7 @@ BEGIN
 	PORT MAP (
 		inclk => sub_wire6,
 		clk => sub_wire0,
-		locked => sub_wire4
+		locked => sub_wire2
 	);
 
 
@@ -270,7 +270,7 @@ END SYN;
 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -406,17 +406,17 @@ END SYN;
 -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE

altpll2.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2010 Altera Corporation
+Copyright (C) 1991-2014 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,100 +18,100 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
 (symbol
-	(rect 0 0 304 248)
+	(rect 0 0 256 200)
-	(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
+	(text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 229 31 244)(font "Arial" ))
+	(text "inst" (rect 8 185 26 196)(font "Arial" ))
 	(port
-		(pt 0 72)
+		(pt 0 64)
 		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 48 72)(line_width 1))
+		(line (pt 0 64)(pt 40 64))
 	)
 	(port
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 		(output)
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+		(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
-		(line (pt 304 72)(pt 272 72)(line_width 1))
 	)
 	(port
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+		(pt 256 80)
 		(output)
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+		(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
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 		(output)
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 	)
 	(drawing
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-		(line (pt 48 56)(pt 48 232)(line_width 1))
+		(line (pt 40 48)(pt 40 183))
+		(line (pt 255 64)(pt 223 64))
+		(line (pt 255 80)(pt 223 80))
+		(line (pt 255 96)(pt 223 96))
+		(line (pt 255 112)(pt 223 112))
+		(line (pt 255 128)(pt 223 128))
 	)
 )

altpll2.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll2.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll2.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]

altpll2.vhd

@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS
 		width_clock		: NATURAL
 	);
 	PORT (
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
 	);
 	END COMPONENT;
 
@@ -149,14 +149,14 @@ BEGIN
 	sub_wire8_bv(0 DOWNTO 0) <= "0";
 	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
 	sub_wire5    <= sub_wire0(4);
-	sub_wire4    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(1);
+	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
-	c0    <= sub_wire1;
+	c1    <= sub_wire1;
-	c1    <= sub_wire2;
+	c3    <= sub_wire2;
-	c2    <= sub_wire3;
+	c0    <= sub_wire3;
-	c3    <= sub_wire4;
+	c2    <= sub_wire4;
 	c4    <= sub_wire5;
 	sub_wire6    <= inclk0;
 	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
@@ -293,7 +293,7 @@ END SYN;
 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -459,18 +459,18 @@ END SYN;
 -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 -- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 -- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE

altpll4.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2010 Altera Corporation
+Copyright (C) 1991-2014 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
 (symbol
-	(rect 0 0 376 232)
+	(rect 0 0 312 184)
-	(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10)))
+	(text "altpll4" (rect 139 0 181 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 213 31 228)(font "Arial" ))
+	(text "inst" (rect 8 169 26 180)(font "Arial" ))
 	(port
-		(pt 0 72)
+		(pt 0 64)
 		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 88 72)(line_width 1))
+		(line (pt 0 64)(pt 72 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8)))
+		(text "areset" (rect 4 67 35 79)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 72 80))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
+		(text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8)))
-		(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8)))
+		(text "scanclk" (rect 4 83 40 95)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 88 96)(line_width 1))
+		(line (pt 0 96)(pt 72 96))
 	)
 	(port
-		(pt 0 120)
+		(pt 0 112)
 		(input)
-		(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8)))
-		(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8)))
+		(text "scandata" (rect 4 99 48 111)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 88 120)(line_width 1))
+		(line (pt 0 112)(pt 72 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8)))
+		(text "scanclkena" (rect 4 115 57 127)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 72 128))
 	)
 	(port
 		(pt 0 144)
 		(input)
-		(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8)))
+		(text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8)))
-		(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8)))
+		(text "configupdate" (rect 4 131 66 143)(font "Arial" (font_size 8)))
-		(line (pt 0 144)(pt 88 144)(line_width 1))
+		(line (pt 0 144)(pt 72 144))
 	)
 	(port
-		(pt 0 168)
+		(pt 312 64)
-		(input)
-		(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 88 168)(line_width 1))
-	)
-	(port
-		(pt 0 192)
-		(input)
-		(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
-		(line (pt 0 192)(pt 88 192)(line_width 1))
-	)
-	(port
-		(pt 376 72)
 		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8)))
+		(text "c0" (rect 297 51 309 63)(font "Arial" (font_size 8)))
-		(line (pt 376 72)(pt 288 72)(line_width 1))
 	)
 	(port
-		(pt 376 96)
+		(pt 312 80)
 		(output)
-		(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8)))
+		(text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8)))
-		(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8)))
+		(text "scandataout" (rect 250 67 309 79)(font "Arial" (font_size 8)))
-		(line (pt 376 96)(pt 288 96)(line_width 1))
 	)
 	(port
-		(pt 376 120)
+		(pt 312 96)
 		(output)
-		(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8)))
+		(text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8)))
-		(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8)))
+		(text "scandone" (rect 262 83 309 95)(font "Arial" (font_size 8)))
-		(line (pt 376 120)(pt 288 120)(line_width 1))
 	)
 	(port
-		(pt 376 144)
+		(pt 312 112)
 		(output)
-		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
+		(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
-		(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8)))
+		(text "locked" (rect 277 99 308 111)(font "Arial" (font_size 8)))
-		(line (pt 376 144)(pt 288 144)(line_width 1))
 	)
 	(drawing
-		(text "Cyclone III" (rect 301 214 349 228)(font "Arial" ))
+		(text "Cyclone III" (rect 254 171 554 352)(font "Arial" ))
-		(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" ))
+		(text "inclk0 frequency: 48.000 MHz" (rect 82 93 290 196)(font "Arial" ))
-		(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 82 105 267 220)(font "Arial" ))
-		(text "Clk " (rect 99 167 116 181)(font "Arial" ))
+		(text "Clk " (rect 83 124 181 258)(font "Arial" ))
-		(text "Ratio" (rect 125 167 149 181)(font "Arial" ))
+		(text "Ratio" (rect 103 124 229 258)(font "Arial" ))
-		(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" ))
+		(text "Ph (dg)" (rect 129 124 289 258)(font "Arial" ))
-		(text "DC (%)" (rect 204 167 239 181)(font "Arial" ))
+		(text "DC (%)" (rect 164 124 360 258)(font "Arial" ))
-		(text "c0" (rect 103 185 115 199)(font "Arial" ))
+		(text "c0" (rect 86 137 183 284)(font "Arial" ))
-		(text "2/1" (rect 131 185 146 199)(font "Arial" ))
+		(text "2/1" (rect 108 137 229 284)(font "Arial" ))
-		(text "0.00" (rect 167 185 188 199)(font "Arial" ))
+		(text "0.00" (rect 135 137 289 284)(font "Arial" ))
-		(text "50.00" (rect 209 185 236 199)(font "Arial" ))
+		(text "50.00" (rect 168 137 360 284)(font "Arial" ))
-		(line (pt 0 0)(pt 377 0)(line_width 1))
+		(line (pt 0 0)(pt 313 0))
-		(line (pt 377 0)(pt 377 233)(line_width 1))
+		(line (pt 313 0)(pt 313 186))
-		(line (pt 0 233)(pt 377 233)(line_width 1))
+		(line (pt 0 186)(pt 313 186))
-		(line (pt 0 0)(pt 0 233)(line_width 1))
+		(line (pt 0 0)(pt 0 186))
-		(line (pt 96 164)(pt 246 164)(line_width 1))
+		(line (pt 80 122)(pt 196 122))
-		(line (pt 96 181)(pt 246 181)(line_width 1))
+		(line (pt 80 134)(pt 196 134))
-		(line (pt 96 199)(pt 246 199)(line_width 1))
+		(line (pt 80 147)(pt 196 147))
-		(line (pt 96 164)(pt 96 199)(line_width 1))
+		(line (pt 80 122)(pt 80 147))
-		(line (pt 122 164)(pt 122 199)(line_width 3))
+		(line (pt 100 122)(pt 100 147)(line_width 3))
-		(line (pt 156 164)(pt 156 199)(line_width 3))
+		(line (pt 126 122)(pt 126 147)(line_width 3))
-		(line (pt 201 164)(pt 201 199)(line_width 3))
+		(line (pt 161 122)(pt 161 147)(line_width 3))
-		(line (pt 245 164)(pt 245 199)(line_width 1))
+		(line (pt 195 122)(pt 195 147))
-		(line (pt 88 56)(pt 288 56)(line_width 1))
+		(line (pt 72 48)(pt 239 48))
-		(line (pt 288 56)(pt 288 216)(line_width 1))
+		(line (pt 239 48)(pt 239 168))
-		(line (pt 88 216)(pt 288 216)(line_width 1))
+		(line (pt 72 168)(pt 239 168))
-		(line (pt 88 56)(pt 88 216)(line_width 1))
+		(line (pt 72 48)(pt 72 168))
+		(line (pt 311 64)(pt 239 64))
+		(line (pt 311 80)(pt 239 80))
+		(line (pt 311 96)(pt 239 96))
+		(line (pt 311 112)(pt 239 112))
 	)
 )

altpll4.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll4.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll4.mif

@@ -1,4 +1,4 @@
--- Copyright (C) 1991-2010 Altera Corporation
+-- Copyright (C) 1991-2014 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
@@ -17,8 +17,8 @@
 --    Device Part: -
 --    Device Speed Grade: 8
 --    PLL Scan Chain: Fast PLL (144 bits)
---    File Name: C:\FireBee\FPGA\altpll4.mif
+--    File Name: /home/mfro/Dokumente/Development/workspace/FPGA_quartus_ori/altpll4.mif
---    Generated: Mon Dec 06 01:47:24 2010
+--    Generated: Fri Oct 30 21:50:08 2015
 
 WIDTH=1;
 DEPTH=144;

altpll4.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]

altpll4.tdf

@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -113,16 +113,16 @@ VARIABLE
 BEGIN
 
 	c0 = altpll_component.clk[0..0];
-	scandone = altpll_component.scandone;
 	scandataout = altpll_component.scandataout;
+	scandone = altpll_component.scandone;
 	locked = altpll_component.locked;
-	altpll_component.scanclkena = scanclkena;
+	altpll_component.areset = areset;
+	altpll_component.configupdate = configupdate;
 	altpll_component.inclk[0..0] = inclk0;
 	altpll_component.inclk[1..1] = GND;
-	altpll_component.scandata = scandata;
-	altpll_component.areset = areset;
 	altpll_component.scanclk = scanclk;
-	altpll_component.configupdate = configupdate;
+	altpll_component.scanclkena = scanclkena;
+	altpll_component.scandata = scandata;
 END;
 
 
@@ -166,7 +166,7 @@ END;
 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
@@ -277,22 +277,22 @@ END;
 -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
 -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
 -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
--- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
--- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
--- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
 -- Retrieval info: LIB_FILE: altera_mf

firebee1.qsf

@@ -41,7 +41,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
 
 # Pin & Location Assignments

firebee1.sdc

@@ -3,7 +3,7 @@
 # Synopsis design constraints for the Firebee project          #
 #                                                              #
 # This file is part of the Firebee ACP project.                #
-# http://www.experiment-s.de                                   #
+# http://www.firebee.org                                       #
 #                                                              #
 # Description:                                                 #
 #   timing constraints for the Firebee VHDL config             #