From fe7824eda3d1ce48063a717ab4d4bc3bd47b3d9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 11 Dec 2013 06:26:41 +0000 Subject: [PATCH] added code to access MIDI and IKBD in mmu.c --- BaS_gcc/include/acia.h | 8 +++---- BaS_gcc/sources/mmu.c | 47 ++++++++++++++++++++++++++++-------------- 2 files changed, 36 insertions(+), 19 deletions(-) diff --git a/BaS_gcc/include/acia.h b/BaS_gcc/include/acia.h index eefaf6a..65e95c2 100644 --- a/BaS_gcc/include/acia.h +++ b/BaS_gcc/include/acia.h @@ -4,9 +4,9 @@ /* * ACIA registers */ -#define keyctl volatile uint8_t *0xfffc00 -#define keybd volatile uint8_t *0xfffc02 -#define midictl volatile uint8_t *0xfffc04 -#define midi volatile uint8_t *0xfffc06 +#define keyctl 0xfffc00 +#define keybd 0xfffc02 +#define midictl 0xfffc04 +#define midi 0xfffc06 #endif /* _ACIA_H_ */ diff --git a/BaS_gcc/sources/mmu.c b/BaS_gcc/sources/mmu.c index 046aafc..e1a3ab9 100644 --- a/BaS_gcc/sources/mmu.c +++ b/BaS_gcc/sources/mmu.c @@ -1,4 +1,5 @@ #include "mmu.h" +#include "acia.h" /* * mmu.c @@ -365,24 +366,40 @@ void mmutr_miss(void) debug_print("MMU TLB MISS at 0x%08x\r\n", address); flush_and_invalidate_caches(); - /* add missed page to TLB */ - MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ + switch (address) + { + case keyctl: + case keybd: + /* do something to emulate the IKBD access */ + debug_print("IKBD access\r\n"); + break; - MCF_MMU_MMUDR = (address & 0xfff00000) | /* physical aligned to 1M */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x1) | /* cacheable copyback */ - MCF_MMU_MMUDR_R | /* read access enable */ - MCF_MMU_MMUDR_W | /* write access enable */ - MCF_MMU_MMUDR_X; /* execute access enable */ + case midictl: + case midi: + /* do something to emulate MIDI access */ + debug_print("MIDI ACIA access\r\n"); + break; - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + default: + /* add missed page to TLB */ + MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */ + MCF_MMU_MMUTR_SG | /* shared global */ + MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + MCF_MMU_MMUDR = (address & 0xfff00000) | /* physical aligned to 1M */ + MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ + MCF_MMU_MMUDR_CM(0x1) | /* cacheable copyback */ + MCF_MMU_MMUDR_R | /* read access enable */ + MCF_MMU_MMUDR_W | /* write access enable */ + MCF_MMU_MMUDR_X; /* execute access enable */ + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ + MCF_MMU_MMUOR_ACC | /* access TLB */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + } }