Firebee/FireBee_SVN
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fixed formatting errors

Browse Source
This commit is contained in:
Markus Fröschle
2014-12-20 08:48:21 +00:00
parent 599b23bdcf
commit fe27ee2e22
1 changed files with 51 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
vhdl/rtl/vhdl/Firebee/Firebee.vhd
View File

@@ -1,38 +1,38 @@
---------------------------------------------------------------------- ----------------------------------------------------------------------
---- ---- ---- ----
---- This file is part of the 'Firebee' project. ---- ---- This file is part of the 'Firebee' project. ----
---- http://acp.atari.ORg ---- ---- http://acp.atari.org ----
---- ---- ---- ----
---- Description: ---- ---- Description: ----
---- This design unit provides the toplevel of the 'Firebee' ---- ---- This design unit provides the toplevel of the 'Firebee' ----
---- computer. It is optimized fOR the use of an Altera Cyclone ---- ---- computer. It is optimized for the use of an Altera Cyclone ----
---- FPGA (EP3C40F484). This IP-CORe is based on the first edi- ---- ---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----
---- tion of the Firebee configware ORigINally provided by Fredi ---- ---- tion of the Firebee configware originally provided by Fredi ----
---- Ashwanden and Wolfgang Förster. This release is IN compa- ---- ---- Aschwanden and Wolfgang Förster. This release is in compa- ----
---- rision to the first edition completely written IN VHDL. ---- ---- rision to the first edition completely written in VHDL. ----
---- ---- ---- ----
---- AuthOR(s): ---- ---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@INventronik.de ---- ---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ---- ---- ----
---------------------------------------------------------------------- ----------------------------------------------------------------------
---- ---- ---- ----
---- Copyright (C) 2012 Wolfgang Förster ---- ---- Copyright (C) 2012 Wolfgang Förster ----
---- ---- ---- ----
---- This source file is free software; you can redistribute it ---- ---- This source file is free software; you can redistribute it ----
---- and/OR modIFy it under the terms of the GNU General Public ---- ---- and/OR modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ---- ---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, OR (at your option) any later ---- ---- version 2 of the License, or (at your option) any later ----
---- version. ---- ---- version. ----
---- ---- ---- ----
---- This program is distributed IN the hope that it will be ---- ---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; WITHOUT even the implied ---- ---- useful, but WITHOUT ANY WARRANTY; WITHOUT even the implied ----
---- warranty of MERCHANTABILITY OR FITNESS FOR A PARTICULAR ---- ---- warranty of MERCHANTABILITY OR FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License fOR mORe ---- ---- PURPOSE. See the GNU General Public License fOR mORe ----
---- details. ---- ---- details. ----
---- ---- ---- ----
---- You should have received a copy of the GNU General Public ---- ---- You should have received a copy of the GNU General Public ----
---- License along WITH this program; IF NOT, write to the Free ---- ---- License along with this program; If not, write to the Free ----
---- Software Foundation, Inc., 51 FranklIN Street, FIFth FloOR, ---- ---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ---- ---- Boston, MA 02110-1301, USA. ----
---- ---- ---- ----
---------------------------------------------------------------------- ----------------------------------------------------------------------
@@ -68,27 +68,27 @@
-- Several code cleanups: -- Several code cleanups:
-- Resolved the tri state logic IN all modules. The only tri states are now IN the -- Resolved the tri state logic IN all modules. The only tri states are now IN the
-- top level FIREBEE_V1. -- top level FIREBEE_V1.
-- Replaced several Altera lpm modules to achieve a manufacturer INdepENDant code. -- Replaced several Altera lpm modules to achieve a manufacturer independant code.
-- However we have still some modules like memORy OR FIFOs which are required up to now. -- However we have still some modules like memory OR FIFOs which are required up to now.
-- Removed the vdr latch. -- Removed the vdr latch.
-- Removed the AMKBD filter. -- Removed the AMKBD filter.
-- Updated all Suska-Codes (ACIA, MFP, 5380, 1772, 2149) to the latest code base. -- Updated all Suska-Codes (ACIA, MFP, 5380, 1772, 2149) to the latest code base.
-- The sound module wORks now on the positive clock edge. -- The sound module works now on the positive clock edge.
-- The multi function PORT wORks now on the positive clock edge. -- The multi function port works now on the positive clock edge.
-- NamINg conventions: -- Naming conventions:
-- Replaced the 'n' prefixes WITH 'n' postfixes to achieve consistent SIGNAL names. -- Replaced the 'n' prefixes WITH 'n' postfixes to achieve consistent signal names.
-- Replaced the old ACP_xx SIGNAL names by FBEE_xx (ACP is the old wORkINg title). -- Replaced the old ACP_xx signal names by FBEE_xx (ACP is the old working title).
-- Improvements (hopefully) -- Improvements (hopefully)
-- Fixed the video_reconfig strobe logic IN the video control section. -- Fixed the video_reconfig strobe logic IN the video control section.
-- Others: -- Others:
-- Provided file headers to all Firebee relevant design units. -- Provided file headers to all Firebee relevant design units.
-- Provided a timequest constraINt file. -- Provided a timequest constraint file.
-- Switched all code elements to English language. -- Switched all code elements to English language.
-- Provided a complete new file structure fOR the project. -- Provided a complete new file structure for the project.
-- --
LIBRARY wORk; LIBRARY work;
USE wORk.firebee_pkg.ALL; USE work.firebee_pkg.ALL;
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
@@ -118,7 +118,7 @@ ENTITY firebee IS
DACK1n : IN STD_LOGIC; DACK1n : IN STD_LOGIC;
DREQ1n : OUT STD_LOGIC; DREQ1n : OUT STD_LOGIC;
MASTERn : IN STD_LOGIC; -- determINes IF the Firebee is PCI master (='0') OR slave. Not used so far. MASTERn : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
TOUT0n : IN STD_LOGIC; -- Not used so far. TOUT0n : IN STD_LOGIC; -- Not used so far.
LED_FPGA_OK : OUT STD_LOGIC; LED_FPGA_OK : OUT STD_LOGIC;
@@ -266,7 +266,7 @@ ARCHITECTURE Structure of firebee is
COMPONENT altpll2 COMPONENT altpll2
PORT( PORT(
INclk0 : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ; c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ;
@@ -277,7 +277,7 @@ ARCHITECTURE Structure of firebee is
COMPONENT altpll3 COMPONENT altpll3
PORT( PORT(
INclk0 : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ; c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ;
@@ -524,7 +524,7 @@ BEGIN
scandata => pll_scandata, scandata => pll_scandata,
scanclkena => pll_scanclkena, scanclkena => pll_scanclkena,
configupdate => pll_configupdate, configupdate => pll_configupdate,
c0 => clk_video, -- configurable video clk, set to 96 MHz INitially c0 => clk_video, -- configurable video clk, set to 96 MHz initially
scandataOUT => pll_scandataout, scandataOUT => pll_scandataout,
scandone => pll_scandone scandone => pll_scandone
--locked => -- Not used. --locked => -- Not used.
@@ -535,7 +535,7 @@ BEGIN
reconfig => video_reconfig, reconfig => video_reconfig,
read_param => vr_rd, read_param => vr_rd,
write_param => vr_wr, write_param => vr_wr,
data_in => FB_AD(24 DOWNTO 16), -- FIXED: this looks like a typo. Must be FB_AD(24 DOWNTO 16) INstead of fb_adr(24 DOWNTO 16) data_in => FB_AD(24 DOWNTO 16), -- FIXED: this looks like a typo. Must be FB_AD(24 DOWNTO 16) instead of fb_adr(24 DOWNTO 16)
counter_type => fb_adr(5 DOWNTO 2), counter_type => fb_adr(5 DOWNTO 2),
counter_param => fb_adr(8 DOWNTO 6), counter_param => fb_adr(8 DOWNTO 6),
pll_scandataout => pll_scandataout, pll_scandataout => pll_scandataout,
@@ -711,20 +711,20 @@ BEGIN
END IF; END IF;
END PROCESS SYNCHRONIZATION; END PROCESS SYNCHRONIZATION;
VIDEO_OUT: PROCESS video_out : PROCESS
BEGIN BEGIN
WAIT UNTIL RISING_EDGE(clk_pixel_i); WAIT UNTIL RISING_EDGE(clk_pixel_i);
VSYNC <= vsync_i; VSYNC <= vsync_i;
HSYNC <= hsync_i; HSYNC <= hsync_i;
BLANKn <= blank_i_n; BLANKn <= blank_i_n;
END PROCESS VIDEO_OUT; END PROCESS video_out;
P_ddr_wr: PROCESS p_ddr_wr: PROCESS
BEGIN BEGIN
WAIT UNTIL RISING_EDGE(clk_ddr(3)); WAIT UNTIL RISING_EDGE(clk_ddr(3));
ddr_wr <= sr_ddr_wr; ddr_wr <= sr_ddr_wr;
ddrwr_d_sel(0) <= sr_ddrwr_d_sel; ddrwr_d_sel(0) <= sr_ddrwr_d_sel;
END PROCESS P_ddr_wr; END PROCESS p_ddr_wr;
vd_qs_en <= ddr_wr; vd_qs_en <= ddr_wr;
VD <= vd_out WHEN vd_en = '1' ELSE (OTHERS => 'Z'); VD <= vd_out WHEN vd_en = '1' ELSE (OTHERS => 'Z');
@@ -735,20 +735,20 @@ BEGIN
vd_qs_out(3) <= clk_ddr(0); vd_qs_out(3) <= clk_ddr(0);
VD_QS <= vd_qs_out WHEN vd_qs_en = '1' ELSE (OTHERS => 'Z'); VD_QS <= vd_qs_out WHEN vd_qs_en = '1' ELSE (OTHERS => 'Z');
DDR_DATA_IN_N: PROCESS ddr_data_in_n : PROCESS
BEGIN BEGIN
WAIT UNTIL RISING_EDGE(clk_ddr(1)); WAIT UNTIL RISING_EDGE(clk_ddr(1));
ddr_d_in_n <= VD; ddr_d_in_n <= VD;
END PROCESS DDR_DATA_IN_N; END PROCESS ddr_data_in_n;
-- --
DDR_DATA_IN_P: PROCESS ddr_data_in_p : PROCESS
BEGIN BEGIN
WAIT UNTIL RISING_EDGE(clk_ddr(1)); WAIT UNTIL RISING_EDGE(clk_ddr(1));
vdp_in(31 DOWNTO 0) <= VD; vdp_in(31 DOWNTO 0) <= VD;
vdp_in(63 DOWNTO 32) <= ddr_d_in_n; vdp_in(63 DOWNTO 32) <= ddr_d_in_n;
END PROCESS DDR_DATA_IN_P; END PROCESS ddr_data_in_p;
DDR_DATA_OUT_P: PROCESS(clk_ddr(3)) ddr_data_out_p : PROCESS(clk_ddr(3))
variable DDR_D_OUT_H : STD_LOGIC_VECTOR(31 DOWNTO 0); variable DDR_D_OUT_H : STD_LOGIC_VECTOR(31 DOWNTO 0);
variable DDR_D_OUT_L : STD_LOGIC_VECTOR(31 DOWNTO 0); variable DDR_D_OUT_L : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN BEGIN
@@ -758,13 +758,13 @@ BEGIN
vd_en <= sr_ddr_wr OR ddr_wr; vd_en <= sr_ddr_wr OR ddr_wr;
END IF; END IF;
-- --
case clk_ddr(3) is CASE clk_ddr(3) IS
WHEN '1' => vd_out <= DDR_D_OUT_H; WHEN '1' => vd_out <= DDR_D_OUT_H;
WHEN OTHERS => vd_out <= DDR_D_OUT_L; WHEN OTHERS => vd_out <= DDR_D_OUT_L;
END case; END CASE;
END PROCESS DDR_DATA_OUT_P; END PROCESS ddr_data_out_p;
WITH ddrwr_d_sel select WITH ddrwr_d_sel SELECT
vdp_out <= blitter_dout(63 DOWNTO 0) WHEN "11", vdp_out <= blitter_dout(63 DOWNTO 0) WHEN "11",
blitter_dout(127 DOWNTO 64) WHEN "10", blitter_dout(127 DOWNTO 64) WHEN "10",
fb_ddr(63 DOWNTO 0) WHEN "01", fb_ddr(63 DOWNTO 0) WHEN "01",
@@ -773,7 +773,7 @@ BEGIN
vd_en_i <= sr_ddr_wr OR ddr_wr; vd_en_i <= sr_ddr_wr OR ddr_wr;
VDP_Q_BUFFER: PROCESS vdp_q_buffer : PROCESS
BEGIN BEGIN
WAIT UNTIL RISING_EDGE(clk_ddr(0)); WAIT UNTIL RISING_EDGE(clk_ddr(0));
ddr_fb <= sr_ddr_fb & ddr_fb(4 DOWNTO 1); ddr_fb <= sr_ddr_fb & ddr_fb(4 DOWNTO 1);
@@ -786,7 +786,7 @@ BEGIN
vdp_q2 <= vdp_in(63 DOWNTO 32); vdp_q2 <= vdp_in(63 DOWNTO 32);
vdp_q3 <= vdp_in(31 DOWNTO 0); vdp_q3 <= vdp_in(31 DOWNTO 0);
END IF; END IF;
END PROCESS VDP_Q_BUFFER; END PROCESS vdp_q_buffer;
I_DDR_CTRL: DDR_CTRL I_DDR_CTRL: DDR_CTRL
PORT MAP( PORT MAP(