renamed mmutr_miss() to mmu_map_page() (that's what its doing)
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@@ -35,6 +35,6 @@ extern long video_tlb;
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extern long video_sbt;
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extern long video_sbt;
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extern void mmu_init(void);
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extern void mmu_init(void);
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extern void mmutr_miss(uint32_t address);
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extern void mmu_map_page(uint32_t virt, uint32_t phys);
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#endif /* _MMU_H_ */
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#endif /* _MMU_H_ */
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14
sys/mmu.c
14
sys/mmu.c
@@ -447,7 +447,7 @@ bool access_exception(uint32_t pc, uint32_t format_status)
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}
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}
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else /* map this page */
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else /* map this page */
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{
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{
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mmutr_miss(fault_address);
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mmu_map_page(fault_address, fault_address);
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return true;
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return true;
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}
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}
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}
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}
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@@ -456,16 +456,18 @@ bool access_exception(uint32_t pc, uint32_t format_status)
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}
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}
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void mmutr_miss(uint32_t address)
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void mmu_map_page(uint32_t virt, uint32_t phys)
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{
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{
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dbg("MMU TLB MISS accessing 0x%08x\r\n", address);
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dbg("%s: map virt=%p to phys=%p\r\n", virt, phys);
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/* add missed page to TLB */
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/*
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MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */
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* add page to TLB
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*/
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MCF_MMU_MMUTR = (virt & 0xfff00000) | /* virtual aligned to 1M */
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = (address & 0xfff00000) | /* physical aligned to 1M */
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MCF_MMU_MMUDR = (phys & 0xfff00000) | /* physical aligned to 1M */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(0x1) | /* cacheable copyback */
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MCF_MMU_MMUDR_CM(0x1) | /* cacheable copyback */
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MCF_MMU_MMUDR_R | /* read access enable */
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MCF_MMU_MMUDR_R | /* read access enable */
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