diff --git a/.gdbinit b/.gdbinit index 598dbde..f40c55a 100644 --- a/.gdbinit +++ b/.gdbinit @@ -1,5 +1,6 @@ #set disassemble-next-line on define tr + !killall m68k-bdm-gdbserver target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3 #target remote | m68k-bdm-gdbserver pipe /dev/tblcf3 #target dbug /dev/ttyS0 diff --git a/BaS_gcc.files b/BaS_gcc.files index 6b516fa..3cb404b 100644 --- a/BaS_gcc.files +++ b/BaS_gcc.files @@ -227,4 +227,5 @@ check.bdm COPYING COPYING.LESSER dump.bdm -mcf5474.gdb \ No newline at end of file +mcf5474.gdb +Makefile diff --git a/Makefile b/Makefile index c516cc5..70128ef 100644 --- a/Makefile +++ b/Makefile @@ -15,7 +15,7 @@ ifeq (Y,$(COMPILE_ELF)) TCPREFIX=m68k-elf- EXE=elf FORMAT=elf32-m68k -else +else TCPREFIX=m68k-atari-mint- EXE=s19 FORMAT=srec @@ -39,6 +39,7 @@ CFLAGS=-mcpu=5474 \ -Wa,--register-prefix-optional CFLAGS_OPTIMIZED = -mcpu=5474 \ -Wall \ + -g3 \ -O2 \ -fomit-frame-pointer \ -ffreestanding \ @@ -135,7 +136,7 @@ CSRCS= \ x86pcibios.c \ \ basflash.c \ - basflash_start.c + basflash_start.c ASRCS= \ @@ -283,21 +284,21 @@ $(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR)))) indent: $(CSRCS) indent $< - + .PHONY: tags tags: ctags $(patsubst %,%/*,$(VPATH)) - + .PHONY: printvars printvars: @$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) ifeq (MACHINE_M5484LITE,$$(MACHINE)) MNAME=m5484lite else ifeq (MACHINE_FIREBEE,$(MACHINE)) - MNAME=firebee + MNAME=firebee endif tools: - $(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o + $(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o $(NATIVECC) -o $(TOOLDIR)/s19header $(TOOLDIR)/s19header.o diff --git a/mcf5474.gdb b/mcf5474.gdb index c4559eb..616d8c4 100644 --- a/mcf5474.gdb +++ b/mcf5474.gdb @@ -5,7 +5,7 @@ define addresses set $vbr = 0x00000000 #monitor bdm-ctl-set 0x0801 0x00000000 - + set $mbar = 0xFF000000 #monitor bdm-ctl-set 0x0C0F 0xFF000000 @@ -22,30 +22,30 @@ end define setup-dram # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) -set *((long *) 0xFF000500) = 0xE0000000 -set *((long *) 0xFF000508) = 0x00041180 -set *((long *) 0xFF000504) = 0x007F0001 +set *((long *) 0xFF000500) = 0xE0000000 +set *((long *) 0xFF000508) = 0x00041180 +set *((long *) 0xFF000504) = 0x007F0001 # set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes -set *((long *) 0xFF000004) = 0x000002AA -set *((long *) 0xFF000020) = 0x0000001A -set *((long *) 0xFF000024) = 0x0800001A -set *((long *) 0xFF000028) = 0x1000001A -set *((long *) 0xFF00002C) = 0x1800001A -set *((long *) 0xFF000108) = 0x73622830 -set *((long *) 0xFF00010C) = 0x46770000 +set *((long *) 0xFF000004) = 0x000002AA +set *((long *) 0xFF000020) = 0x0000001A +set *((long *) 0xFF000024) = 0x0800001A +set *((long *) 0xFF000028) = 0x1000001A +set *((long *) 0xFF00002C) = 0x1800001A +set *((long *) 0xFF000108) = 0x73622830 +set *((long *) 0xFF00010C) = 0x46770000 -set *((long *) 0xFF000104) = 0xE10D0002 -set *((long *) 0xFF000100) = 0x40010000 -set *((long *) 0xFF000100) = 0x048D0000 -set *((long *) 0xFF000104) = 0xE10D0002 -set *((long *) 0xFF000104) = 0xE10D0004 -set *((long *) 0xFF000104) = 0xE10D0004 -set *((long *) 0xFF000100) = 0x008D0000 -set *((long *) 0xFF000104) = 0x710D0F00 +set *((long *) 0xFF000104) = 0xE10D0002 +set *((long *) 0xFF000100) = 0x40010000 +set *((long *) 0xFF000100) = 0x048D0000 +set *((long *) 0xFF000104) = 0xE10D0002 +set *((long *) 0xFF000104) = 0xE10D0004 +set *((long *) 0xFF000104) = 0xE10D0004 +set *((long *) 0xFF000100) = 0x008D0000 +set *((long *) 0xFF000104) = 0x710D0F00 end define cu @@ -61,6 +61,10 @@ define ib setup-dram end +define run + continue +end + tr ib -load +load firebee/ram.elf diff --git a/sys/exceptions.S b/sys/exceptions.S index a335ee3..237485c 100644 --- a/sys/exceptions.S +++ b/sys/exceptions.S @@ -509,7 +509,7 @@ irq6: // MFP interrupt from FPGA movem.l (sp),d0-d1/a0-a1 // restore registers saved above lea 4 * 4(sp),sp // adjust stack - bra irq6_os // call OS handler + beq irq6_os // call OS handler rte irq6_os: // call native OS irq6 handler diff --git a/sys/mmu.c b/sys/mmu.c index 02ec821..07277e1 100644 --- a/sys/mmu.c +++ b/sys/mmu.c @@ -55,19 +55,19 @@ */ inline uint32_t set_asid(uint32_t value) { - extern long rt_asid; - uint32_t ret = rt_asid; + extern long rt_asid; + uint32_t ret = rt_asid; - __asm__ __volatile__( - "movec %[value],ASID\n\t" - : /* no output */ - : [value] "r" (value) - : - ); + __asm__ __volatile__( + "movec %[value],ASID\n\t" + : /* no output */ + : [value] "r" (value) + : + ); - rt_asid = value; + rt_asid = value; - return ret; + return ret; } @@ -77,18 +77,18 @@ inline uint32_t set_asid(uint32_t value) */ inline uint32_t set_acr0(uint32_t value) { - extern uint32_t rt_acr0; - uint32_t ret = rt_acr0; + extern uint32_t rt_acr0; + uint32_t ret = rt_acr0; - __asm__ __volatile__( - "movec %[value],ACR0\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr0 = value; + __asm__ __volatile__( + "movec %[value],ACR0\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr0 = value; - return ret; + return ret; } /* @@ -97,18 +97,18 @@ inline uint32_t set_acr0(uint32_t value) */ inline uint32_t set_acr1(uint32_t value) { - extern uint32_t rt_acr1; - uint32_t ret = rt_acr1; + extern uint32_t rt_acr1; + uint32_t ret = rt_acr1; - __asm__ __volatile__( - "movec %[value],ACR1\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr1 = value; + __asm__ __volatile__( + "movec %[value],ACR1\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr1 = value; - return ret; + return ret; } @@ -118,18 +118,18 @@ inline uint32_t set_acr1(uint32_t value) */ inline uint32_t set_acr2(uint32_t value) { - extern uint32_t rt_acr2; - uint32_t ret = rt_acr2; + extern uint32_t rt_acr2; + uint32_t ret = rt_acr2; - __asm__ __volatile__( - "movec %[value],ACR2\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr2 = value; + __asm__ __volatile__( + "movec %[value],ACR2\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr2 = value; - return ret; + return ret; } /* @@ -138,35 +138,35 @@ inline uint32_t set_acr2(uint32_t value) */ inline uint32_t set_acr3(uint32_t value) { - extern uint32_t rt_acr3; - uint32_t ret = rt_acr3; + extern uint32_t rt_acr3; + uint32_t ret = rt_acr3; - __asm__ __volatile__( - "movec %[value],ACR3\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr3 = value; + __asm__ __volatile__( + "movec %[value],ACR3\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr3 = value; - return ret; + return ret; } inline uint32_t set_mmubar(uint32_t value) { - extern uint32_t rt_mmubar; - uint32_t ret = rt_mmubar; + extern uint32_t rt_mmubar; + uint32_t ret = rt_mmubar; - __asm__ __volatile__( - "movec %[value],MMUBAR\n\t" - : /* no output */ - : [value] "r" (value) - : /* no clobber */ - ); - rt_mmubar = value; - NOP(); + __asm__ __volatile__( + "movec %[value],MMUBAR\n\t" + : /* no output */ + : [value] "r" (value) + : /* no clobber */ + ); + rt_mmubar = value; + NOP(); - return ret; + return ret; } @@ -181,229 +181,229 @@ extern uint8_t _FASTRAM_END[]; struct mmu_mapping { - uint32_t phys; - uint32_t virt; - uint32_t length; - uint32_t pagesize; - struct map_flags flags; + uint32_t phys; + uint32_t virt; + uint32_t length; + uint32_t pagesize; + struct map_flags flags; }; static struct mmu_mapping locked_map[] = { - { - /* Falcon video memory. Needs special care */ - 0xd00000, - 0x60d00000, - 0x100000, - MMU_PAGE_SIZE_1M, - { CACHE_WRITETHROUGH, SV_USER, SCA_PAGE_ID, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, + { + /* Falcon video memory. Needs special care */ + 0xd00000, + 0x60d00000, + 0x100000, + MMU_PAGE_SIZE_1M, + { CACHE_WRITETHROUGH, SV_USER, SCA_PAGE_ID, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, }; static int num_locked_mmu_maps = sizeof(locked_map) / sizeof(struct mmu_mapping); static struct mmu_mapping memory_map[] = { - /* map system vectors supervisor-protected */ - { - 0, - 0, - 0x800, - MMU_PAGE_SIZE_1K, - { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - { - 0x800, - 0x800, - 0x800, - MMU_PAGE_SIZE_1K, - { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - { - /* when the first 4k are filled with 1k pages, we can switch to 8k pages */ - 0x1000, - 0x1000, - 0xff000, - MMU_PAGE_SIZE_8K, - { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - { - /* arrived at a 1Meg border, we can switch to 1Meg pages */ - 0x100000, - 0x100000, - 0xc00000, - MMU_PAGE_SIZE_1M, - { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - /* Falcon video ram left out intentionally here (see above) */ - { - /* ROM */ - 0xe00000, - 0xe00000, - 0x100000, - MMU_PAGE_SIZE_1M, - { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_EXECUTE }, - }, - { - /* FASTRAM */ - 0x1000000, - 0x1000000, - (uint32_t) _FASTRAM_END - 0x1000000, - MMU_PAGE_SIZE_1M, - { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - { - /* MBAR */ - MBAR_ADDRESS, - MBAR_ADDRESS, - 0x100000, - MMU_PAGE_SIZE_1M, - { CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE }, - }, - { - /* RAMBAR0 */ - RAMBAR0_ADDRESS, - RAMBAR0_ADDRESS, - (uint32_t) _RAMBAR0_SIZE, - MMU_PAGE_SIZE_1K, - { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - { - /* RAMBAR1 */ - RAMBAR1_ADDRESS, - RAMBAR1_ADDRESS, - (uint32_t) _RAMBAR1_SIZE, - MMU_PAGE_SIZE_1K, - { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - { - /* SYSTEM SRAM */ - SYS_SRAM_ADDRESS, - SYS_SRAM_ADDRESS, - (uint32_t) _SYS_SRAM_SIZE, - MMU_PAGE_SIZE_8K, - { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, - }, - { - /* Firebee FPGA registers */ - (uint32_t) 0xf0000000, - (uint32_t) 0xf0000000, - (uint32_t) 0x08000000, - MMU_PAGE_SIZE_1M, - { CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE }, - }, - { - /* Falcon I/O registers */ - (uint32_t) 0xfff00000, - (uint32_t) 0xfff00000, - (uint32_t) 0x100000, - MMU_PAGE_SIZE_1M, - { CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE }, - }, - { - /* the same, but different virtual address */ - (uint32_t) 0x00f00000, - (uint32_t) 0xfff00000, - (uint32_t) 0x100000, - MMU_PAGE_SIZE_1M, - { CACHE_NOCACHE_PRECISE, SV_PROTECT, ACCESS_READ | ACCESS_WRITE }, - } + /* map OS system vectors supervisor-protected */ + { + 0, + 0, + 0x800, + MMU_PAGE_SIZE_1K, + { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + { + 0x800, + 0x800, + 0x800, + MMU_PAGE_SIZE_1K, + { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + { + /* when the first 4k are filled with 1k pages, we can switch to 8k pages */ + 0x1000, + 0x1000, + 0xff000, + MMU_PAGE_SIZE_8K, + { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + { + /* arrived at a 1Meg border, we can switch to 1Meg pages */ + 0x100000, + 0x100000, + 0xc00000, + MMU_PAGE_SIZE_1M, + { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + /* Falcon video ram left out intentionally here (see above) */ + { + /* ROM */ + 0xe00000, + 0xe00000, + 0x100000, + MMU_PAGE_SIZE_1M, + { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_EXECUTE }, + }, + { + /* FASTRAM */ + 0x1000000, + 0x1000000, + (uint32_t) _FASTRAM_END - 0x1000000, + MMU_PAGE_SIZE_1M, + { CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + { + /* MBAR */ + MBAR_ADDRESS, + MBAR_ADDRESS, + 0x100000, + MMU_PAGE_SIZE_1M, + { CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE }, + }, + { + /* RAMBAR0 */ + RAMBAR0_ADDRESS, + RAMBAR0_ADDRESS, + (uint32_t) _RAMBAR0_SIZE, + MMU_PAGE_SIZE_1K, + { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + { + /* RAMBAR1 */ + RAMBAR1_ADDRESS, + RAMBAR1_ADDRESS, + (uint32_t) _RAMBAR1_SIZE, + MMU_PAGE_SIZE_1K, + { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + { + /* SYSTEM SRAM */ + SYS_SRAM_ADDRESS, + SYS_SRAM_ADDRESS, + (uint32_t) _SYS_SRAM_SIZE, + MMU_PAGE_SIZE_8K, + { CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE }, + }, + { + /* Firebee FPGA registers */ + (uint32_t) 0xf0000000, + (uint32_t) 0xf0000000, + (uint32_t) 0x08000000, + MMU_PAGE_SIZE_1M, + { CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE }, + }, + { + /* Falcon I/O registers */ + (uint32_t) 0xfff00000, + (uint32_t) 0xfff00000, + (uint32_t) 0x100000, + MMU_PAGE_SIZE_1M, + { CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE }, + }, + { + /* the same, but different virtual address */ + (uint32_t) 0x00f00000, + (uint32_t) 0xfff00000, + (uint32_t) 0x100000, + MMU_PAGE_SIZE_1M, + { CACHE_NOCACHE_PRECISE, SV_PROTECT, ACCESS_READ | ACCESS_WRITE }, + } }; static int num_mmu_maps = sizeof(memory_map) / sizeof(struct mmu_mapping); static struct mmu_mapping *lookup_mapping(uint32_t virt) { - int i; + int i; - /* - * dumb, for now - */ + /* + * dumb, for now + */ - for (i = 0; i < num_mmu_maps; i++) - { - if (virt >= memory_map[i].virt && virt <= memory_map[i].virt + memory_map[i].length - 1) - return &memory_map[i]; - } - return NULL; + for (i = 0; i < num_mmu_maps; i++) + { + if (virt >= memory_map[i].virt && virt <= memory_map[i].virt + memory_map[i].length - 1) + return &memory_map[i]; + } + return NULL; } void mmu_init(void) { - extern uint8_t _MMUBAR[]; - uint32_t MMUBAR = (uint32_t) &_MMUBAR[0]; - int i; + extern uint8_t _MMUBAR[]; + uint32_t MMUBAR = (uint32_t) &_MMUBAR[0]; + int i; - set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */ + set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */ - /* - * need to set data ACRs in a way that supervisor access to all memory regions - * becomes possible. Otherways it might be that the supervisor stack ends up in an unmapped - * region when further MMU TLB entries force a page steal. This would lead to a double - * fault since the CPU wouldn't be able to push its exception stack frame during an access - * exception - */ + /* + * need to set data ACRs in a way that supervisor access to all memory regions + * becomes possible. Otherways it might be that the supervisor stack ends up in an unmapped + * region when further MMU TLB entries force a page steal. This would lead to a double + * fault since the CPU wouldn't be able to push its exception stack frame during an access + * exception + */ - /* set data access attributes in ACR0 and ACR1 */ + /* set data access attributes in ACR0 and ACR1 */ - set_acr0(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */ - ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */ - ACR_CACHE_MODE(CACHE_WRITETHROUGH) | /* cacheable, write through */ - ACR_ADDRESS_MASK_MODE(1) | /* region 13 MByte */ - ACR_S(ACR_S_SUPERVISOR_MODE) | /* memory only visible from supervisor mode */ - ACR_E(1) | /* enable ACR */ - ACR_ADMSK(0x0a) | /* cover 12 MByte from 0x0 */ - ACR_BA(0)); /* start from 0x0 */ + set_acr0(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */ + ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */ + ACR_CACHE_MODE(CACHE_WRITETHROUGH) | /* cacheable, write through */ + ACR_ADDRESS_MASK_MODE(1) | /* region 13 MByte */ + ACR_S(ACR_S_SUPERVISOR_MODE) | /* memory only visible from supervisor mode */ + ACR_E(1) | /* enable ACR */ + ACR_ADMSK(0x0a) | /* cover 12 MByte from 0x0 */ + ACR_BA(0)); /* start from 0x0 */ - set_acr1(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */ - ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */ - ACR_CACHE_MODE(CACHE_WRITETHROUGH) | /* cacheable, write through */ - ACR_ADDRESS_MASK_MODE(0) | /* region > 16 MByte */ - ACR_S(ACR_S_SUPERVISOR_MODE) | /* memory only visible from supervisor mode */ - ACR_E(1) | /* enable ACR */ - ACR_ADMSK(0x1f) | /* cover 495 MByte from 0x1000000 */ - ACR_BA(0x01000000)); /* all Fast RAM */ + set_acr1(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */ + ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */ + ACR_CACHE_MODE(CACHE_WRITETHROUGH) | /* cacheable, write through */ + ACR_ADDRESS_MASK_MODE(0) | /* region > 16 MByte */ + ACR_S(ACR_S_SUPERVISOR_MODE) | /* memory only visible from supervisor mode */ + ACR_E(1) | /* enable ACR */ + ACR_ADMSK(0x1f) | /* cover 495 MByte from 0x1000000 */ + ACR_BA(0x01000000)); /* all Fast RAM */ - /* - * set instruction access attributes in ACR2 and ACR3. This is the same as above, basically: - * enable supervisor access to all SDRAM - */ + /* + * set instruction access attributes in ACR2 and ACR3. This is the same as above, basically: + * enable supervisor access to all SDRAM + */ - set_acr2(ACR_WRITE_PROTECT(0) | - ACR_SUPERVISOR_PROTECT(0) | - ACR_CACHE_MODE(CACHE_WRITETHROUGH) | - ACR_ADDRESS_MASK_MODE(1) | - ACR_S(ACR_S_SUPERVISOR_MODE) | - ACR_E(1) | - ACR_ADMSK(0x0c) | - ACR_BA(0x0)); + set_acr2(ACR_WRITE_PROTECT(0) | + ACR_SUPERVISOR_PROTECT(0) | + ACR_CACHE_MODE(CACHE_WRITETHROUGH) | + ACR_ADDRESS_MASK_MODE(1) | + ACR_S(ACR_S_SUPERVISOR_MODE) | + ACR_E(1) | + ACR_ADMSK(0x0c) | + ACR_BA(0x0)); - set_acr3(ACR_WRITE_PROTECT(0) | - ACR_SUPERVISOR_PROTECT(0) | - ACR_CACHE_MODE(CACHE_WRITETHROUGH) | - ACR_ADDRESS_MASK_MODE(0) | - ACR_S(ACR_S_SUPERVISOR_MODE) | - ACR_E(1) | - ACR_ADMSK(0x1f) | - ACR_BA(0x0f)); + set_acr3(ACR_WRITE_PROTECT(0) | + ACR_SUPERVISOR_PROTECT(0) | + ACR_CACHE_MODE(CACHE_WRITETHROUGH) | + ACR_ADDRESS_MASK_MODE(0) | + ACR_S(ACR_S_SUPERVISOR_MODE) | + ACR_E(1) | + ACR_ADMSK(0x1f) | + ACR_BA(0x0f)); - set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */ + set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */ - /* clear all MMU TLB entries */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA; + /* clear all MMU TLB entries */ + MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA; - /* map locked TLB entries */ - for (i = 0; i < num_locked_mmu_maps; i++) - { - mmu_map_page(locked_map[i].virt, locked_map[i].phys, locked_map->pagesize, locked_map->flags); + /* map locked TLB entries */ + for (i = 0; i < num_locked_mmu_maps; i++) + { + mmu_map_page(locked_map[i].virt, locked_map[i].phys, locked_map->pagesize, locked_map->flags); - if (locked_map[i].flags.page_id == SCA_PAGE_ID) - { - video_tlb = 0x2000; - video_sbt = 0x0; - } - } + if (locked_map[i].flags.page_id == SCA_PAGE_ID) + { + video_tlb = 0x2000; + video_sbt = 0x0; + } + } } /* @@ -412,101 +412,105 @@ void mmu_init(void) */ bool access_exception(uint32_t pc, uint32_t format_status) { - int fault_status; - uint32_t fault_address; - uint32_t mmu_status; + int fault_status; + uint32_t fault_address; + uint32_t mmu_status; - /* - * extract fault status from format_status exception stack field - */ - fault_status = format_status & 0xc030000; - mmu_status = MCF_MMU_MMUSR; + /* + * extract fault status from format_status exception stack field + */ + fault_status = format_status & 0xc030000; + mmu_status = MCF_MMU_MMUSR; - /* - * determine if access fault was caused by a TLB miss - */ - switch (fault_status) - { - case 0x4010000: /* TLB miss on opword of instruction fetch */ - case 0x4020000: /* TLB miss on extension word of instruction fetch */ - fault_address = pc; - break; - case 0x8020000: /* TLB miss on data write */ - case 0xc020000: /* TLB miss on data read or read-modify-write */ - fault_address = MCF_MMU_MMUAR; - dbg("access fault - TLB miss at %p. Fault status = 0x0%x\r\n", pc, fault_status); - break; + /* + * determine if access fault was caused by a TLB miss + */ + switch (fault_status) + { + case 0x4010000: /* TLB miss on opword of instruction fetch */ + case 0x4020000: /* TLB miss on extension word of instruction fetch */ + fault_address = pc; + break; + case 0x8020000: /* TLB miss on data write */ + case 0xc020000: /* TLB miss on data read or read-modify-write */ + fault_address = MCF_MMU_MMUAR; + /* + * the following line must stay commented or we risk a double fault (debugging + * output requiring itself a page mapping): + */ + // dbg("access fault - TLB miss at %p. Fault status = 0x0%x\r\n", pc, fault_status); + break; - default: - return false; - } + default: + return false; + } - if (mmu_status & MCF_MMU_MMUSR_HIT) /* did the last fault hit in TLB? */ - { - /* - * if yes, then we already mapped that page during a previous turn and this is in fact a bus error - */ - return false; - } - else - { - struct mmu_mapping *map; + if (mmu_status & MCF_MMU_MMUSR_HIT) /* did the last fault hit in TLB? */ + { + /* + * if yes, then we already mapped that page during a previous turn and this is in fact a bus error + */ + return false; + } + else + { + struct mmu_mapping *map; - if ((map = lookup_mapping(fault_address)) != NULL) - { - uint32_t mask; + if ((map = lookup_mapping(fault_address)) != NULL) + { + uint32_t mask; - switch (map->pagesize) - { - case MMU_PAGE_SIZE_1M: - mask = ~(0x100000 - 1); - break; - case MMU_PAGE_SIZE_4K: - mask = ~(0x1000 - 1); - break; - case MMU_PAGE_SIZE_8K: - mask = ~(0x2000 - 1); - break; - case MMU_PAGE_SIZE_1K: - mask = ~(0x400 - 1); - break; - } + switch (map->pagesize) + { + case MMU_PAGE_SIZE_1M: + mask = ~(0x100000 - 1); + break; + case MMU_PAGE_SIZE_4K: + mask = ~(0x1000 - 1); + break; + case MMU_PAGE_SIZE_8K: + mask = ~(0x2000 - 1); + break; + case MMU_PAGE_SIZE_1K: + mask = ~(0x400 - 1); + break; + } - mmu_map_page(fault_address & mask, fault_address & mask, map->pagesize, map->flags); - return true; - } - } - return false; + mmu_map_page(fault_address & mask, fault_address & mask, map->pagesize, map->flags); + return true; + } + } + return false; } void mmu_map_page(uint32_t virt, uint32_t phys, uint32_t map_size, struct map_flags flags) { - /* - * add page to TLB - */ - MCF_MMU_MMUTR = virt | /* virtual address */ - MCF_MMU_MMUTR_ID(flags.page_id) | - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ + /* + * add page to TLB + */ + MCF_MMU_MMUTR = virt | /* virtual address */ + MCF_MMU_MMUTR_ID(flags.page_id) | + MCF_MMU_MMUTR_SG | /* shared global */ + MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUDR = phys | /* physical address */ - MCF_MMU_MMUDR_SZ(map_size) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(flags.cache_mode) | - (flags.access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) | /* read access enable */ - (flags.access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) | /* write access enable */ - (flags.access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0); /* execute access enable */ + MCF_MMU_MMUDR = phys | /* physical address */ + MCF_MMU_MMUDR_SZ(map_size) | /* 1 MB page size */ + MCF_MMU_MMUDR_CM(flags.cache_mode) | + (flags.access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) | /* read access enable */ + (flags.access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) | /* write access enable */ + (flags.access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0); /* execute access enable */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - dbg("mapped virt=%p to phys=%p\r\n", virt, phys); + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ + MCF_MMU_MMUOR_ACC | /* access TLB */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + dbg("mapped virt=%p to phys=%p\r\n", virt, phys); } diff --git a/sys/sysinit.c b/sys/sysinit.c index 1c90567..2e2bbc9 100644 --- a/sys/sysinit.c +++ b/sys/sysinit.c @@ -2,7 +2,7 @@ * File: sysinit.c * Purpose: Power-on Reset configuration of the Firebee board. * - * Notes: + * Notes: * * This file is part of BaS_gcc. * @@ -60,7 +60,7 @@ extern volatile long _VRAM; /* start address of video ram from linker script */ /* - * init SLICE TIMER 0 + * init SLICE TIMER 0 * all = 32.538 sec = 30.736mHz * BYT0 = 127.1ms/tick = 7.876Hz offset 0 * BYT1 = 496.5us/tick = 2.014kHz offset 1 @@ -89,10 +89,10 @@ void init_gpio(void) * configure all four 547x GPIO module DMA pins: * * /DACK1 - DMA acknowledge 1 - * /DACK0 - DMA acknowledge 0 - * /DREQ1 - DMA request 1 - * /DREQ0 - DMA request 0 - * + * /DACK0 - DMA acknowledge 0 + * /DREQ1 - DMA request 1 + * /DREQ0 - DMA request 0 + * * for DMA operation */ MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0(0x3) | @@ -430,27 +430,27 @@ void init_fbcs() #if MACHINE_FIREBEE /* FBC setup for FireBee */ MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */ MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */ - | MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */ - | MCF_FBCS_CSCR_AA; /* AA */ + | MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */ + | MCF_FBCS_CSCR_AA; /* AA */ MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V; MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT - | MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS - | MCF_FBCS_CSCR_AA; // AA + | MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS + | MCF_FBCS_CSCR_AA; // AA MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF | MCF_FBCS_CSMR_V); MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT - | MCF_FBCS_CSCR_AA; // AA + | MCF_FBCS_CSCR_AA; // AA MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF | MCF_FBCS_CSMR_V); MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÜTZT, DECODE DIREKT AUF DEM FPGA MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT - | MCF_FBCS_CSCR_BSTR // BURST READ ENABLE - | MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE + | MCF_FBCS_CSCR_BSTR // BURST READ ENABLE + | MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF | MCF_FBCS_CSMR_V; #elif MACHINE_M5484LITE @@ -465,7 +465,7 @@ void init_fbcs() | MCF_FBCS_CSCR_WS(32) | MCF_FBCS_CSCR_ASET(1) | MCF_FBCS_CSCR_AA; - MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M + MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M | MCF_FBCS_CSMR_V; #endif /* MACHINE_FIREBEE */ @@ -583,7 +583,7 @@ void init_video_ddr(void) { /* * probe for NEC compatible USB host controller and install if found */ -void init_usb(void) +void init_usb(void) { extern struct pci_device_id ohci_usb_pci_table[]; extern struct pci_device_id ehci_usb_pci_table[]; @@ -673,7 +673,7 @@ void dvi_on(void) { uint8_t receivedByte; uint8_t dummyByte; /* only used for a dummy read */ int num_tries = 0; - + xprintf("DVI digital video output initialization: "); MCF_I2C_I2FDR = 0x3c; /* divide system clock by 1280: 100kHz standard */ @@ -817,16 +817,16 @@ void init_ac97(void) { int va; int vb; int vc; - + xprintf("AC97 sound chip initialization: "); MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97 - | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK + | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK | MCF_PAD_PAR_PSC2_PAR_TXD2 | MCF_PAD_PAR_PSC2_PAR_RXD2; MCF_PSC2_PSCMR1 = 0x0; MCF_PSC2_PSCMR2 = 0x0; MCF_PSC2_PSCIMR = 0x0300; - MCF_PSC2_PSCSICR = 0x03; //AC97 + MCF_PSC2_PSCSICR = 0x03; //AC97 MCF_PSC2_PSCRFCR = 0x0f000000; MCF_PSC2_PSCTFCR = 0x0f000000; MCF_PSC2_PSCRFAR = 0x00F0; @@ -847,7 +847,7 @@ void init_ac97(void) { { MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 } - + // read register MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume @@ -857,7 +857,7 @@ void init_ac97(void) { MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0 } wait(50); - + va = MCF_PSC2_PSCTB_AC97; if ((va & 0x80000fff) == 0x80000800) { vb = MCF_PSC2_PSCTB_AC97; @@ -961,10 +961,10 @@ void initialize_hardware(void) * (volatile uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ * (volatile uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ - /* TT-RAM */ + /* TT-RAM */ - * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ - * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ + * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ /* Jump into FireTOS */ typedef void void_func(void); @@ -977,7 +977,7 @@ void initialize_hardware(void) init_serial(); xprintf("\n\n"); - xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n", + xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n", #if MACHINE_FIREBEE "Firebee" #elif MACHINE_M5484LITE @@ -1093,6 +1093,7 @@ void initialize_hardware(void) /* the following only makes sense _after_ DDRAM has been initialized */ clear_bss_segment(); + xprintf(".bss segment cleared\r\n"); if (BAS_LMA != BAS_IN_RAM) { @@ -1112,7 +1113,7 @@ void initialize_hardware(void) init_video_ddr(); dvi_on(); -#ifdef _NOT_USED_ +#ifdef _NOT_USED_ /* experimental */ { int i; @@ -1138,7 +1139,7 @@ void initialize_hardware(void) driver_mem_init(); init_pci(); video_init(); - + /* do not try to init USB for now on the Firebee, it hangs the machine */ #ifndef MACHINE_FIREBEE //init_usb();