new function enable_pci_interrupts() (defer PCI interrupt activation
until after PCI scan)
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@@ -232,26 +232,32 @@ void enable_coldfire_interrupts()
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MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */
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MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
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MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */
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MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
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MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
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MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
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//MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
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MCF_INTC_IMRH = 0;
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FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
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FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
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FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
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FBEE_INTR_INT_VSYNC_IRQ4 //| /* enable vsync interrupts */
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//FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
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//FBEE_INTR_PCI_INTB |
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//FBEE_INTR_PCI_INTC |
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//FBEE_INTR_PCI_INTD;
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;
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MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
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#endif
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xprintf("finished\r\n");
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}
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void enable_pci_interrupts()
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{
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dbg("enable PCI interrupts\r\n");
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MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
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MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
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MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
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MCF_INTC_IMRH = 0;
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#if defined(MACHINE_FIREBEE)
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FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
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FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
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FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
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FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */
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FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
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FBEE_INTR_PCI_INTB |
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FBEE_INTR_PCI_INTC |
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FBEE_INTR_PCI_INTD;
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;
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#endif
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}
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void disable_coldfire_interrupts()
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{
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#if defined(MACHINE_FIREBEE)
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@@ -465,10 +471,11 @@ void BaS(void)
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fec_irq_enable(0, 5, 1);
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init_pci();
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enable_pci_interrupts();
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video_init();
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/* initialize USB devices */
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//init_usb();
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init_usb();
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set_ipl(7); /* disable interrupts */
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