activated more Coldfire interrupt sources

include/interrupts.h

@@ -144,5 +144,6 @@ extern bool isr_execute_handler(int vector);
 extern bool pic_interrupt_handler(void *arg1, void *arg2);
 extern bool xlbpci_interrupt_handler(void *arg1, void *arg2);
 extern bool pciarb_interrupt_handler(void *arg1, void *arg2);
+extern bool gpt0_interrupt_handler(void *arg1, void *arg2);
 extern bool irq5_handler(void *arg1, void *arg2);
 #endif /* _INTERRUPTS_H_ */

sys/BaS.c

@@ -259,7 +259,6 @@ void disable_coldfire_interrupts()
 #endif /* MACHINE_FIREBEE */
 
     MCF_EPORT_EPIER = 0x0;
-    MCF_EPORT_EPFR = 0x0;
     MCF_INTC_IMRL = 0xfffffffe;
     MCF_INTC_IMRH = 0xffffffff;
 }
@@ -281,7 +280,7 @@ void init_isr(void)
     /*
      * register the FEC interrupt handler
      */
-    if (!isr_register_handler(64 + INT_SOURCE_FEC0, 7, 6, fec0_interrupt_handler, NULL, (void *) &nif1))
+    if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1))
     {
         err("unable to register isr for FEC0\r\n");
     }
@@ -290,32 +289,37 @@ void init_isr(void)
      * Register the DMA interrupt handler
      */
 
-    if (!isr_register_handler(64 + INT_SOURCE_DMA, 7, 7, dma_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL))
     {
-        err("Error: Unable to register isr for DMA\r\n");
+        err("unable to register isr for DMA\r\n");
+    }
+
+#ifdef MACHINE_FIREBEE
+    /*
+     * register GPT0 timer interrupt vector
+     */
+    if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL))
+    {
+        err("unable to register isr for GPT0 timer\r\n");
     }
 
-#ifdef _NOT_USED_
     /*
      * register the PIC interrupt handler
      */
-    if (!isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL))
     {
         err("Error: unable to register ISR for PSC3\r\n");
     }
+#endif /* MACHINE_FIREBEE */
 
     /*
      * register the XLB PCI interrupt handler
      */
-    if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, xlbpci_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 7, 0, xlbpci_interrupt_handler, NULL, NULL))
     {
         err("Error: unable to register isr for XLB PCI interrupts\r\n");
     }
 
-    MCF_INTC_ICR43 = MCF_INTC_ICR_IL(7) |           /* level 7, priority 6 */
-                     MCF_INTC_ICR_IP(6);
-    MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK43;     /* enable XLB PCI interrupts in DMA controller */
-
     MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE |      /* slave error acknowledge interrupt */
             MCF_XLB_XARB_IMR_MME |                  /* multiple master at prio 0 interrupt */
             MCF_XLB_XARB_IMR_TTAE |                 /* TT address only interrupt */
@@ -324,19 +328,14 @@ void init_isr(void)
             MCF_XLB_XARB_IMR_TTME |                 /* TBST/TSIZ mismatch interrupt */
             MCF_XLB_XARB_IMR_BAE;                   /* bus activity tenure timeout interrupt */
 
-    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, pciarb_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
     {
         err("Error: unable to register isr for PCIARB interrupts\r\n");
 
         return;
     }
-    MCF_INTC_ICR41 = MCF_INTC_ICR_IL(7) |           /* level 5, priority 0 */
-                     MCF_INTC_ICR_IP(5);
-    MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK41;     /* enable PCIARB interrupts in DMA controller */
-
     MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
                       MCF_PCIARB_PACR_INTMINTEN;        /* internal master broken interrupt */
-#endif /* _NOT_USED_ */
 }
 
 void BaS(void)

sys/exceptions.S

@@ -214,13 +214,6 @@ init_vec_loop:
                 move.l  a1,0x11c(a0)
 
 
-#ifdef MACHINE_FIREBEE
-
-// timer vectors (triggers when vbashi gets changed, used for video page copy)
-                lea     handler_gpt0(pc),a1
-                // GPT0 interrupt source = 62
-                move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
-#endif /* MACHINE_FIREBEE */
 
 // install lowlevel_isr_handler for the three GPT timers
                 lea     _lowlevel_isr_handler(pc),a1
@@ -245,6 +238,12 @@ init_vec_loop:
                 move.l  a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
 #endif
 
+#ifdef MACHINE_FIREBEE
+
+// timer vectors (triggers when vbashi gets changed, used for video page copy)
+                move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
+#endif /* MACHINE_FIREBEE */
+
                 move.l  (sp)+,a2            // Restore registers
                 rts
 
@@ -489,38 +488,6 @@ irq7:
                 move.l  (sp)+,a0
                 rts                                 // Forward to the Access Error handler
 
-
-/*
- * general purpose timer 0 (GPT0): video change, later also others.
- *
- * GPT0 is used as input trigger. It is connected to the TIN0 signal of
- * the FPGA and triggers everytime vbasehi is written to, i.e.
- * when the video base address gets changed
- */
-
-/*
- * TODO: remove. This interrupt still fires, but doesn't do anything anymore.
- * BaS_gcc handles FPGA RAM as STRAM, so there is no page copy necessary as
- * it was with previous versions.
- */
-handler_gpt0:
-                .extern _gpt0_interrupt_handler
-
-                //move.w  #0x2700,sr                  // disable interrupts
-                link    a6,#-4 * 4                  // make room for
-                movem.l d0-d1/a0-a1,(sp)            // gcc scratch registers and save them,
-                                                    // other registers will be handled by gcc itself
-
-                move.w  4(a6),d0                    // fetch vector number from stack
-                move.l  d0,-(sp)                    // push it
-                jsr     _gpt0_interrupt_handler     // call C handler
-                addq.l  #4,sp                       // adjust stack
-
-                movem.l (sp),d0-d1/a0-a1            // restore registers
-
-                unlk    a6
-                rte
-
 #else                                               // handlers for M5484LITE
 
 irq5:                                               // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE

sys/interrupts.c

@@ -76,6 +76,8 @@ bool isr_set_prio_and_level(int int_source, int priority, int level)
         /*
         * preset interrupt control registers with level and priority
         */
+        dbg("set MCF_INTC_ICR(%d) to priority %d, level %d\r\n",
+            int_source, priority, level);
         MCF_INTC_ICR(int_source) = MCF_INTC_ICR_IP(priority) |
                                    MCF_INTC_ICR_IL(level);
     }
@@ -97,6 +99,14 @@ bool isr_set_prio_and_level(int int_source, int priority, int level)
  */
 bool isr_enable_int_source(int int_source)
 {
+    dbg("anding int_source %d, MCF_INTC_IMR%c = 0x%08x, now 0x%08x\r\n",
+        int_source,
+        int_source < 32 && int_source > 0 ? 'L' :
+                    int_source >= 32 && int_source <= 62 ? 'H' : 'U',
+        int_source < 32 && int_source > 0 ? ~(1 << int_source) :
+                    int_source >= 32 && int_source <= 62 ? ~(1 << (int_source - 32)) : 0,
+        MCF_INTC_IMRH);
+
     if (int_source < 32 && int_source > 0)
     {
         MCF_INTC_IMRL &= ~(1 << int_source);
@@ -439,7 +449,7 @@ bool irq7_handler(void)
  * video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
  * RAM page.
  */
-bool gpt0_interrupt_handler(void)
+bool gpt0_interrupt_handler(void *arg0, void *arg1)
 {
     dbg("handler called\n\r");