From f6984e68b1bdc07edd4b8203dba3f3c136259678 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Sun, 22 Dec 2013 16:08:18 +0000
Subject: [PATCH] added a 1 Meg page as very last RAM page to handle uncached
 memory for drivers. This moved the BaS RAM area to the second last page of
 memory

---
 BaS_gcc/bas.lk.in         | 17 +++++++++--------
 BaS_gcc/include/firebee.h |  2 +-
 BaS_gcc/include/m5484l.h  |  2 +-
 BaS_gcc/sys/mmu.c         | 28 +++++++++++++++++++++++++---
 4 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/BaS_gcc/bas.lk.in b/BaS_gcc/bas.lk.in
index 9488fdd..50e778e 100644
--- a/BaS_gcc/bas.lk.in
+++ b/BaS_gcc/bas.lk.in
@@ -19,7 +19,8 @@ MEMORY
    /*
 	* target to copy BaS data segment to. 1M should be enough for now
 	*/
-   bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
+   bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
+   driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
 }
 
 SECTIONS
@@ -78,15 +79,11 @@ SECTIONS
 		*(.bss)	
 		__BAS_BSS_END = .;
 #endif /* COMPILE_RAM */
+
 #if (FORMAT == elf32-m68k)
 		*(.rodata)
 		*(.rodata.*)
 #endif
-#ifdef COMPILE_RAM
-		. = ALIGN(16);
-		_driver_mem_buffer = .;
-		// . = . + DRIVER_MEM_BUFFER_SIZE
-#endif /* COMPILE_RAM */
 	} > bas_rom
 
 #if (TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS)
@@ -108,11 +105,15 @@ SECTIONS
 		__BAS_BSS_END = .;
 
 		. = ALIGN(16);
-		_driver_mem_buffer = .;
-		//. = . + DRIVER_MEM_BUFFER_SIZE;
 	} > bas_ram
 #endif
 
+	.driver_memory :
+	{
+		_driver_mem_buffer = .;
+		//. = . + DRIVER_MEM_BUFFER_SIZE;
+	} > driver_ram
+	
 	/*
 	 * Global memory map
 	 */
diff --git a/BaS_gcc/include/firebee.h b/BaS_gcc/include/firebee.h
index 2077d9d..5054766 100644
--- a/BaS_gcc/include/firebee.h
+++ b/BaS_gcc/include/firebee.h
@@ -37,7 +37,7 @@
 #define SDRAM_SIZE					0x20000000	/* 512 MB on the Firebee */
 
 #ifdef COMPILE_RAM
-#define TARGET_ADDRESS  	(SDRAM_START + SDRAM_SIZE - 0x100000)
+#define TARGET_ADDRESS  	(SDRAM_START + SDRAM_SIZE - 0x200000)
 #else
 #define TARGET_ADDRESS  	BOOTFLASH_BASE_ADDRESS
 
diff --git a/BaS_gcc/include/m5484l.h b/BaS_gcc/include/m5484l.h
index 250bc6a..1292a5a 100644
--- a/BaS_gcc/include/m5484l.h
+++ b/BaS_gcc/include/m5484l.h
@@ -37,7 +37,7 @@
 #define SDRAM_SIZE					0x4000000  	/* 64 MB on the LITEKIT */
 
 #ifdef COMPILE_RAM
-#define TARGET_ADDRESS	(SDRAM_START + SDRAM_SIZE - 0x100000)
+#define TARGET_ADDRESS	(SDRAM_START + SDRAM_SIZE - 0x200000)
 #else
 #define TARGET_ADDRESS	BOOTFLASH_BASE_ADDRESS
 #endif /* COMPILE_RAM */
diff --git a/BaS_gcc/sys/mmu.c b/BaS_gcc/sys/mmu.c
index 077c58f..4613360 100644
--- a/BaS_gcc/sys/mmu.c
+++ b/BaS_gcc/sys/mmu.c
@@ -313,7 +313,7 @@ void __attribute__((flatten)) mmu_init(void)
 					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
 					MCF_MMU_MMUDR_CM(0x1) |	/* cachable copyback */
 					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable (FIXME: for now) */
+					//MCF_MMU_MMUDR_W |		/* write access enable (FIXME: for now) */
 					MCF_MMU_MMUDR_X |		/* execute access enable */
 					MCF_MMU_MMUDR_LK;		/* lock entry */
 	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
@@ -347,16 +347,38 @@ void __attribute__((flatten)) mmu_init(void)
 #endif /* MACHINE_FIREBEE */
 
 	/*
-	 * Map (locked) the last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
+	 * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
 	 * virtual address. This is also used when BaS is in RAM
 	 */
 
+	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* virtual address */
+					MCF_MMU_MMUTR_SG |		/* shared global */
+					MCF_MMU_MMUTR_V;		/* valid */
+	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* physical address */
+					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+					MCF_MMU_MMUDR_CM(0x0) |	/* cacheable writethrough */
+					MCF_MMU_MMUDR_SP |		/* supervisor protect */
+					MCF_MMU_MMUDR_R |		/* read access enable */
+					MCF_MMU_MMUDR_W |		/* write access enable */
+					MCF_MMU_MMUDR_X |		/* execute access enable */
+					MCF_MMU_MMUDR_LK;		/* lock entry */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+					MCF_MMU_MMUOR_ACC |     /* access TLB */
+					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+					
+	/*
+	 * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
+	 * virtual address. Used uncached for drivers.
+	 */
+
 	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* virtual address */
 					MCF_MMU_MMUTR_SG |		/* shared global */
 					MCF_MMU_MMUTR_V;		/* valid */
 	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* physical address */
 					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x0) |	/* cacheable writethrough */
+					MCF_MMU_MMUDR_CM(0x2) |	/* nocache precise */
 					MCF_MMU_MMUDR_SP |		/* supervisor protect */
 					MCF_MMU_MMUDR_R |		/* read access enable */
 					MCF_MMU_MMUDR_W |		/* write access enable */