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memory to memory DMA test

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display BaS version and compile date/time
This commit is contained in:
Markus Fröschle
2013-07-31 20:57:55 +00:00
parent aa4be4dfa8
commit f67b0e4d17
3 changed files with 56 additions and 21 deletions
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34
BaS_gcc/run_bas.bdm
View File

@@ -16,29 +16,30 @@ write-ctrl 0x0C0F 0xFF000000
write-ctrl 0x0C04 0xFF100007 write-ctrl 0x0C04 0xFF100007
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently) # Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
#write-ctrl 0x0C05 0xFF101001 write-ctrl 0x0C05 0xFF101001
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
#write 0xFF000500 0xE0000000 4 write 0xFF000500 0xE0000000 4
#write 0xFF000508 0x00041180 4 write 0xFF000508 0x00041180 4
#write 0xFF000504 0x007F0001 4 write 0xFF000504 0x007F0001 4
wait
# Init CS1 (Atari I/O address range) # Init CS1 (Atari I/O address range)
#write 0xFF00050C 0xFFF00000 4 write 0xFF00050C 0xFFF00000 4
#write 0xFF000514 0x00002180 4 write 0xFF000514 0x00002180 4
#write 0xFF000510 0x000F0001 4 write 0xFF000510 0x000F0001 4
# Init CS2 (FireBee 32 bit I/O address range) # Init CS2 (FireBee 32 bit I/O address range)
#write 0xFF000518 0xF0000000 4 write 0xFF000518 0xF0000000 4
#write 0xFF000520 0x00002100 4 write 0xFF000520 0x00002100 4
#write 0xFF00051C 0x07FF0001 4 write 0xFF00051C 0x07FF0001 4
# Init CS3 (FireBee 16 bit I/O address range) # Init CS3 (FireBee 16 bit I/O address range)
#write 0xFF000524 0xF8000000 4 write 0xFF000524 0xF8000000 4
#write 0xFF00052C 0x00000180 4 write 0xFF00052C 0x00000180 4
#write 0xFF000528 0x03FF0001 4 write 0xFF000528 0x03FF0001 4
# Init CS4 (FireBee video address range) # Init CS4 (FireBee video address range)
#write 0xFF000530 0x40000000 4 write 0xFF000530 0x40000000 4
#write 0xFF000538 0x00000018 4 write 0xFF000538 0x00000018 4
#write 0xFF000534 0x003F0001 4 write 0xFF000534 0x003F0001 4
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
@@ -53,6 +54,7 @@ write 0xFF00010C 0x46770000 4 # SDCFG2
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)

34
BaS_gcc/sources/spidma.c
View File

@@ -19,7 +19,9 @@ void *dma_memcpy(void *dst, void *src, size_t n)
int32_t start = MCF_SLT_SCNT(0); int32_t start = MCF_SLT_SCNT(0);
int32_t end; int32_t end;
ret = MCD_startDma(0, src, 1, dst, 1, n, 1, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0); xprintf("doing memory to memory DMA from %p to %p (%x bytes)\r\n", src, dst, n);
ret = MCD_startDma(0, src, n, dst, n, n, 1, DMA_ALWAYS, 7, MCD_SINGLE_DMA|MCD_TT_FLAGS_CW|MCD_TT_FLAGS_RL|MCD_TT_FLAGS_SP, 0);
if (ret == MCD_OK) if (ret == MCD_OK)
{ {
xprintf("DMA on channel 0 successfully started\r\n"); xprintf("DMA on channel 0 successfully started\r\n");
@@ -28,7 +30,33 @@ void *dma_memcpy(void *dst, void *src, size_t n)
do do
{ {
ret = MCD_dmaStatus(0); ret = MCD_dmaStatus(0);
xprintf("."); switch (ret)
{
case MCD_NO_DMA:
xprintf("MCD_NO_DMA: no DMA active on this channel\r\n");
break;
case MCD_IDLE:
xprintf("MCD_IDLE: DMA defined but not active (initiator not ready)\r\n");
break;
case MCD_RUNNING:
//xprintf("MCD_RUNNING: DMA active and working on this channel\r\n");
break;
case MCD_PAUSED:
xprintf("MCD_PAUSED: DMA defined and enabled, but currently paused\r\n");
break;
case MCD_HALTED:
xprintf("MCD_HALTED: DMA killed\r\n");
break;
case MCD_DONE:
xprintf("MCD_DONE: DMA finished\r\n");
break;
case MCD_CHANNEL_INVALID:
xprintf("MCD_CHANNEL_INVALID: invalid DMA channel\r\n");
break;
default:
xprintf("unknown DMA status %d\r\n", ret);
break;
}
} while (ret != MCD_DONE); } while (ret != MCD_DONE);
xprintf("\r\n"); xprintf("\r\n");
@@ -57,7 +85,7 @@ int spidma_init(void)
xprintf("DMA API initialized. Tasks are at %p\r\n", SYS_SRAM); xprintf("DMA API initialized. Tasks are at %p\r\n", SYS_SRAM);
// test // test
dma_memcpy((void *) 0x40000000, (void *) 0x30000000, 0x100000); dma_memcpy((void *) 0x1e000000, (void *) 0x1f000000, 0xf00000);
xprintf("DMA finished\r\n"); xprintf("DMA finished\r\n");
return 1; return 1;
} }

9
BaS_gcc/sources/sysinit.c
View File

@@ -34,6 +34,9 @@
#include "bas_types.h" #include "bas_types.h"
#include "wait.h" #include "wait.h"
#define MAJOR_VERSION 0
#define MINOR_VERSION 7
#define UNUSED(x) (void)(x) /* Unused variable */ #define UNUSED(x) (void)(x) /* Unused variable */
extern volatile long _VRAM; /* start address of video ram from linker script */ extern volatile long _VRAM; /* start address of video ram from linker script */
@@ -321,13 +324,14 @@ void init_fbcs()
xprintf("FlexBus chip select registers initialization: "); xprintf("FlexBus chip select registers initialization: ");
/* Flash */ /* Flash */
MCF_FBCS0_CSAR = 0xE0000000; /* flash base address */ MCF_FBCS0_CSAR = 0xE0000000; /* flash base address */
MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 | MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 |
MCF_FBCS_CSCR_WS(4)| MCF_FBCS_CSCR_WS(6)|
MCF_FBCS_CSCR_AA; MCF_FBCS_CSCR_AA;
MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM_8M | MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM_8M |
MCF_FBCS_CSMR_V; /* 8 MByte on */ MCF_FBCS_CSMR_V; /* 8 MByte on */
MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */ MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */
MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */ MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
| MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */ | MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */
@@ -844,6 +848,7 @@ void initialize_hardware(void) {
* Determine cause(s) of Reset * Determine cause(s) of Reset
*/ */
xprintf("\n\n"); xprintf("\n\n");
xprintf("Firebee BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n", MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__);
if (MCF_SIU_RSR & MCF_SIU_RSR_RST) if (MCF_SIU_RSR & MCF_SIU_RSR_RST)
xprintf("Reset. Cause: External Reset\r\n"); xprintf("Reset. Cause: External Reset\r\n");
if (MCF_SIU_RSR & MCF_SIU_RSR_RSTWD) if (MCF_SIU_RSR & MCF_SIU_RSR_RSTWD)