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found a line been lost in dvi_on()

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This commit is contained in:
Markus Fröschle
2012-10-18 14:00:47 +00:00
parent f7e74c3a30
commit ec510c63b0
1 changed files with 19 additions and 2 deletions
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21
sources/sysinit.c
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@@ -244,9 +244,9 @@ void init_fbcs()
void wait_pll(void) void wait_pll(void)
{ {
register uint32_t trgt = MCF_SLT0_SCNT - 100000;
do { do {
wait_1ms(); } while ((* (volatile uint16_t *) 0xf0000800 > 0) && MCF_SLT0_SCNT > trgt);
} while (! * (volatile uint16_t *) 0xf0000800);
} }
static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
@@ -255,30 +255,44 @@ void init_pll(void)
{ {
uart_out_word('PLL '); uart_out_word('PLL ');
wait_pll();
* (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */ * (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */
wait_pll(); wait_pll();
* (volatile uint8_t *) 0xf0000800 = 0; /* set */ * (volatile uint8_t *) 0xf0000800 = 0; /* set */
uart_out_word('SET!'); uart_out_word('SET!');
@@ -491,6 +505,9 @@ loop_i2c:
MCF_I2C_I2SR &= 0xfd; MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;;
MCF_I2C_I2CR = 0x80; // stop MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2SR = 0x0; // clear sr MCF_I2C_I2SR = 0x0; // clear sr