diff --git a/usb/store/asm-m68k/byteorder.h b/usb/store/asm-m68k/byteorder.h
new file mode 100644
index 0000000..3d4f13c
--- /dev/null
+++ b/usb/store/asm-m68k/byteorder.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M68K_BYTEORDER_H
+#define _M68K_BYTEORDER_H
+
+#include "types.h"
+
+#ifdef __GNUC__
+#define __sw16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define __sw32(x) \
+	((__u32)( \
+		(((__u32)(x)) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x)) >> 24) ))
+
+extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+	unsigned result = *addr;
+	return __sw16(result);
+}
+
+extern __inline__ void st_le16(volatile unsigned short *addr,
+			       const unsigned val)
+{
+	*addr = __sw16(val);
+}
+
+extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+	unsigned result = *addr;
+	return __sw32(result);
+}
+
+extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+	*addr = __sw32(val);
+}
+
+#if 0
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+   inline asm correctly, and can cause file corruption. Until I hear that
+   it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+#  define __arch_swab16(x) ld_le16(&x)
+#  define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__ ((const))
+__u16 ___arch__swab16(__u16 value)
+{
+	return __sw16(value);
+}
+
+static __inline__ __attribute__ ((const))
+__u32 ___arch__swab32(__u32 value)
+{
+	return __sw32(value);
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif				/* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+#endif
+
+#endif				/* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
+#include "byteorder/big_endian.h"
+
+#endif				/* _M68K_BYTEORDER_H */
diff --git a/usb/store/asm-m68k/byteorder/big_endian.h b/usb/store/asm-m68k/byteorder/big_endian.h
new file mode 100644
index 0000000..fbdea2c
--- /dev/null
+++ b/usb/store/asm-m68k/byteorder/big_endian.h
@@ -0,0 +1,69 @@
+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
+
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN 4321
+#endif
+#ifndef __BIG_ENDIAN_BITFIELD
+#define __BIG_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__BIG_ENDIAN
+
+#include "swab.h"
+
+#define __constant_htonl(x) ((__u32)(x))
+#define __constant_ntohl(x) ((__u32)(x))
+#define __constant_htons(x) ((__u16)(x))
+#define __constant_ntohs(x) ((__u16)(x))
+#define __constant_cpu_to_le64(x) ___swab64((x))
+#define __constant_le64_to_cpu(x) ___swab64((x))
+#define __constant_cpu_to_le32(x) ___swab32((x))
+#define __constant_le32_to_cpu(x) ___swab32((x))
+#define __constant_cpu_to_le16(x) ___swab16((x))
+#define __constant_le16_to_cpu(x) ___swab16((x))
+#define __constant_cpu_to_be64(x) ((__u64)(x))
+#define __constant_be64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_be32(x) ((__u32)(x))
+#define __constant_be32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_be16(x) ((__u16)(x))
+#define __constant_be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64(x) __swab64((x))
+#define __le64_to_cpu(x) __swab64((x))
+#define __cpu_to_le32(x) __swab32((x))
+#define __le32_to_cpu(x) __swab32((x))
+#define __cpu_to_le16(x) __swab16((x))
+#define __le16_to_cpu(x) __swab16((x))
+#define __cpu_to_be64(x) ((__u64)(x))
+#define __be64_to_cpu(x) ((__u64)(x))
+#define __cpu_to_be32(x) ((__u32)(x))
+#define __be32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_be16(x) ((__u16)(x))
+#define __be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64p(x) __swab64p((x))
+#define __le64_to_cpup(x) __swab64p((x))
+#define __cpu_to_le32p(x) __swab32p((x))
+#define __le32_to_cpup(x) __swab32p((x))
+#define __cpu_to_le16p(x) __swab16p((x))
+#define __le16_to_cpup(x) __swab16p((x))
+#define __cpu_to_be64p(x) (*(__u64*)(x))
+#define __be64_to_cpup(x) (*(__u64*)(x))
+#define __cpu_to_be32p(x) (*(__u32*)(x))
+#define __be32_to_cpup(x) (*(__u32*)(x))
+#define __cpu_to_be16p(x) (*(__u16*)(x))
+#define __be16_to_cpup(x) (*(__u16*)(x))
+#define __cpu_to_le64s(x) __swab64s((x))
+#define __le64_to_cpus(x) __swab64s((x))
+#define __cpu_to_le32s(x) __swab32s((x))
+#define __le32_to_cpus(x) __swab32s((x))
+#define __cpu_to_le16s(x) __swab16s((x))
+#define __le16_to_cpus(x) __swab16s((x))
+#define __cpu_to_be64s(x) do {} while (0)
+#define __be64_to_cpus(x) do {} while (0)
+#define __cpu_to_be32s(x) do {} while (0)
+#define __be32_to_cpus(x) do {} while (0)
+#define __cpu_to_be16s(x) do {} while (0)
+#define __be16_to_cpus(x) do {} while (0)
+
+#include "generic.h"
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
diff --git a/usb/store/asm-m68k/byteorder/generic.h b/usb/store/asm-m68k/byteorder/generic.h
new file mode 100644
index 0000000..e3db5cc
--- /dev/null
+++ b/usb/store/asm-m68k/byteorder/generic.h
@@ -0,0 +1,180 @@
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+#define _LINUX_BYTEORDER_GENERIC_H
+
+/*
+ * linux/byteorder_generic.h
+ * Generic Byte-reordering support
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19970707
+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
+ *    cleaned them up.
+ *    I hope it is compliant with non-GCC compilers.
+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
+ *    because I wasn't sure it would be ok to put it in types.h
+ *    Upgraded it to 2.1.43
+ * Francois-Rene Rideau <fare@tunes.org> 19971012
+ *    Upgraded it to 2.1.57
+ *    to please Linus T., replaced huge #ifdef's between little/big endian
+ *    by nestedly #include'd files.
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    Made it to 2.1.71; now a facelift:
+ *    Put files under include/linux/byteorder/
+ *    Split swab from generic support.
+ *
+ * TODO:
+ *   = Regular kernel maintainers could also replace all these manual
+ *    byteswap macros that remain, disseminated among drivers,
+ *    after some grep or the sources...
+ *   = Linus might want to rename all these macros and files to fit his taste,
+ *    to fit his personal naming scheme.
+ *   = it seems that a few drivers would also appreciate
+ *    nybble swapping support...
+ *   = every architecture could add their byteswap macro in asm/byteorder.h
+ *    see how some architectures already do (i386, alpha, ppc, etc)
+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
+ *    distinguished throughout the kernel. This is not the case currently,
+ *    since little endian, big endian, and pdp endian machines needn't it.
+ *    But this might be the case for, say, a port of Linux to 20/21 bit
+ *    architectures (and F21 Linux addict around?).
+ */
+
+/*
+ * The following macros are to be defined by <asm/byteorder.h>:
+ *
+ * Conversion of long and short int between network and host format
+ *	ntohl(__u32 x)
+ *	ntohs(__u16 x)
+ *	htonl(__u32 x)
+ *	htons(__u16 x)
+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
+ * might like the above to be functions, not macros (why?).
+ * if that's true, then detect them, and take measures.
+ * Anyway, the measure is: define only ___ntohl as a macro instead,
+ * and in a separate file, have
+ * unsigned long inline ntohl(x){return ___ntohl(x);}
+ *
+ * The same for constant arguments
+ *	__constant_ntohl(__u32 x)
+ *	__constant_ntohs(__u16 x)
+ *	__constant_htonl(__u32 x)
+ *	__constant_htons(__u16 x)
+ *
+ * Conversion of XX-bit integers (16- 32- or 64-)
+ * between native CPU format and little/big endian format
+ * 64-bit stuff only defined for proper architectures
+ *	cpu_to_[bl]eXX(__uXX x)
+ *	[bl]eXX_to_cpu(__uXX x)
+ *
+ * The same, but takes a pointer to the value to convert
+ *	cpu_to_[bl]eXXp(__uXX x)
+ *	[bl]eXX_to_cpup(__uXX x)
+ *
+ * The same, but change in situ
+ *	cpu_to_[bl]eXXs(__uXX x)
+ *	[bl]eXX_to_cpus(__uXX x)
+ *
+ * See asm-foo/byteorder.h for examples of how to provide
+ * architecture-optimized versions
+ *
+ */
+
+
+//#if defined(__KERNEL__)
+/*
+ * inside the kernel, we can use nicknames;
+ * outside of it, we must avoid POSIX namespace pollution...
+ */
+#define cpu_to_le64 __cpu_to_le64
+#define le64_to_cpu __le64_to_cpu
+#define cpu_to_le32 __cpu_to_le32
+#define le32_to_cpu __le32_to_cpu
+#define cpu_to_le16 __cpu_to_le16
+#define le16_to_cpu __le16_to_cpu
+#define cpu_to_be64 __cpu_to_be64
+#define be64_to_cpu __be64_to_cpu
+#define cpu_to_be32 __cpu_to_be32
+#define be32_to_cpu __be32_to_cpu
+#define cpu_to_be16 __cpu_to_be16
+#define be16_to_cpu __be16_to_cpu
+#define cpu_to_le64p __cpu_to_le64p
+#define le64_to_cpup __le64_to_cpup
+#define cpu_to_le32p __cpu_to_le32p
+#define le32_to_cpup __le32_to_cpup
+#define cpu_to_le16p __cpu_to_le16p
+#define le16_to_cpup __le16_to_cpup
+#define cpu_to_be64p __cpu_to_be64p
+#define be64_to_cpup __be64_to_cpup
+#define cpu_to_be32p __cpu_to_be32p
+#define be32_to_cpup __be32_to_cpup
+#define cpu_to_be16p __cpu_to_be16p
+#define be16_to_cpup __be16_to_cpup
+#define cpu_to_le64s __cpu_to_le64s
+#define le64_to_cpus __le64_to_cpus
+#define cpu_to_le32s __cpu_to_le32s
+#define le32_to_cpus __le32_to_cpus
+#define cpu_to_le16s __cpu_to_le16s
+#define le16_to_cpus __le16_to_cpus
+#define cpu_to_be64s __cpu_to_be64s
+#define be64_to_cpus __be64_to_cpus
+#define cpu_to_be32s __cpu_to_be32s
+#define be32_to_cpus __be32_to_cpus
+#define cpu_to_be16s __cpu_to_be16s
+#define be16_to_cpus __be16_to_cpus
+//#endif
+
+
+/*
+ * Handle ntohl and suches. These have various compatibility
+ * issues - like we want to give the prototype even though we
+ * also have a macro for them in case some strange program
+ * wants to take the address of the thing or something..
+ *
+ * Note that these used to return a "long" in libc5, even though
+ * long is often 64-bit these days.. Thus the casts.
+ *
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+
+#undef ntohl
+#undef ntohs
+#undef htonl
+#undef htons
+
+/*
+ * Do the prototypes. Somebody might want to take the
+ * address or some such sick thing..
+ */
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+extern __u32			ntohl(__u32);
+extern __u32			htonl(__u32);
+#else
+extern unsigned long int	ntohl(unsigned long int);
+extern unsigned long int	htonl(unsigned long int);
+#endif
+extern unsigned short int	ntohs(unsigned short int);
+extern unsigned short int	htons(unsigned short int);
+
+
+#if defined(__GNUC__) && (__GNUC__ >= 2)
+
+#define ___htonl(x) __cpu_to_be32(x)
+#define ___htons(x) __cpu_to_be16(x)
+#define ___ntohl(x) __be32_to_cpu(x)
+#define ___ntohs(x) __be16_to_cpu(x)
+
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+#define htonl(x) ___htonl(x)
+#define ntohl(x) ___ntohl(x)
+#else
+#define htonl(x) ((unsigned long)___htonl(x))
+#define ntohl(x) ((unsigned long)___ntohl(x))
+#endif
+#define htons(x) ___htons(x)
+#define ntohs(x) ___ntohs(x)
+
+#endif /* OPTIMIZE */
+
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
diff --git a/usb/store/asm-m68k/byteorder/little_endian.h b/usb/store/asm-m68k/byteorder/little_endian.h
new file mode 100644
index 0000000..b6c67eb
--- /dev/null
+++ b/usb/store/asm-m68k/byteorder/little_endian.h
@@ -0,0 +1,69 @@
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+#define __LITTLE_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__LITTLE_ENDIAN
+
+#include "swab.h"
+
+#define __constant_htonl(x) ___constant_swab32((x))
+#define __constant_ntohl(x) ___constant_swab32((x))
+#define __constant_htons(x) ___constant_swab16((x))
+#define __constant_ntohs(x) ___constant_swab16((x))
+#define __constant_cpu_to_le64(x) ((__u64)(x))
+#define __constant_le64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_le32(x) ((__u32)(x))
+#define __constant_le32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_le16(x) ((__u16)(x))
+#define __constant_le16_to_cpu(x) ((__u16)(x))
+#define __constant_cpu_to_be64(x) ___constant_swab64((x))
+#define __constant_be64_to_cpu(x) ___constant_swab64((x))
+#define __constant_cpu_to_be32(x) ___constant_swab32((x))
+#define __constant_be32_to_cpu(x) ___constant_swab32((x))
+#define __constant_cpu_to_be16(x) ___constant_swab16((x))
+#define __constant_be16_to_cpu(x) ___constant_swab16((x))
+#define __cpu_to_le64(x) ((__u64)(x))
+#define __le64_to_cpu(x) ((__u64)(x))
+#define __cpu_to_le32(x) ((__u32)(x))
+#define __le32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_le16(x) ((__u16)(x))
+#define __le16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_be64(x) __swab64((x))
+#define __be64_to_cpu(x) __swab64((x))
+#define __cpu_to_be32(x) __swab32((x))
+#define __be32_to_cpu(x) __swab32((x))
+#define __cpu_to_be16(x) __swab16((x))
+#define __be16_to_cpu(x) __swab16((x))
+#define __cpu_to_le64p(x) (*(__u64*)(x))
+#define __le64_to_cpup(x) (*(__u64*)(x))
+#define __cpu_to_le32p(x) (*(__u32*)(x))
+#define __le32_to_cpup(x) (*(__u32*)(x))
+#define __cpu_to_le16p(x) (*(__u16*)(x))
+#define __le16_to_cpup(x) (*(__u16*)(x))
+#define __cpu_to_be64p(x) __swab64p((x))
+#define __be64_to_cpup(x) __swab64p((x))
+#define __cpu_to_be32p(x) __swab32p((x))
+#define __be32_to_cpup(x) __swab32p((x))
+#define __cpu_to_be16p(x) __swab16p((x))
+#define __be16_to_cpup(x) __swab16p((x))
+#define __cpu_to_le64s(x) do {} while (0)
+#define __le64_to_cpus(x) do {} while (0)
+#define __cpu_to_le32s(x) do {} while (0)
+#define __le32_to_cpus(x) do {} while (0)
+#define __cpu_to_le16s(x) do {} while (0)
+#define __le16_to_cpus(x) do {} while (0)
+#define __cpu_to_be64s(x) __swab64s((x))
+#define __be64_to_cpus(x) __swab64s((x))
+#define __cpu_to_be32s(x) __swab32s((x))
+#define __be32_to_cpus(x) __swab32s((x))
+#define __cpu_to_be16s(x) __swab16s((x))
+#define __be16_to_cpus(x) __swab16s((x))
+
+#include "generic.h"
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
diff --git a/usb/store/asm-m68k/byteorder/swab.h b/usb/store/asm-m68k/byteorder/swab.h
new file mode 100644
index 0000000..d3394b0
--- /dev/null
+++ b/usb/store/asm-m68k/byteorder/swab.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_BYTEORDER_SWAB_H
+#define _LINUX_BYTEORDER_SWAB_H
+
+/*
+ * linux/byteorder/swab.h
+ * Byte-swapping, independently from CPU endianness
+ *	swabXX[ps]?(foo)
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    separated swab functions from cpu_to_XX,
+ *    to clean up support for bizarre-endian architectures.
+ *
+ * See asm-i386/byteorder.h and suches for examples of how to provide
+ * architecture-dependent optimized versions
+ *
+ */
+
+/* casts are necessary for constants, because we never know how for sure
+ * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
+ */
+#define ___swab16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define ___swab32(x) \
+	((__u32)( \
+		(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
+#define ___swab64(x) \
+	((__u64)( \
+		(__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) <<  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >>  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \
+		(__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) ))
+
+/*
+ * provide defaults when no architecture-specific optimization is detected
+ */
+#ifndef __arch__swab16
+#  define __arch__swab16(x) ___swab16(x)
+#endif
+#ifndef __arch__swab32
+#  define __arch__swab32(x) ___swab32(x)
+#endif
+#ifndef __arch__swab64
+#  define __arch__swab64(x) ___swab64(x)
+#endif
+
+#ifndef __arch__swab16p
+#  define __arch__swab16p(x) __swab16(*(x))
+#endif
+#ifndef __arch__swab32p
+#  define __arch__swab32p(x) __swab32(*(x))
+#endif
+#ifndef __arch__swab64p
+#  define __arch__swab64p(x) __swab64(*(x))
+#endif
+
+#ifndef __arch__swab16s
+#  define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0)
+#endif
+#ifndef __arch__swab32s
+#  define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0)
+#endif
+#ifndef __arch__swab64s
+#  define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0)
+#endif
+
+
+/*
+ * Allow constant folding
+ */
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
+#  define __swab16(x) \
+(__builtin_constant_p((__u16)(x)) ? \
+ ___swab16((x)) : \
+ __fswab16((x)))
+#  define __swab32(x) \
+(__builtin_constant_p((__u32)(x)) ? \
+ ___swab32((x)) : \
+ __fswab32((x)))
+#  define __swab64(x) \
+(__builtin_constant_p((__u64)(x)) ? \
+ ___swab64((x)) : \
+ __fswab64((x)))
+#else
+#  define __swab16(x) __fswab16(x)
+#  define __swab32(x) __fswab32(x)
+#  define __swab64(x) __fswab64(x)
+#endif /* OPTIMIZE */
+
+
+static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x)
+{
+	return __arch__swab16(x);
+}
+static __inline__ __u16 __swab16p(__u16 *x)
+{
+	return __arch__swab16p(x);
+}
+static __inline__ void __swab16s(__u16 *addr)
+{
+	__arch__swab16s(addr);
+}
+
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
+{
+	return __arch__swab32(x);
+}
+static __inline__ __u32 __swab32p(__u32 *x)
+{
+	return __arch__swab32p(x);
+}
+static __inline__ void __swab32s(__u32 *addr)
+{
+	__arch__swab32s(addr);
+}
+
+#ifdef __BYTEORDER_HAS_U64__
+static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x)
+{
+#  ifdef __SWAB_64_THRU_32__
+	__u32 h = x >> 32;
+	__u32 l = x & ((1ULL<<32)-1);
+	return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h)));
+#  else
+	return __arch__swab64(x);
+#  endif
+}
+static __inline__ __u64 __swab64p(__u64 *x)
+{
+	return __arch__swab64p(x);
+}
+static __inline__ void __swab64s(__u64 *addr)
+{
+	__arch__swab64s(addr);
+}
+#endif /* __BYTEORDER_HAS_U64__ */
+
+//#if defined(__KERNEL__)
+#define swab16 __swab16
+#define swab32 __swab32
+#define swab64 __swab64
+#define swab16p __swab16p
+#define swab32p __swab32p
+#define swab64p __swab64p
+#define swab16s __swab16s
+#define swab32s __swab32s
+#define swab64s __swab64s
+//#endif
+
+#endif /* _LINUX_BYTEORDER_SWAB_H */
diff --git a/usb/store/asm-m68k/io.h b/usb/store/asm-m68k/io.h
new file mode 100644
index 0000000..3c6455d
--- /dev/null
+++ b/usb/store/asm-m68k/io.h
@@ -0,0 +1,263 @@
+/*
+ * IO header file
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_M68K_IO_H__
+#define __ASM_M68K_IO_H__
+
+#include "byteorder.h"
+
+#define __raw_readb(addr) (*(volatile u8 *)(addr))
+#define __raw_readw(addr) (*(volatile u16 *)(addr))
+#define __raw_readl(addr) (*(volatile u32 *)(addr))
+
+#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
+#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
+
+#define readb(addr)		in_8((volatile u8 *)(addr))
+#define writeb(b,addr)		out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+//#if defined(__BIG_ENDIAN)
+#define readw(addr)		(*(volatile u16 *) (addr))
+#define readl(addr)		(*(volatile u32 *) (addr))
+#define writew(b,addr)		((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr)		((*(volatile u32 *) (addr)) = (b))
+#else				/* Galvez: in_le16() does the swap reading 
+				 * twice from fifo (register), when reading 
+				 * from fifo once the value is changed by the new one */
+#define readw(addr)		ld_le16((volatile u16 *)(addr))   /* instead of in_le16((volatile u16 *)(addr))*/
+#define readl(addr)		in_le32((volatile u32 *)(addr))
+#define writew(b,addr)		out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr)		out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns)	_insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns)	_outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port)		in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port)		out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+//#if defined(__BIG_ENDIAN)
+#define inw(port)		in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)		out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)		in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)		out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port)		in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)		out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)		in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)		out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+extern inline void _insb(volatile u8 * port, void *buf, int ns)
+{
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*data++ = *port;
+}
+
+extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
+{
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*port = *data++;
+}
+
+extern inline void _insw(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = __sw16(*port);
+}
+
+extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = __sw16(*data);
+		data++;
+	}
+}
+
+extern inline void _insl(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = __sw32(*port);
+}
+
+extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = __sw32(*data);
+		data++;
+	}
+}
+
+extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = *port;
+}
+
+extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = *data++;
+	}
+}
+
+extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = *port;
+}
+
+extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = *data;
+		data++;
+	}
+}
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define IO_SPACE_LIMIT ~0
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+extern inline int in_8(volatile u8 * addr)
+{
+	return (int)*addr;
+}
+
+extern inline void out_8(volatile u8 * addr, int val)
+{
+	*addr = (u8) val;
+}
+
+extern inline int in_le16(volatile u16 * addr)
+{
+	return __sw16(*addr);
+}
+
+extern inline int in_be16(volatile u16 * addr)
+{
+	return (*addr & 0xFFFF);
+}
+
+extern inline void out_le16(volatile u16 * addr, int val)
+{
+	*addr = __sw16(val);
+}
+
+extern inline void out_be16(volatile u16 * addr, int val)
+{
+	*addr = (u16) val;
+}
+
+extern inline unsigned in_le32(volatile u32 * addr)
+{
+	return __sw32(*addr);
+}
+
+extern inline unsigned in_be32(volatile u32 * addr)
+{
+	return (*addr);
+}
+
+extern inline void out_le32(volatile unsigned *addr, int val)
+{
+	*addr = __sw32(val);
+}
+
+extern inline void out_be32(volatile unsigned *addr, int val)
+{
+	*addr = val;
+}
+
+static inline void sync(void)
+{
+	/* This sync function is for PowerPC or other architecture instruction
+	 * ColdFire does not have this instruction. Dummy function, added for
+	 * compatibility (CFI driver)
+	 */
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
+				unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+#endif				/* __ASM_M68K_IO_H__ */
diff --git a/usb/store/asm-m68k/types.h b/usb/store/asm-m68k/types.h
new file mode 100644
index 0000000..42ff2a6
--- /dev/null
+++ b/usb/store/asm-m68k/types.h
@@ -0,0 +1,53 @@
+#ifndef _M68K_TYPES_H
+#define _M68K_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+typedef struct {
+	__u32 u[4];
+} __attribute__((aligned(16))) vector128;
+
+//#ifdef __KERNEL__
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+//#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/usb/store/bios.S b/usb/store/bios.S
new file mode 100644
index 0000000..fb83a92
--- /dev/null
+++ b/usb/store/bios.S
@@ -0,0 +1,1378 @@
+/* TOS 4.04 Xbios dispatcher for the CT60/CTPCI boards
+ * and USB-disk / Ram-Disk utility
+ * Didier Mequignon 2005-2009, e-mail: aniplay@wanadoo.fr
+ *
+ * Modified to be used as an application by David Gálvez 2010.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+ 
+
+ 
+#include "config.h"
+#include "vars.h"
+
+#define old_pun_ptr 	0x516
+
+#undef pun_ptr
+#define pun_ptr pun_ptr_usb
+
+.global	_max_logical_drive
+
+#define MAX_LOGICAL_DRIVE	_max_logical_drive
+
+.chip 68040
+
+.global ___mint
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \
+	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+	.global _install_usb_stor,_usb_stor_read,_usb_stor_write,_usb_1st_disk_drive,_SuperFromUser, _SuperTouser
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */
+
+
+
+#if defined(CONFIG_USB_KEYBOARD) || (CONFIG_USB_MOUSE)
+.global _asm_set_ipl
+.global _call_ikbdvec,_call_mousevec
+#endif
+
+#ifdef DEBUG_BIOS_LAYER
+	.global display_string,hex_long,hex_word,hex_byte,display_char,wait_key,_debug
+#endif
+
+	.data
+
+/* XHDI */
+
+#define XH_DL_SECSIZ 0 // maximal sector size (BIOS level)
+#define XH_DL_MINFAT 1 // minimal number of FATs
+#define XH_DL_MAXFAT 2 // maximal number of FATs
+#define XH_DL_MINSPC 3 // sectors per cluster minimal
+#define XH_DL_MAXSPC 4 // sectors per cluster maximal
+#define XH_DL_CLUSTS 5 // maximal number of clusters of a 16 bit FAT
+#define XH_DL_MAXSEC 6 // maximal number of sectors
+#define XH_DL_DRIVES 7 // maximal number of BIOS drives supported by the DOS
+
+	
+/* AHDI */
+
+#define PUN_DEV           0x1F /* device number of HD */
+#define PUN_UNIT          0x07 /* Unit number */
+#define PUN_SCSI          0x08 /* 1=SCSI 0=ACSI */
+#define PUN_IDE           0x10 /* Falcon IDE */
+#define PUN_USB           0x20 /* USB */
+#define PUN_REMOVABLE     0x40 /* Removable media */
+#define PUN_VALID         0x80 /* zero if valid */
+
+#define pinfo_puns      0  // 2 bytes
+#define pinfo_pun       2  // 32 bytes
+#define pinfo_pstart   34  // 32 x 4 bytes
+#define pinfo_cookie  162  // 4 bytes
+#define pinfo_cookptr 166  // 4 bytes
+#define pinfo_vernum  170  // 2 bytes
+#define pinfo_maxsiz  172  // 2 bytes
+#define pinfo_ptype   174  // 32 x 4 bytes
+#define pinfo_psize   302  // 32 x 4 bytes
+#define pinfo_flags   430  // 32 x 2 bytes, internal use: B15:swap, B7:change, B0:bootable
+#define pinfo_bpb     494  // 32 x 32 bytes
+#define pinfo_devnum 1518  // 32 bytes 
+#define pinfo_size   1550
+
+
+#if 1//#ifdef DEBUG_BIOS_LAYER
+//debug1:	.asciz "XBIOS #0x"
+//debug2:	.asciz "Setscreen 0x"
+debug3:	.asciz "hdv_rw 0x"
+debug4:	.ascii "hdv_bpb"
+	.byte 13,10,0
+debug5:	.ascii "hdv_mediach"
+	.byte 13,10,0
+//debug6:	.asciz "Vsetmode 0x"
+//debug7:	.asciz "ValidMode 0x"
+//debug8:	.asciz "Gettime 0x
+debug132:	.asciz "XHDI XHReadWrite 0x"
+debug133:	.ascii "XHDI XHInqTarget2"
+	.byte 13,10,0
+debug134:	.ascii "XHDI XHInqDev"
+	.byte 13,10,0
+debug135:	.ascii "XHDI XHInqDriver"
+	.byte 13,10,0
+debug136:	.ascii "XHDI XHInqDev2"
+	.byte 13,10,0
+debug137:	.ascii "XHDI XHDOSLimits"
+	.byte 13,10,0
+debug138:	.ascii "GALVEZ DEBUG"		/* Galvez: DEBUG */
+	.byte 13,10,0
+debug139:	.ascii "XHDI XHReadWrite"	/* Galvez: DEBUG */
+	.byte 13,10,0
+	.align 2
+#endif
+
+
+//	dc.l 0x58425241          // XBRA
+//	dc.l 0x5F504349          // _PCI
+//	dc.l 0                   // cannot store here because we are in flash
+
+
+
+text_color:
+
+	moveq #0,D0
+	move.w 0x3E86,D0         // number of planes
+	cmp.l #2,D0
+	bls.s .black_and_white
+	pea (A0)
+	move.w #9,-(SP)
+	trap #1                  // Cconws
+	addq.l #6,SP
+.black_and_white:
+	rts
+	
+#if defined(CONFIG_USB_KEYBOARD) || (CONFIG_USB_MOUSE)
+_asm_set_ipl:
+	link A6,#-8
+	movem.l D6-D7,(SP)
+	move.w SR,D7            //  current SR 
+	move.l D7,D0            //  prepare return value
+	and.l #0x0700,D0        // mask out IPL 
+	lsr.l #8,D0             // IPL 
+	move.l 8(A6),D6         // get argument 
+	and.l #7,D6             // least significant three bits 
+	lsl.l #8,D6             // move over to make mask 
+	and.l #0x0000F8FF,D7    // zero out current IPL 
+	or.l D6,D7              // place new IPL in SR 
+	move.w D7,SR
+	movem.l (SP),D6-D7
+	lea 8(SP),SP
+	unlk A6
+	rts
+	
+_call_ikbdvec:
+
+	lea -24(SP),SP
+	movem.l D0-D2/A0-A2,(SP)
+	move.l 28(SP),D0         // ikbd code 
+	move.l 32(SP),A0         // iorec 
+	and.l #0xFF,D0
+	move.l 0x1132,A2         // ikbdvec 
+	jsr (A2)
+	movem.l (SP),D0-D2/A0-A2
+	lea 24(SP),SP
+	rts
+
+_call_mousevec:
+
+	lea -24(SP),SP
+	movem.l D0-D2/A0-A2,(SP)
+	move.l 28(SP),A0         // data 
+	move.l 32(SP),A2
+	move.l (A2),A2           // mousevec 
+	jsr (A2)
+	movem.l (SP),D0-D2/A0-A2
+	lea 24(SP),SP
+	rts
+#endif
+
+install_xbra:	// A0: handler, D0: vector, D1: ID 
+
+	lea -28(SP),SP
+	movem.l D1-D3/A0-A3,(SP)
+	moveq #0,D3
+	move.w D0,D3             // vector
+	move.l A0,A3             // handler
+	move.l D1,-(SP)
+	move.w #3,-(SP)          // TT ram if possible
+	move.l #18,-(SP)         // size
+	move.w #0x44,-(SP)       // Mxalloc
+	trap #1 
+	addq.l #8,SP
+	move.l (SP)+,D1
+	tst.l D0
+	beq.s .error_xbra
+	move.l D0,A0
+	move.l #0x58425241,(A0)+ // XBRA
+	move.l D1,(A0)+
+	clr.l (A0)+	
+	move.w #0x4EF9,(A0)+     // JMP
+	move.l A3,(A0)+          // handler
+	lea -10(A0),A0
+
+	cpusha BC
+
+	move.l D3,A1
+	move.l (A1),D0
+	move.l D0,(A0)+          // old vector
+	move.l A0,(A1)           // JMP, new vector
+.error_xbra:
+	tst.l D0
+	movem.l (SP),D1-D3/A0-A3
+	lea 28(SP),SP
+	rts
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \
+	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+_install_usb_stor:
+	lea -32(SP),SP
+	movem.l D1-D4/A0-A3,(SP)
+	move.l 36(SP),D0         // dev_num
+	cmp.l #PUN_DEV,D0
+	bhi .no_pinfo            // error
+	move.l 40(SP),D2         // part_type
+	move.l D2,D1
+	and.l #0xFFFFFF,D1       // ID
+	// GEMDOS
+	cmp.l #0x47454D,D1       // GEM up to 16M
+	beq.s .partition_ok
+	cmp.l #0x42474D,D1       // BGM over 16M
+	beq.s .partition_ok
+	cmp.l #0x524157,D1       // RAW
+	beq.s .partition_ok
+	// DOS 1:FAT12, 0xB/0xC:FAT32
+	cmp.l #0x4,D2            // FAT16 up to 32M
+	beq.s .partition_ok
+	cmp.l #0x6,D2            // FAT16 over 32M
+	beq.s .partition_ok
+	tst.l ___mint		// Galvez: NOT MiNT? then go out
+	beq .invalid_partition_type
+	cmp.l #0xE,D2            // WIN95 FAT16
+	beq .partition_ok
+	cmp.l #0xB,D2		// FAT32
+	beq.s .partition_ok
+	cmp.l #0xC,D2		// FAT32
+	bne .partition_ok
+	cmp.l #0x81,D2		// MINIX
+	bne .partition_ok
+	cmp.l #0x83,D2		// EXT2/LNX
+	bne .partition_ok
+.partition_ok:
+	move.l old_pun_ptr,A2	// Galvez: we need it to update hd driver pun struct
+	move.l pun_ptr,D0
+	bne.s .pinfo_ok
+	move.w #3,-(SP)          // TT ram if possible
+	move.l #pinfo_size,-(SP)
+	move.w #0x44,-(SP)       // Mxalloc
+	trap #1 
+	addq.l #8,SP
+	move.l D0,pun_ptr
+	beq.s .no_pinfo
+	move.l D0,A3
+	clr.w pinfo_puns(A3)
+	move.w #0x0300,D0
+	move.w D0,pinfo_vernum(A3)
+	move.w #0x4000,D0
+	move.w D0,pinfo_maxsiz(A3)
+	lea pinfo_pun(A3),A0
+	moveq #-1,D0
+	move.w D0,(A0)+          // drives A/B
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.w D0,(A0)
+	lea pinfo_pstart(A3),A0
+	lea pinfo_size(A3),A1
+.clrpun:
+	clr.w -(A1)
+	cmp.l A0,A1
+	bgt.s .clrpun
+	move.l A3,D0             // pun_ptr 
+.pinfo_ok:
+	move.l D0,A3             // pun_ptr 
+	moveq #2,D4              // drive C 
+	move.l _drvbits,D0
+.search_empty_drive_usb:
+	btst D4,D0
+	beq.s .drive_not_exist_usb
+	addq.l #1,D4
+	cmp.l #MAX_LOGICAL_DRIVE,D4
+	bcs.s .search_empty_drive_usb
+	bra .drive_full_usb          // all drives already used 
+.no_pinfo:
+	moveq #0,D0              // not installed 
+	bra .end_usb_disk
+.drive_not_exist_usb:
+	move.w pinfo_puns(A3),D0
+	addq.l #1,D0
+	move.w D0,pinfo_puns(A3)
+	moveq #0,D0
+	bset #7,D0               // changed
+	lea pinfo_flags(A3),A0
+	move.l D0,(A0,D4.l*4)    // B15:swap, B7:change, B0:bootable
+	lea pinfo_psize(A3),A0
+	move.l 48(SP),D3         // part_size
+	move.l 44(SP),D1         // part_offset
+	move.l 40(SP),D2         // part_type
+	move.l 36(SP),D0         // dev_num
+	move.b D0,pinfo_devnum(A3,D4.l)
+	move.l D2,pinfo_ptype(A3,D4.l*4)
+	move.l D4,D2
+	or.l #PUN_USB,D2
+	move.b D2,pinfo_pun(A3,D4.l)
+	cmp.l #15,D4			// Galvez: update AHDI pun struct:
+	bgt .ahdi_part_num_limit	// Galvez: if logical part. > 16
+	move.b D2,pinfo_pun(A2,D4.l)	// Galvez: don't update pun struct,
+	move.w D0,-(SP)			// Galvez: to avoid corruption.
+	move.w pinfo_puns(A2),D0	// Galvez: update hd driver pun stuct
+	addq.l #1,D0			// Galvez: othewise MiNT only handles 16MB
+	move.w D0,pinfo_puns(A2)	// Galvez: when not using XHDI
+	move.w (SP)+,D0			// Galvez: see BLOCK_IO.c (MiNT sources)
+.ahdi_part_num_limit:			
+	move.l D3,(A0,D4.l*4)    // size
+	move.l D1,pinfo_pstart(A3,D4.l*4)	
+	move.l _dskbufp,A0 
+	move.l A0,-(SP)          // buffer
+	move.l #1,-(SP)          // blkcnt	
+	move.l D1,-(SP)          // blknr
+	move.l D0,-(SP)          // devnum
+	jsr _usb_stor_read
+	lea 16(SP),SP
+	tst.l D0
+	beq .end_usb_disk        // read error
+	tst.l _usb_1st_disk_drive
+	bne .usb_1st_drive_ok    // hdv vectors installed
+	move.l D4,_usb_1st_disk_drive
+	move.w SR,D0
+	move.w D0,-(SP)
+	or.l #0x700,D0           // mask interrupts
+	move.w D0,SR
+	move.l #0x5F555342,D1    // _USB
+	lea det_hdv_bpb_usb(PC),A0
+	move.w #hdv_bpb,D0
+	bsr install_xbra
+	move.l D0,old_hdv_bpb_usb
+	lea det_hdv_rw_usb(PC),A0
+	move.w #hdv_rw,D0
+	bsr install_xbra	
+	move.l D0,old_hdv_rw_usb
+	lea det_hdv_mediach_usb(PC),A0
+	move.w #hdv_mediach,D0
+	bsr install_xbra
+	move.l D0,old_hdv_mediach_usb
+	move.l cookie,D0
+	beq.s .no_cookie_jar
+	move.l D0,A0
+	move.l #0x58484449,D1    // XHDI
+.find_cookie_jar:
+	tst.l (A0)
+	beq.s .cookie_slot_free
+	cmp.l (A0),D1
+	beq.s .cookie_found
+	addq.l #8,A0
+	bra.s .find_cookie_jar
+.cookie_found:
+	move.l 4(A0),D0
+	move.l D0,old_xhdi
+	lea xhdi(PC),A1
+	clr.l -(SP)              	// XHGetVersion
+	move.l D0,A0
+	jsr (A0)
+	addq.l #4,SP
+	move.l D0,old_xhdi_version
+	move.l A1,-(SP)			
+	move.w #9,-(SP)			// Galvez: XHNewCookie
+	jsr (A0)
+	add.l #6,SP
+	tst.l D0
+	beq.s .no_cookie_jar
+	move.l A1,4(A0)			// Galvez: Replace cookie "by-hand"			
+	bra.s .no_cookie_jar
+.cookie_slot_free:
+	move.l 4(A0),12(A0)      // copy size
+	lea xhdi(PC),A1
+	move.l A1,(A0)+
+	clr.l (A0)
+	clr.l old_xhdi
+	move.l #0x120,D0         //  protocol version
+	move.l D0,old_xhdi_version
+.no_cookie_jar:
+	move.w (SP)+,D0
+	move.w D0,SR		// restore interrupts
+.usb_1st_drive_ok:
+	move.l _dskbufp,A0       // boot sector 
+	lea pinfo_bpb(A3),A1
+	move.l D4,D2             // logical drive 
+	asl.l #5,D2              // * 32 
+	add.l D2,A1
+	moveq #0,D2
+	move.b 0xC(A0),D2
+	asl.l #8,D2
+	move.b 0xB(A0),D2        // BPS 
+	move.w D2,(A1)           // sector size 
+	moveq #0,D1
+	move.b 0xD(A0),D1        // SPC 
+	move.w D1,2(A1)          // cluster size in sectors 
+	move.w D1,D0
+	mulu D2,D0	
+	move.w D0,4(A1)          // cluster size in bytes 
+	moveq #0,D0
+	move.b 0x12(A0),D0
+	asl.l #8,D0
+	move.b 0x11(A0),D0       // NDIRS 
+	asl.l #5,D0              // * 32 
+
+	divu D2,D0               // / sector size 
+
+	move.w D0,6(A1)          // size directory in sectors 
+	moveq #0,D2
+	move.b 0x17(A0),D2
+	asl.l #8,D2
+	move.b 0x16(A0),D2       // SPF 
+	move.w D2,8(A1)          // FAT size 
+	moveq #0,D0
+	move.b 0xF(A0),D0
+	asl.l #8,D0
+	move.b 0xE(A0),D0        // RES 
+	move.l D0,D3
+	add.l D2,D3              // + FAT size 
+	move.w D3,10(A1)         // 1st sector of FAT2  
+	moveq #0,D3
+	move.b 0x10(A0),D3       // NFATS 
+	mulu D2,D3               // * FAT size 
+	add.l D0,D3              // + RES 
+	moveq #0,D0
+	move.w 6(A1),D0          // size directory in sectors 
+	add.l D3,D0
+	move.w D0,12(A1)         // 1st data sector 
+	moveq #0,D2
+	move.b 0x14(A0),D2
+	asl.l #8,D2
+	move.b 0x13(A0),D2       // NSECTS 
+	bne.s .nsects_ok_usb
+	lea pinfo_psize(A3),A2
+	move.l (A2,D4.w*4),D2    // partition size in sectors 
+	sub.l D0,D2              // - 1st data sector 
+.nsects_ok_usb:
+	divu D1,D2
+
+	move.w D2,14(A1)         // total clusters 
+	moveq #1,D0 
+	move.w D0,16(A1)         // FAT 16 
+	clr.w 18(A1)
+	clr.l 20(A1)
+	clr.l 24(A1)
+	clr.l 28(A1)	
+	move.l _drvbits,D0
+	bset D4,D0
+	move.l D0,_drvbits
+	moveq #2,D0              // drive C 
+	cmp.l D4,D0
+	bne.s .no_set_drive_usb
+	move.w D0,_bootdev
+	move.w D0,-(SP)
+	move.w #0xE,-(SP)        // Dsetdrv 
+	trap #1
+	addq.l #4,SP
+.no_set_drive_usb:
+	move.l 36(SP),D0         // devnum        
+	movem.l 52(SP),A1/A2/A3  // vendor / revision / product
+	move.l product_name,A0      // save product name pointer for XHDI
+#if DEBUG_BIOS_LAYER	
+	move.l D0, -(SP)
+	move.b D4,D0
+	jsr hex_byte		/* Galvez: DEBUG device */	
+	move.l (SP)+,D0
+#endif
+	move.l A3,(A0,D4.l*4)
+	bsr display_drive_usb
+	pea message2b(PC)
+	move.w #9,-(SP)
+	trap #1                  // Cconws
+	addq.l #6,SP
+	moveq #0x41,D0           // A
+	add.l D4,D0
+	move.w D0,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout
+	addq.l #4,SP
+	pea crlf(PC)
+	move.w #9,-(SP)
+	trap #1                  // Cconws
+	addq.l #6,SP
+	move.l D4,D0             // OK
+	bra.s .end_usb_disk
+.invalid_partition_type:
+	pea error4(PC)
+	bra.s .display_error_usb
+.drive_full_usb:
+	pea error2(PC)
+.display_error_usb:
+	move.l 36+4(SP),D0       // devnum 
+        movem.l 52+4(SP),A1/A2/A3 // vendor / revision / product 
+	bsr display_drive_usb
+	move.w #0x2C,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP
+	moveq #0,D0              // not installed 
+.end_usb_disk:
+	movem.l (SP),D1-D4/A0-A3
+	lea 32(SP),SP
+	rts
+
+display_drive_usb:
+
+	move.l A1,-(SP)
+	moveq #0x30,D1
+	add.l D1,D0	            // dev_num 
+	move.w D0,-(SP)         
+	lea blue(PC),A0
+	bsr text_color
+	pea message2(PC)         // USB-disk installed 
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #0x2E,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #0x30,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	lea black(PC),A0
+	bsr text_color
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP    
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+        move.l A2,-(SP)
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP             
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+        move.l A3,-(SP)
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP
+	rts
+
+det_hdv_bpb_usb:
+	move.l A0,-(SP)
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 4+4(SP),D0        // drive
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .dhbu2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .dhbu2
+	tst.b pinfo_pun(A0,D0.l)
+	bpl.s .dhbu1
+.dhbu2:
+	move.l (SP)+,A0
+	moveq #0,D0
+	move.l old_hdv_bpb_usb,-(SP)
+	rts
+.dhbu1:
+	move.l D1,-(SP)
+	move.l pinfo_ptype(A0,D0.l*4),D1
+	and.l #0xFFFFFF,D1
+	cmp.l #0x524157,D1       // RAW
+	beq.s .dhbu4
+	cmp.l #0x81,D1       	 // MINIX
+	beq.s .dhbu4
+	cmp.l #0x83,D1       	 // EXT2/LNX
+	bne.s .dhbu3
+.dhbu4:
+	move.l (SP)+,D1
+	move.l (SP)+,A0
+	moveq #0,D0
+	rts	
+.dhbu3:
+	lea pinfo_bpb(A0),A0
+	asl.l #5,D0              // * 32
+	add.l A0,D0
+#if DEBUG_BIOS_LAYER
+	move.l D0,-(SP)
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l (SP),D0
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	lea debug4(PC),A0
+	jsr display_string
+	move.l (SP)+,D0
+#endif
+	move.l (SP)+,D1
+	move.l (SP)+,A0
+	rts
+
+det_hdv_rw_usb:
+
+	lea -28(SP),SP
+	movem.l D1-D4/A0-A2,(SP)
+#if DEBUG_BIOS_LAYER
+	lea debug3(PC),A0
+	jsr display_string	
+	move.w 4+28(SP),D0       // rwflag
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l 6+28(SP),D0       // buffer
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 10+28(SP),D0      // num sectors
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 12+28(SP),D0      // logical sector
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 16+28(SP),D0      // Galvez: logical sector (lrecno)
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 14+28(SP),D0      // drive
+	jsr hex_word
+	moveq #13,D0
+	jsr display_char
+	moveq #10,D0
+	jsr display_char
+#endif
+	btst #3,5+28(SP)         // rwflag
+	bne.s .dhru8             // physical
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 14+28(SP),D0      // drive
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .dhru8
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .dhru8
+	moveq #0,D4
+	move.b pinfo_pun(A0,D0.l),D4
+	bpl.s .dhru1             // valid
+.dhru8:
+	movem.l (SP),D1-D4/A0-A2
+	lea 28(SP),SP
+	moveq #0,D0
+	move.l old_hdv_rw_usb,-(SP)
+	rts
+.dhru1:
+	move.l D4,D2
+	and.l #PUN_USB,D2
+	beq.s .dhru8             // not USB
+	and.l #PUN_DEV,D4
+	moveq #0,D2
+	move.w 12+28(SP),D2      // logical sector
+	cmp.w #0xffff,D2         // Galvez: check recno <> -1
+	bne.s .dhru6		
+	move.l 16+28(SP),D2      // logical sector
+.dhru6:
+	tst.l D2
+	bmi .dhru2               // negative logical sector
+	move.l 6+28(SP),D1       // buffer
+	beq .dhru4               // no buffer
+	move.l pinfo_pstart(A0,D0.l*4),D3
+	move.l pinfo_devnum(A0,D0.l),D4	 // devnum in the USB bus
+	lea pinfo_bpb(A0),A0
+	asl.l #5,D0              // * 32
+	add.l D0,A0
+	move.w 14(A0),D0         // total clusters
+	mulu.w 2(A0),D0          // cluster size in sectors
+	cmp.l D0,D2              // logical sector to hight
+	bcc .dhru2
+	moveq #0,D0
+	move.w (A0),D0           // sector size
+	lsr.l #8,D0
+	lsr.l #1,D0              // / 512
+	move.l D1,A0             // buffer
+	move.w 10+28(SP),D1      // num sectors
+	beq .dhru4               // no sectors
+	mulu D0,D1
+	mulu.l D0,D2
+	add.l D3,D2              // start sector
+	move.l D1,D3             // count
+	btst #0,5+28(SP)         // rwflag
+	beq.s .dhru7             // read
+	// write
+	tst.l D2                 // logical sector
+	beq.s .dhru2             // root sector
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,-(SP)          // USB devnum 
+	jsr _usb_stor_write
+	bra.s .dhru5
+.dhru2:
+	moveq #-1,D0             // error
+	bra.s .dhru3
+.dhru4:
+	moveq #0,D0              // OK
+	bra.s .dhru3
+.dhru7:
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,-(SP)          // USB devnum
+	jsr _usb_stor_read
+.dhru5:
+	lea 16(SP),SP
+	tst.l D0
+	seq.b D0
+	ext.w D0
+	ext.l D0
+	bclr #0,D0               // OK or device not responding -2
+.dhru3:
+	movem.l (SP),D1-D4/A0-A2
+	lea 28(SP),SP
+ 	rts
+
+det_hdv_mediach_usb:
+
+	move.l A0,-(SP)
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 4+4(SP),D0        // drive
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .dhmu2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .dhmu2
+	tst.b pinfo_pun(A0,D0.l)
+	bpl.s .dhmu1
+.dhmu2:
+	move.l (SP)+,A0
+	moveq #0,D0
+	move.l old_hdv_mediach_usb,-(SP)
+	rts
+.dhmu1:
+#if 0 // #if DEBUG_BIOS_LAYER
+	move.l A0,-(SP)
+	lea debug5(PC),A0
+	jsr display_string
+	move.l (SP)+,A0
+#endif
+	lea pinfo_flags(A0),A0
+	add.l D0,A0
+	add.l D0,A0
+	bclr #7,1(A0)
+	sne.b D0
+	and.l #2,D0
+	move.l (SP)+,A0
+	rts
+
+	// XHDI
+	
+	dc.l 0x27011992
+	
+xhdi:
+	link A6,#0
+	movem.l D1-A5,-(SP)
+	moveq #0,D1
+	move.w 8(A6),D1
+
+	move.w D1,D0
+#if DEBUG_BIOS_LAYER	
+	move.w D0, -(SP)
+	jsr hex_word		/* Galvez: DEBUG. XHDI function */
+	move.w (SP)+,D0
+#endif	
+	moveq #-32,D0            // invalid function
+	cmp.l #18,d1
+	bcc.s .bad_xhdi
+	move.w SR,D0             // supervisor only
+	moveq #-1,d0             // error
+	move.w tab_xhdi(PC,D1.l*2),D1
+	jsr tab_xhdi(PC,D1.W)
+	
+.bad_xhdi:
+	movem.l (SP)+,D1-A5
+	unlk A6
+	rts
+#if DEBUG_BIOS_LAYER
+debug:
+	lea debug138(PC),A0
+	jsr display_string
+	rts
+#endif
+	
+tab_xhdi:
+	dc.w XHGetVersion-tab_xhdi    // 0
+	dc.w XHInqTarget-tab_xhdi     // 1
+	dc.w XHReserve-tab_xhdi       // 2
+	dc.w XHLock-tab_xhdi          // 3
+	dc.w XHStop-tab_xhdi          // 4
+	dc.w XHEject-tab_xhdi         // 5
+	dc.w XHDrvMap-tab_xhdi        // 6
+	dc.w XHInqDev-tab_xhdi        // 7
+	dc.w XHInqDriver-tab_xhdi     // 8
+	dc.w XHNewCookie-tab_xhdi     // 9
+	dc.w XHReadWrite-tab_xhdi     // 10
+	dc.w XHInqTarget2-tab_xhdi    // 11
+	dc.w XHInqDev2-tab_xhdi       // 12
+	dc.w XHDriverSpecial-tab_xhdi // 13
+	dc.w XHGetCapacity-tab_xhdi   // 14
+	dc.w XHMediumChanged-tab_xhdi // 15
+	dc.w XHMiNTInfo-tab_xhdi      // 16
+	dc.w XHDOSLimits-tab_xhdi     // 17
+	
+XHGetVersion:
+#if DEBUG_BIOS_LAYER
+	move.l A0,-(SP)
+	lea debug138(PC),A0
+	jsr display_string
+	move.l (SP)+,A0
+#endif
+	move.l #0x120,D0         //  protocol version
+	move.l old_xhdi_version,D1
+	cmp.l D1,D0
+	bcs.s .xv1
+	move.l D1,D0             // minimum version
+.xv1:	
+	rts
+	
+XHInqTarget:
+
+	moveq #32,D2             // stringlen
+	bra.s .xi1
+	
+XHInqTarget2:
+
+#if DEBUG_BIOS_LAYER
+	move.l A0,-(SP)
+	lea debug133(PC),A0
+	jsr display_string
+	move.l (SP)+,A0
+#endif
+	move.w 26(A6),D2         // stringlen
+.xi1:
+	tst.w 12(A6)             // minor
+	bne.s .xi2
+	moveq #0,D0
+	move.w 10(A6),D0         // major
+	cmp.w #PUN_USB,D0
+	bcs.s .xi2
+	cmp.w #PUN_USB+PUN_DEV,D0
+	bls.s .xi3
+.xi2:
+	tst.l old_xhdi
+	beq.s .xi7
+	moveq #-15,D0            // unknown device
+	rts
+.xi7:
+	move.l old_xhdi,-(SP)
+	rts
+.xi3:
+	tst.l 14(A6)
+	beq.s .xi8
+	move.l 14(A6),A0
+	move.l #512,(A0)
+.xi8:
+	tst.l 18(A6)
+	beq.s .xi9
+	move.l 18(A6),A0	 // flags
+	move.l #0x00000002,(A0)  // removable
+.xi9:
+	move.l 22(A6),D1         // product_name
+	beq.s .xi6		 // no pointer
+	move.l D1,A0
+
+	and.b #PUN_DEV,D0
+	move.l product_name,A1
+	move.l (A1,D0.l*4),D0    // Galvez: D0 should be the bios drive number			
+	beq.s .xi6               // no pointer
+	move.l D0,A1
+.xi5:
+	move.b (A1)+,(A0)+
+	beq.s .xi4
+	subq.w #1,D2
+	bpl.s .xi5		// Galvez: test
+.xi4:
+	clr.b -1(A0)
+.xi6:
+	moveq #0,D0
+	rts
+
+XHReserve:
+XHLock:
+XHStop:
+XHEject:
+
+	tst.l old_xhdi
+	beq.s .xnu1
+	moveq #0,D0
+	rts
+.xnu1:
+	move.l old_xhdi,-(SP)
+	rts
+	
+XHDrvMap:
+
+	move.l _drvbits,D0
+	rts
+
+XHInqDev:
+
+#if DEBUG_BIOS_LAYER
+	lea debug134(PC),A0
+	jsr display_string
+#endif
+	
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 10(A6),D0         // bios_device
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .xd2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .xd2
+	moveq #0,D1
+	move.b pinfo_pun(A0,D0.l),D1
+	bpl.s .xd1
+.xd2:	
+
+	tst.l old_xhdi
+	beq.s .xd3
+	moveq #-46,D0            // invalid drive number
+		
+	rts
+.xd3:
+	move.l old_xhdi,-(SP)
+	rts
+.xd1:	
+	move.l D1,D2
+	and.l #PUN_USB+PUN_DEV,D2
+	beq.s .xd2
+	tst.l 12(A6)
+	beq.s .xd4
+	move.l 12(A6),A1         // major
+	move.w D1,(A1)
+.xd4:
+	tst.l 16(A6)
+	beq.s .xd5
+	move.l 16(A6),A1         // minor
+	clr.w (A1)
+.xd5:
+	tst.l 20(A6)
+	beq.s .xd6
+	move.l pinfo_pstart(A0,D0.l*4),D1
+	move.l 20(A6),A1         // start_sector
+	move.l D1,(A1)
+.xd6:
+	lea pinfo_bpb(A0),A0
+	asl.l #5,D0              // * 32
+	add.l A0,D0
+	tst.l 24(A6)
+	beq.s .xd7
+	move.l 24(A6),A1         // bpb
+	move.l D0,(A1)
+.xd7:
+	moveq #0,D0
+	rts
+
+XHInqDriver:
+
+#if DEBUG_BIOS_LAYER
+	lea debug135(PC),A0
+	jsr display_string
+#endif	
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 10(A6),D0         // bios_device
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .xdr2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .xdr2
+	moveq #0,D1
+	move.b pinfo_pun(A0,D0.l),D1
+	bpl.s .xdr1
+.xdr2:	
+	tst.l old_xhdi
+	beq.s .xdr8
+	moveq #-46,D0            // invalid drive number
+	rts
+.xdr8:
+	move.l old_xhdi,-(SP)
+	rts
+.xdr1:
+	move.l D1,D0
+	and.l #PUN_USB,D0
+	beq.s .xdr2
+	move.l 12(A6),D0         // name, 17 characters
+	beq.s .xdr3
+	move.l D0,A1
+	lea message1(PC),A0
+	moveq #17,D1
+.xdr6:
+	move.b (A0)+,D0
+	beq.s .xdr7
+	move.b D0,(A1)+
+	subq.l #1,D1
+	bpl.s .xdr6
+.xdr7:
+	clr.b (A1)
+.xdr3:
+	move.l 16(A6),D0         // version, 7 characters
+	beq.s .xdr4
+	move.l D0,A1
+	move.b #0x34,(A1)+       // ??? TOS 4.04
+	move.b #0x2E,(A1)+
+	move.b #0x30,(A1)+
+	move.b #0x34,(A1)+
+	clr.b (A1)
+.xdr4:
+	move.l 20(A6),D0         // company, 17 characters
+	beq.s .xdr5
+	move.l D0,A1
+	clr.b (A1)
+.xdr5:
+	move.l 24(A6),A1         // ahdi_version
+	move.w pinfo_vernum(A0),(A1)
+	move.l 28(A6),A1         // maxIPL
+	moveq #5,D0
+	move.w D0,(A1)	
+	moveq #0,D0
+	rts
+
+XHReadWrite:                      // read / write physical sectors
+#if DEBUG_BIOS_LAYER
+	lea debug139(PC),A0
+	jsr display_string
+#endif	
+
+	tst.w 12(A6)             // minor
+	bne.s .xr4
+	moveq #0,D4
+	move.w 10(A6),D4         // major
+	cmp.l #PUN_USB,D4
+	bcs.s .xr4
+	cmp.l #PUN_USB+PUN_DEV,D4
+	bls.s .xr1
+.xr4:
+	tst.l old_xhdi
+	beq.s .xr6
+	moveq #-15,D0            // unknown device
+	rts
+.xr6:
+	move.l old_xhdi,-(SP)
+	rts
+.xr1:
+#if DEBUG_BIOS_LAYER
+	lea debug132(PC),A0
+	jsr display_string
+	move.w 14(A6),D0         // rwflag
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l 24(A6),D0         // buffer
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 20(A6),D0         // num sectors
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l 16(A6),D0         // logical sector
+	jsr hex_long
+	moveq #13,D0
+	jsr display_char
+	moveq #10,D0
+	jsr display_char	
+#endif
+	move.l 22(A6),A0         // buffer
+	moveq #0,D3
+	move.w 20(A6),D3         // count
+	beq .xr2                 // no sectors
+        move.l 16(A6),D2         // start sector
+	btst #0,15(A6)           // rwflag
+	beq.s .xr7               // read
+	// write
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,D0             // major
+	and.l #PUN_DEV,D0
+	move.l pun_ptr,A0	
+	move.b pinfo_devnum(A0,D0.l),D0 // devnum in the USB bus
+	move.l D0,-(SP)          // USB devnum
+	jsr _usb_stor_write
+	bra.s .xr5
+.xr2:
+	moveq #-1,D0             // error
+	bra.s .xr3
+.xr7:
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,D0             // major
+	and.l #PUN_DEV,D0
+	move.l pun_ptr,A0	
+	move.b pinfo_devnum(A0,D0.l),D0 // devnum in the USB bus
+	move.l D0,-(SP)          // USB devnum
+	jsr _usb_stor_read
+.xr5:
+	lea 16(SP),SP
+	tst.l D0
+	seq.b D0
+	ext.w D0
+	ext.l D0
+	bclr #0,D0               // OK or device not responding -2
+.xr3:
+ 	rts
+
+XHInqDev2:
+
+#if DEBUG_BIOS_LAYER
+	lea debug136(PC),A0
+	jsr display_string	// Galvez: changed bsr by jsr to avoid linker error
+#endif
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 10(A6),D0         // bios_device
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .xdd2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .xdd2
+	moveq #0,D1
+	move.b pinfo_pun(A0,D0.l),D1
+	bpl.s .xdd1
+.xdd2:	
+	tst.l old_xhdi
+	beq.s .xdd4
+	moveq #-46,D0            // invalid drive number
+	rts
+.xdd4:
+	move.l old_xhdi,-(SP)
+	rts
+.xdd1:	
+	move.w D1,D2
+	and.b #PUN_USB+PUN_DEV,D2
+	beq.s .xdd2
+	tst.l 12(A6)
+	beq.s .xdd5
+	move.l 12(A6),A1         // major
+	move.w D2,(A1)
+.xdd5:
+	tst.l 16(A6)
+	beq.s .xdd6
+	move.l 16(A6),A1         // minor
+	clr.w (A1)
+.xdd6:
+	tst.l 20(A6)
+	beq.s .xdd7
+	move.l pinfo_pstart(A0,D0.l*4),D1
+	move.l 20(A6),A1         // start_sector
+	move.l D1,(A1)
+.xdd7:
+	tst.l 24(A6)
+	beq.s .xdd8
+	lea pinfo_bpb(A0),A2
+	move.l D0,D1
+	asl.l #5,D1              // * 32
+	add.l A2,D1
+	move.l 24(A6),A1         // bpb
+	move.l D1,(A1)
+.xdd8:
+	tst.l 28(A6)
+	beq.s .xdd9
+	move.l 28(A6),A1         // blocks
+	lea pinfo_psize(A0),A2
+	move.l (A2,D0.l*4),(A1)
+.xdd9:
+	tst.l 32(A6)
+	beq.s .xdd10
+	move.l 32(A6),A1         // partid
+	clr.l (A1)
+	move.b pinfo_ptype+3(A0,D0.l*4),D1   
+	move.w #0x0044,(A1)          		// NULL+ 'D'
+	move.b D1,2(A1)
+.xdd10:
+	moveq #0,D0
+	rts
+ 
+XHDriverSpecial:
+XHGetCapacity:
+XHMediumChanged:
+XHMiNTInfo:
+XHNewCookie:
+
+	tst.l old_xhdi
+	beq.s .xn1
+	moveq #-32,D0            //  invalid function number 
+	rts
+.xn1:
+	move.l old_xhdi,-(SP)
+	rts
+
+XHDOSLimits:
+
+	tst.l old_xhdi
+	bne.s .xn1
+#if DEBUG_BIOS_LAYER
+	lea debug137(PC),A0
+	jsr display_string
+#endif
+	moveq #0,D0
+	move.w 10(A6),D0         // which
+	cmp.l #XH_DL_SECSIZ,D0   // maximal sector size (BIOS level)
+	bne.s .xl1
+	move.l #0x4000,D0
+	rts	
+.xl1:
+	cmp.l #XH_DL_MINFAT,D0   // minimal number of FATs
+	bne.s .xl2
+	moveq #1,D0
+	rts
+.xl2:
+	cmp.l #XH_DL_MAXFAT,D0   // maximal number of FATs
+	bne.s .xl3
+	moveq #2,D0
+	rts
+.xl3:
+	cmp.l #XH_DL_MINSPC,D0   // sectors per cluster minimal
+	bne.s .xl4
+	moveq #2,D0
+	rts
+.xl4:
+	cmp.l #XH_DL_MAXSPC,D0   // sectors per cluster maximal
+	bne.s .xl5
+#ifdef COLDFIRE
+	moveq #64,D0             // for this Coldfire version of BDOS, else 2
+#else
+	moveq #2,D0
+#endif
+	rts
+.xl5:
+	cmp.l #XH_DL_CLUSTS,D0   // maximal number of clusters of a 16 bit FAT
+	bne.s .xl6
+	move.l #0x8000,D0
+	rts	
+.xl6:
+	cmp.l #XH_DL_MAXSEC,D0   // maximal number of sectors
+	bne.S .xl7
+#ifdef COLDFIRE
+	move.l #0x200000,D0      // for this Coldfire version of BDOS, else 0x10000
+#else
+	move.l #0x10000,D0
+#endif
+	rts
+.xl7:
+	cmp.l #XH_DL_DRIVES,D0   // maximal number of BIOS drives supported by the DOS
+	bne.s .xl8
+	moveq #16,D0
+	rts
+.xl8:
+	moveq #-32,D0            // invalid function number 
+	rts
+
+	
+
+
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */
+
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \
+	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+message1:	.ascii "TOS4.04 "
+message2:	.asciz "USB  "
+message2b:	.asciz ", disk installed in "
+#endif
+#endif
+
+crlf:	.byte 13,10,0
+error:	.asciz "No ram-disk installed, "
+error1:	.ascii "no enough radeon memory"
+	.byte 13,10,0
+error2:	.ascii "all drives already used"
+	.byte 13,10,0
+error3:	.ascii "error disk name"
+	.byte 13,10,0
+error4:	.ascii "partition type not supported"
+	.byte 13,10,0
+blue:	.byte 0x1B,0x62,0x34,0
+black:	.byte 0x1B,0x62,0x3F,0
+
+	.align 2
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) \
+	|| defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+
+	.lcomm pun_ptr_usb,4
+	.lcomm user_sp,4
+
+	.lcomm _usb_1st_disk_drive,4
+	.lcomm old_hdv_bpb_usb,4
+	.lcomm old_hdv_rw_usb,4
+	.lcomm old_hdv_mediach_usb,4
+	.lcomm old_xhdi,4
+	.lcomm old_xhdi_version,4
+	.lcomm product_name,4*(PUN_DEV+1)
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */
+
+
diff --git a/usb/store/cmd_usb.c b/usb/store/cmd_usb.c
new file mode 100644
index 0000000..9c6b3da
--- /dev/null
+++ b/usb/store/cmd_usb.c
@@ -0,0 +1,731 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * Most of this source has been derived from the Linux USB
+ * project.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ 
+
+#include "config.h"
+#include "asm-m68k/byteorder.h"
+#include "usb.h"
+
+
+//#undef RESET_START_STOP_CMDS
+//#define RESET_START_STOP_CMDS
+
+#ifdef CONFIG_USB_STORAGE
+static int usb_stor_curr_dev = -1; /* current device */
+#endif
+
+#ifdef PCI_XBIOS
+extern short pci_init(void);
+#endif
+
+/* some display routines (info command) */
+char *usb_get_class_desc(unsigned char dclass)
+{
+	switch (dclass) {
+	case USB_CLASS_PER_INTERFACE:
+		return "See Interface";
+	case USB_CLASS_AUDIO:
+		return "Audio";
+	case USB_CLASS_COMM:
+		return "Communication";
+	case USB_CLASS_HID:
+		return "Human Interface";
+	case USB_CLASS_PRINTER:
+		return "Printer";
+	case USB_CLASS_MASS_STORAGE:
+		return "Mass Storage";
+	case USB_CLASS_HUB:
+		return "Hub";
+	case USB_CLASS_DATA:
+		return "CDC Data";
+	case USB_CLASS_VENDOR_SPEC:
+		return "Vendor specific";
+	default:
+		return "";
+	}
+}
+
+void usb_display_class_sub(unsigned char dclass, unsigned char subclass,
+			   unsigned char proto)
+{
+	switch (dclass) {
+	case USB_CLASS_PER_INTERFACE:
+		printf("See Interface");
+		break;
+	case USB_CLASS_HID:
+		printf("Human Interface, Subclass: ");
+		switch (subclass) {
+		case USB_SUB_HID_NONE:
+			printf("None");
+			break;
+		case USB_SUB_HID_BOOT:
+			printf("Boot ");
+			switch (proto) {
+			case USB_PROT_HID_NONE:
+				printf("None");
+				break;
+			case USB_PROT_HID_KEYBOARD:
+				printf("Keyboard");
+				break;
+			case USB_PROT_HID_MOUSE:
+				printf("Mouse");
+				break;
+			default:
+				printf("reserved");
+				break;
+			}
+			break;
+		default:
+			printf("reserved");
+			break;
+		}
+		break;
+	case USB_CLASS_MASS_STORAGE:
+		printf("Mass Storage, ");
+		switch (subclass) {
+		case US_SC_RBC:
+			printf("RBC ");
+			break;
+		case US_SC_8020:
+			printf("SFF-8020i (ATAPI)");
+			break;
+		case US_SC_QIC:
+			printf("QIC-157 (Tape)");
+			break;
+		case US_SC_UFI:
+			printf("UFI");
+			break;
+		case US_SC_8070:
+			printf("SFF-8070");
+			break;
+		case US_SC_SCSI:
+			printf("Transp. SCSI");
+			break;
+		default:
+			printf("reserved");
+			break;
+		}
+		printf(", ");
+		switch (proto) {
+		case US_PR_CB:
+			printf("Command/Bulk");
+			break;
+		case US_PR_CBI:
+			printf("Command/Bulk/Int");
+			break;
+		case US_PR_BULK:
+			printf("Bulk only");
+			break;
+		default:
+			printf("reserved");
+			break;
+		}
+		break;
+	default:
+		printf("%s", usb_get_class_desc(dclass));
+		break;
+	}
+}
+
+void usb_display_string(struct usb_device *dev, int idx)
+{
+	char buffer[256];
+	if (idx != 0) {
+		if (usb_string(dev, idx, &buffer[0], 256) > 0)
+			printf("String: \"%s\"", buffer);
+	}
+}
+
+void usb_display_desc(struct usb_device *dev)
+{
+	if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) {
+		printf("%d: %s,  USB Revision %x.%x\n", dev->devnum,
+		usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass),
+				   (dev->descriptor.bcdUSB>>8) & 0xff,
+				   dev->descriptor.bcdUSB & 0xff);
+
+		if (strlen(dev->mf) || strlen(dev->prod) ||
+		    strlen(dev->serial))
+			printf(" - %s %s %s\n", dev->mf, dev->prod,
+				dev->serial);
+		if (dev->descriptor.bDeviceClass) {
+			printf(" - Class: ");
+			usb_display_class_sub(dev->descriptor.bDeviceClass,
+					      dev->descriptor.bDeviceSubClass,
+					      dev->descriptor.bDeviceProtocol);
+			printf("\n");
+		} else {
+			printf(" - Class: (from Interface) %s\n",
+			       usb_get_class_desc(
+				dev->config.if_desc[0].bInterfaceClass));
+		}
+		printf(" - PacketSize: %d  Configurations: %d\n",
+			dev->descriptor.bMaxPacketSize0,
+			dev->descriptor.bNumConfigurations);
+		printf(" - Vendor: 0x%04x  Product 0x%04x Version %d.%d\n",
+			dev->descriptor.idVendor, dev->descriptor.idProduct,
+			(dev->descriptor.bcdDevice>>8) & 0xff,
+			dev->descriptor.bcdDevice & 0xff);
+	}
+
+}
+
+void usb_display_conf_desc(struct usb_config_descriptor *config,
+			   struct usb_device *dev)
+{
+	printf("   Configuration: %d\n", config->bConfigurationValue);
+	printf("   - Interfaces: %d %s%s%dmA\n", config->bNumInterfaces,
+	       (config->bmAttributes & 0x40) ? "Self Powered " : "Bus Powered ",
+	       (config->bmAttributes & 0x20) ? "Remote Wakeup " : "",
+		config->MaxPower*2);
+	if (config->iConfiguration) {
+		printf("   - ");
+		usb_display_string(dev, config->iConfiguration);
+		printf("\n");
+	}
+}
+
+void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,
+			 struct usb_device *dev)
+{
+	printf("     Interface: %d\n", ifdesc->bInterfaceNumber);
+	printf("     - Alternate Setting %d, Endpoints: %d\n",
+		ifdesc->bAlternateSetting, ifdesc->bNumEndpoints);
+	printf("     - Class ");
+	usb_display_class_sub(ifdesc->bInterfaceClass,
+		ifdesc->bInterfaceSubClass, ifdesc->bInterfaceProtocol);
+	printf("\n");
+	if (ifdesc->iInterface) {
+		printf("     - ");
+		usb_display_string(dev, ifdesc->iInterface);
+		printf("\n");
+	}
+}
+
+void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc)
+{
+	printf("     - Endpoint %d %s ", epdesc->bEndpointAddress & 0xf,
+		(epdesc->bEndpointAddress & 0x80) ? "In" : "Out");
+	switch ((epdesc->bmAttributes & 0x03)) {
+	case 0:
+		printf("Control");
+		break;
+	case 1:
+		printf("Isochronous");
+		break;
+	case 2:
+		printf("Bulk");
+		break;
+	case 3:
+		printf("Interrupt");
+		break;
+	}
+	printf(" MaxPacket %d", epdesc->wMaxPacketSize);
+	if ((epdesc->bmAttributes & 0x03) == 0x3)
+		printf(" Interval %dms", epdesc->bInterval);
+	printf("\n");
+}
+
+/* main routine to diasplay the configs, interfaces and endpoints */
+void usb_display_config(struct usb_device *dev)
+{
+	struct usb_config_descriptor *config;
+	struct usb_interface_descriptor *ifdesc;
+	struct usb_endpoint_descriptor *epdesc;
+	int i, ii;
+
+	config = &dev->config;
+	usb_display_conf_desc(config, dev);
+	for (i = 0; i < config->no_of_if; i++) {
+		ifdesc = &config->if_desc[i];
+		usb_display_if_desc(ifdesc, dev);
+		for (ii = 0; ii < ifdesc->no_of_ep; ii++) {
+			epdesc = &ifdesc->ep_desc[ii];
+			usb_display_ep_desc(epdesc);
+		}
+	}
+	printf("\n");
+}
+
+static inline char *portspeed(int speed)
+{
+	if (speed == USB_SPEED_HIGH)
+		return "480 Mb/s";
+	else if (speed == USB_SPEED_LOW)
+		return "1.5 Mb/s";
+	else
+		return "12 Mb/s";
+}
+
+/* shows the device tree recursively */
+void usb_show_tree_graph(struct usb_device *dev, char *pre)
+{
+	int i, idx;
+	int has_child, last_child, port;
+
+	idx = strlen(pre);
+	printf(" %s", pre);
+	/* check if the device has connected children */
+	has_child = 0;
+	for (i = 0; i < dev->maxchild; i++) {
+		if (dev->children[i] != NULL)
+			has_child = 1;
+	}
+	/* check if we are the last one */
+	last_child = 1;
+	if (dev->parent != NULL) {
+		for (i = 0; i < dev->parent->maxchild; i++) {
+			/* search for children */
+			if (dev->parent->children[i] == dev) {
+				/* found our pointer, see if we have a
+				 * little sister
+				 */
+				port = i;
+				while (i++ < dev->parent->maxchild) {
+					if (dev->parent->children[i] != NULL) {
+						/* found a sister */
+						last_child = 0;
+						break;
+					} /* if */
+				} /* while */
+			} /* device found */
+		} /* for all children of the parent */
+		printf("\b+-");
+		/* correct last child */
+		if (last_child)
+			pre[idx-1] = ' ';
+	} /* if not root hub */
+	else
+		printf(" ");
+	printf("%d ", dev->devnum);
+	pre[idx++] = ' ';
+	pre[idx++] = has_child ? '|' : ' ';
+	pre[idx] = 0;
+	printf(" %s (%s, %dmA)\n", usb_get_class_desc(
+					dev->config.if_desc[0].bInterfaceClass),
+					portspeed(dev->speed),
+					dev->config.MaxPower * 2);
+	if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial))
+		printf(" %s  %s %s %s\n", pre, dev->mf, dev->prod, dev->serial);
+	printf(" %s\n", pre);
+	if (dev->maxchild > 0) {
+		for (i = 0; i < dev->maxchild; i++) {
+			if (dev->children[i] != NULL) {
+				usb_show_tree_graph(dev->children[i], pre);
+				pre[idx] = 0;
+			}
+		}
+	}
+}
+
+/* main routine for the tree command */
+void usb_show_tree(struct usb_device *dev)
+{
+	char preamble[32];
+
+	memset(preamble, 0, 32);
+	usb_show_tree_graph(dev, &preamble[0]);
+}
+
+
+/******************************************************************************
+ * usb boot command intepreter. Derived from diskboot
+ */
+#if 0
+#ifdef CONFIG_USB_STORAGE
+int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char *boot_device = NULL;
+	char *ep;
+	int dev, part = 1, rcode;
+	ulong addr, cnt;
+	disk_partition_t info;
+	image_header_t *hdr;
+	block_dev_desc_t *stor_dev;
+#if defined(CONFIG_FIT)
+	const void *fit_hdr = NULL;
+#endif
+
+	switch (argc) {
+	case 1:
+		addr = CONFIG_SYS_LOAD_ADDR;
+		boot_device = getenv("bootdevice");
+		break;
+	case 2:
+		addr = strtoul(argv[1], NULL, 16);
+		boot_device = getenv("bootdevice");
+		break;
+	case 3:
+		addr = strtoul(argv[1], NULL, 16);
+		boot_device = argv[2];
+		break;
+	default:
+//		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if (!boot_device) {
+		puts("\n** No boot device **\n");
+		return 1;
+	}
+
+	dev = strtoul(boot_device, &ep, 16);
+	stor_dev = usb_stor_get_dev(dev);
+	if (stor_dev->type == DEV_TYPE_UNKNOWN) {
+		printf("\n** Device %d not available\n", dev);
+		return 1;
+	}
+	if (stor_dev->block_read == NULL) {
+		printf("storage device not initialized. Use usb scan\n");
+		return 1;
+	}
+	if (*ep) {
+		if (*ep != ':') {
+			puts("\n** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
+		}
+		part = strtoul(++ep, NULL, 16);
+	}
+
+	if (get_partition_info(stor_dev, part, &info)) {
+		/* try to boot raw .... */
+		strncpy((char *)&info.type[0], BOOT_PART_TYPE,
+			sizeof(BOOT_PART_TYPE));
+		strncpy((char *)&info.name[0], "Raw", 4);
+		info.start = 0;
+		info.blksz = 0x200;
+		info.size = 2880;
+		printf("error reading partinfo...try to boot raw\n");
+	}
+	if ((strncmp((char *)info.type, BOOT_PART_TYPE,
+	    sizeof(info.type)) != 0) &&
+	    (strncmp((char *)info.type, BOOT_PART_COMP,
+	    sizeof(info.type)) != 0)) {
+		printf("\n** Invalid partition type \"%.32s\""
+			" (expect \"" BOOT_PART_TYPE "\")\n",
+			info.type);
+		return 1;
+	}
+	printf("\nLoading from USB device %d, partition %d: "
+		"Name: %.32s  Type: %.32s\n",
+		dev, part, info.name, info.type);
+
+	debug("First Block: %ld,  # of blocks: %ld, Block Size: %ld\n",
+		info.start, info.size, info.blksz);
+
+	if (stor_dev->block_read(dev, info.start, 1, (ulong *)addr) != 1) {
+		printf("** Read error on %d:%d\n", dev, part);
+		return 1;
+	}
+
+	switch (genimg_get_format((void *)addr)) {
+	case IMAGE_FORMAT_LEGACY:
+//		hdr = (image_header_t *)addr;
+
+//		if (!image_check_hcrc(hdr)) {
+//			puts("\n** Bad Header Checksum **\n");
+			return 1;
+		}
+
+//		image_print_contents(hdr);
+
+//		cnt = image_get_image_size(hdr);
+		break;
+#if defined(CONFIG_FIT)
+	case IMAGE_FORMAT_FIT:
+		fit_hdr = (const void *)addr;
+		puts("Fit image detected...\n");
+
+		cnt = fit_get_size(fit_hdr);
+		break;
+#endif
+	default:
+		puts("** Unknown image type\n");
+		return 1;
+	}
+
+	cnt += info.blksz - 1;
+	cnt /= info.blksz;
+	cnt -= 1;
+
+	if (stor_dev->block_read(dev, info.start+1, cnt,
+		      (ulong *)(addr+info.blksz)) != cnt) {
+		printf("\n** Read error on %d:%d\n", dev, part);
+		return 1;
+	}
+
+#if defined(CONFIG_FIT)
+	/* This cannot be done earlier, we need complete FIT image in RAM
+	 * first
+	 */
+	if (genimg_get_format((void *)addr) == IMAGE_FORMAT_FIT) {
+		if (!fit_check_format(fit_hdr)) {
+			puts("** Bad FIT image format\n");
+			return 1;
+		}
+		fit_print_contents(fit_hdr);
+	}
+#endif
+
+	/* Loading ok, update default load address */
+	load_addr = addr;
+
+	flush_cache(addr, (cnt+1)*info.blksz);
+
+	/* Check if we should attempt an auto-start */
+	if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
+		char *local_args[2];
+		extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		printf("Automatic boot of image at addr 0x%08lX ...\n", addr);
+		rcode = do_bootm(cmdtp, 0, 1, local_args);
+		return rcode;
+	}
+	return 0;
+}
+#endif
+#endif /* CONFIG_USB_STORAGE */
+
+
+/******************************************************************************
+ * usb command intepreter
+ */
+int do_usb(int argc, char **argv)
+{
+
+	int i;
+	struct usb_device *dev = NULL;
+	
+#ifdef CONFIG_USB_STORAGE
+	block_dev_desc_t *stor_dev;
+#endif
+	extern char usb_started;
+
+	if ((strncmp(argv[1], "reset", 5) == 0) ||
+		 (strncmp(argv[1], "start", 5) == 0)) {
+		usb_stop();
+		printf("(Re)start USB...\n");
+#ifdef PCI_XBIOS
+		i = pci_init();
+#else
+		if (usb_init() >= 0)
+			i = 1;
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+		/* try to recognize storage devices immediately */
+		if (i == 1)
+			usb_stor_curr_dev = usb_stor_scan( );
+#endif
+		return 0;
+	}
+	if (strncmp(argv[1], "stop", 4) == 0) {
+#ifdef CONFIG_USB_KEYBOARD
+		if (argc == 2) {
+			if (usb_kbd_deregister() != 0) {
+				printf("USB not stopped: usbkbd still"
+					" using USB\n");
+				return 1;
+			}
+		} else {
+			/* forced stop, switch console in to serial */
+			usb_kbd_deregister();
+		}
+#endif
+		printf("stopping USB..\n");
+		usb_stop();
+		return 0;
+	}
+	if (!usb_started) {
+		printf("USB is stopped. Please issue 'usb start' first.\n");
+		return 1;
+	}
+
+	if (strncmp(argv[1], "tree", 4) == 0) {
+		printf("\nDevice Tree:\n");
+		usb_show_tree(usb_get_dev_index(0));
+		return 0;
+	}
+	if (strncmp(argv[1], "inf", 3) == 0)
+	{
+		int d1;
+		if (argc == 2) 
+		{
+			for (d1 = 0; d1 < USB_MAX_DEVICE; d1++) {
+				dev = usb_get_dev_index(d1);
+				if (dev == NULL)
+					break;
+				usb_display_desc(dev);
+				usb_display_config(dev);
+			}
+			return 0;
+		} else 
+		{
+			int d2;
+			
+			i = strtoul(argv[2], NULL, 16);
+			printf("config for device %d\n", i);
+			for (d2 = 0; d2 < USB_MAX_DEVICE; d2++) {
+				dev = usb_get_dev_index(d2);
+				if (dev == NULL)
+					break;
+				if (dev->devnum == i)
+					break;
+			}
+			if (dev == NULL) {
+				printf("*** NO Device avaiable ***\n");
+				return 0;
+			} else {
+				usb_display_desc(dev);
+				usb_display_config(dev);
+			}
+		}
+		return 0;
+	}
+#ifdef CONFIG_USB_STORAGE
+	if (strncmp(argv[1], "stor", 4) == 0)
+		return usb_stor_info();
+#if 0
+	if (strncmp(argv[1], "part", 4) == 0) {
+		int devno, ok = 0;
+		if (argc == 2) {
+			for (devno = 0; devno < USB_MAX_STOR_DEV; ++devno) {
+				stor_dev = usb_stor_get_dev(devno);
+				if (stor_dev->type != DEV_TYPE_UNKNOWN) {
+					ok++;
+					if (devno)
+						printf("\n");
+					printf("print_part of %x\n", devno);
+					print_part(stor_dev);
+				}
+			}
+		} else {
+			devno = strtoul(argv[2], NULL, 16);
+			stor_dev = usb_stor_get_dev(devno);
+			if (stor_dev->type != DEV_TYPE_UNKNOWN) {
+				ok++;
+				printf("print_part of %x\n", devno);
+				print_part(stor_dev);
+			}
+		}
+		if (!ok) {
+			printf("\nno USB devices available\n");
+			return 1;
+		}
+		return 0;
+	}
+#endif
+	if (strcmp(argv[1], "read") == 0) {
+		if (usb_stor_curr_dev < 0) {
+			printf("no current device selected\n");
+			return 1;
+		}
+		if (argc == 5) {
+			unsigned long addr = strtoul(argv[2], NULL, 16);
+			unsigned long blk  = strtoul(argv[3], NULL, 16);
+			unsigned long cnt  = strtoul(argv[4], NULL, 16);
+			unsigned long n;
+			printf("\nUSB read: device %d block # %ld, count %ld"
+				" ... ", usb_stor_curr_dev, blk, cnt);
+			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt,
+						 (unsigned long *)addr);
+			printf("%ld blocks read: %s\n", n,
+				(n == cnt) ? "OK" : "ERROR");
+			if (n == cnt)
+				return 0;
+			return 1;
+		}
+	}
+	if (strncmp(argv[1], "dev", 3) == 0) {
+		if (argc == 3) {
+			int device = (int)strtoul(argv[2], NULL, 10);
+			printf("\nUSB device %d: ", device);
+			if (device >= USB_MAX_STOR_DEV) {
+				printf("unknown device\n");
+				return 1;
+			}
+			printf("\n    Device %d: ", device);
+			stor_dev = usb_stor_get_dev(device);
+			dev_print(stor_dev);
+			if (stor_dev->type == DEV_TYPE_UNKNOWN)
+				return 1;
+			usb_stor_curr_dev = device;
+			printf("... is now current device\n");
+			return 0;
+		} else {
+			printf("\nUSB device %d: ", usb_stor_curr_dev);
+			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			dev_print(stor_dev);
+			if (stor_dev->type == DEV_TYPE_UNKNOWN)
+				return 1;
+			return 0;
+		}
+		return 0;
+	}
+#endif /* CONFIG_USB_STORAGE */
+//	cmd_usage(cmdtp);
+	return 1;
+}
+#if 0
+#ifdef CONFIG_USB_STORAGE
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
+	"USB sub-system",
+	"reset - reset (rescan) USB controller\n"
+	"usb stop [f]  - stop USB [f]=force stop\n"
+	"usb tree  - show USB device tree\n"
+	"usb info [dev] - show available USB devices\n"
+	"usb storage  - show details of USB storage devices\n"
+	"usb dev [dev] - show or set current USB storage device\n"
+	"usb part [dev] - print partition table of one or all USB storage"
+	" devices\n"
+	"usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
+	"    to memory address `addr'"
+);
+
+
+U_BOOT_CMD(
+	usbboot,	3,	1,	do_usbboot,
+	"boot from USB device",
+	"loadAddr dev:part"
+);
+
+#else
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
+	"USB sub-system",
+	"reset - reset (rescan) USB controller\n"
+	"usb  tree  - show USB device tree\n"
+	"usb  info [dev] - show available USB devices"
+);
+#endif
+#endif
diff --git a/usb/store/compile.txt b/usb/store/compile.txt
new file mode 100644
index 0000000..c14b6bd
--- /dev/null
+++ b/usb/store/compile.txt
@@ -0,0 +1,6 @@
+I have used gcc 4.4.3 native version and gcc 4.4.3 cross-compiler version to
+compile these sources.
+There are 4 targets "make ethernat", "make netusbee", "make aranym", "make ohci-pci".
+If you use cross-compiler add "CROSS=yes" to the commands above.
+Before compiling "ohci-pci" target you must "make clean" if you have been compiling the other targets before.
+"make all" compiles the 4 targets.
diff --git a/usb/store/config.h b/usb/store/config.h
new file mode 100644
index 0000000..ce5464f
--- /dev/null
+++ b/usb/store/config.h
@@ -0,0 +1,54 @@
+#ifndef _CONFIG_H
+#define _CONFIG_H
+
+//#define ARCH m68k
+//#define COLDFIRE      /* Besides change one(first) .chip in detxbios.S 68060 or 5200 */
+//#define CONFIG_USB_ISP116X_HCD
+//#define SUPERVISOR
+/* Change .chip in detxbios.S 68060 or 5200 */
+
+/*----- USB -----*/
+//#define CONFIG_LEGACY_USB_INIT_SEQ
+#define CONFIG_USB_STORAGE
+//#define CONFIG_USB_KEYBOARD
+//#define CONFIG_USB_MOUSE
+//#define CONFIG_USB_INTERRUPT_POLLING
+#define CONFIG_USB_ARANYM_HCD
+/*----- ISP116x-HCD ------*/
+#define ISP116X_HCD_USE_UDELAY
+#define ISP116X_HCD_USE_EXTRA_DELAY
+//#define ISP116X_HCD_SEL15kRES
+//#define ISP116X_HCD_OC_ENABLE
+//#define ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+/*----- OHCI-HCI -----*/
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_USB_OHCI
+//#define PCI_XBIOS	/* Defined in the makefile */
+
+
+/*----- DEBUG -----*/
+/* You should activate global debug, 
+ * #define DEBUG_GLOBAL 1 to turn on 
+ * #define DEBUG_GLOBAL 0 to turn off
+ * After global debug is enable 
+ * you can activate the debug independently 
+ * in each layer where debug is possible
+ */
+
+#define DEBUG_GLOBAL 1
+#if DEBUG_GLOBAL
+/* Define only one of the three debug posibilities below */
+#define DEBUG_TO_FILE 1
+#define DEBUG_TO_ARANYM 0	/* NOTE: No arguments are passed to the printf function */
+#define DEBUG_TO_CONSOLE 0
+
+/* Define which local layer you want on */
+#define DEBUG_HOST_LAYER	0
+#define DEBUG_USB_LAYER		0
+#define DEBUG_HUB_LAYER		0
+#define DEBUG_STORAGE_LAYER	0
+#define DEBUG_XHDI_LAYER	0
+#define DEBUG_BIOS_LAYER	0	/* NOTE: Always to console */
+
+#endif
+#endif /* _CONFIG_H */
diff --git a/usb/store/debug.c b/usb/store/debug.c
new file mode 100644
index 0000000..a2a1a86
--- /dev/null
+++ b/usb/store/debug.c
@@ -0,0 +1,64 @@
+/* 
+ * debug.c
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include "config.h"
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+
+
+#if  DEBUG_TO_FILE
+static FILE *debug_handle = NULL;
+
+
+void
+debug_init(char *file)
+{
+	char filename[20] = "";
+
+	strcpy(filename, file);
+		
+	debug_handle = fopen(filename, "a");
+		
+	if (debug_handle != NULL)
+		setvbuf (debug_handle, NULL, _IONBF, 0);
+}
+
+
+void debug_exit(void)
+{
+	if (debug_handle != NULL && debug_handle != stdout)
+		fclose(debug_handle);
+	debug_handle = NULL;
+}
+
+
+void debug(char *FormatString, ...)
+{
+	va_list arg_ptr;
+
+	va_start(arg_ptr, FormatString);
+	vfprintf(debug_handle, FormatString, arg_ptr);
+	va_end(arg_ptr);
+	fflush(debug_handle);
+	
+}
+#endif
+
+
diff --git a/usb/store/debug.h b/usb/store/debug.h
new file mode 100644
index 0000000..e64b59e
--- /dev/null
+++ b/usb/store/debug.h
@@ -0,0 +1,97 @@
+/*
+ * debug.h
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _DEBUG_H
+#define _DEBUG_H
+
+#include "config.h"
+#include "host/aranym/nf_ops.h"
+
+void debug_init ( char *file);
+void debug_exit ( void );
+void debug (char *FormatString, ...);
+
+/* You should activate global debug in config.h, uncommenting the #define DEBUG line */
+/* After global debug is enable you can activate them independly in each file */ 
+
+
+#if DEBUG_GLOBAL
+#if DEBUG_TO_FILE
+#define DEBUG(fmt, args...)	debug_init("usb.log"); \
+				debug( "%s: "fmt"\n\r" , __FUNCTION__, ##args); \
+				debug_exit( )
+#endif /* DEBUG_TO_FILE */
+
+#if DEBUG_TO_ARANYM
+#define	DEBUG(fmt, args...)	nf_debug(fmt )
+#endif /* DEBUG_TO_ARANYM */
+
+#if DEBUG_TO_CONSOLE
+#define DEBUG(fmt, args...)	printf("%s: "fmt"\n\r" , __FUNCTION__, ##args)
+#endif /* DEBUG_TO_CONSOLE */
+
+/* This allows control debug messages independenly for different layers */
+#if DEBUG_HOST_LAYER
+#define DEBUG_HOST(fmt, args...)	DEBUG(fmt, ##args)
+#else
+#define DEBUG_HOST(fmt, args...)	{}
+#endif
+#if DEBUG_USB_LAYER
+#define DEBUG_USB(fmt, args...)		DEBUG(fmt, ##args)
+#else
+#define DEBUG_USB(fmt, args...)		{}
+#endif
+#if DEBUG_HUB_LAYER
+#define DEBUG_HUB(fmt, args...)		DEBUG(fmt, ##args)
+#else
+#define DEBUG_HUB(fmt, args...)		{}
+#endif
+#if DEBUG_STORAGE_LAYER
+#define DEBUG_STORAGE(fmt, args...)	DEBUG(fmt, ##args)
+#else
+#define DEBUG_STORAGE(fmt, args...)	{}
+#endif
+#if DEBUG_XHDI_LAYER
+#define DEBUG_XHDI(fmt, args...)	DEBUG(fmt, ##args)
+#else
+#define DEBUG_XHDI(fmt, args...)	{}
+#endif
+
+#else
+#define DEBUG(fmt, args...) 	{}
+#if DEBUG_HOST_LAYER
+#define DEBUG_HOST(fmt, args...)	DEBUG(fmt, ##args)
+#endif
+#define DEBUG(fmt, args...) 	{}
+#if DEBUG_USB_LAYER
+#define DEBUG_USB(fmt, args...)		DEBUG(fmt, ##args)
+#endif
+#if DEBUG_HUB_LAYER
+#define DEBUG_HUB(fmt, args...)		DEBUG(fmt, ##args)
+#endif
+#if DEBUG_STORAGE_LAYER
+#define DEBUG_STORAGE(fmt, args...)	DEBUG(fmt, ##args)
+#endif
+#if DEBUG_XHDI_LAYER
+#define DEBUG_XHDI(fmt, args...)	DEBUG(fmt, ##args)
+#endif
+
+#endif  /* DEBUG_GLOBAL */
+
+
+#endif /* _DEBUG_H */
diff --git a/usb/store/debug2.S b/usb/store/debug2.S
new file mode 100644
index 0000000..0c8dd8a
--- /dev/null
+++ b/usb/store/debug2.S
@@ -0,0 +1,840 @@
+/*  Debug the CT60
+ * 
+ * Didier Mequignon, 2003-2006, e-mail: aniplay@wanadoo.fr
+ *
+ *  This library is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU Lesser General Public
+ *  License as published by the Free Software Foundation; either
+ *  version 2.1 of the License, or (at your option) any later version.
+ *
+ *  This library is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  Lesser General Public License for more details.
+ *
+ *  You should have received a copy of the GNU Lesser General Public
+ *  License along with this library; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+	.chip 68040
+	.globl	exception
+	
+#ifdef COLDFIRE
+	.globl	null
+	
+#include "fire.h"
+#endif
+
+#include "vars.h"
+
+#define DEBUG
+
+#ifdef DEBUG
+	.global display_string,hex_long,hex_word,hex_byte,display_char,wait_key,_debug
+#endif
+
+	.text
+	
+#ifdef COLDFIRE
+
+null:
+	clr.l 0x380        // not valid
+	move.l SP,0x3C0
+	move.l A6,0x3BC
+	lea 0x384,A6
+	movem.l D0-D7/A0-A5,(A6)
+	clr.l 0x3C8        // USP
+	moveq #-1,D1
+#endif
+
+exception:
+
+	clr.l memvalid
+	lea.l mess1(PC),A0
+	bsr display_string
+#ifdef COLDFIRE
+	ext.l D1
+	addq.l #1,D1
+	move.l D1,D7       // vector number
+#else
+	addq.w #1,D1
+	move.w D1,D7       // vector number
+#endif
+	moveq #0,D0
+	move.w D7,D0
+#ifdef COLDFIRE
+	.chip 68060
+	divu #10,D0
+	.chip 5200
+	move.l D0,D1
+	and.l #7,D0
+	beq.s .ex1
+	or.l #0x30,D0
+	bsr display_char
+.ex1:
+	swap D1
+	move.w D1,D0
+	or.l #0x30,D0
+#else
+	divu #10,D0
+	and.w #7,D0
+	beq.s .ex1
+	or.w #0x30,D0
+	bsr display_char
+.ex1:
+	swap d0
+	or.w #0x30,D0
+#endif
+	bsr display_char
+	moveq #0x3A,D0
+	bsr display_char
+	moveq #0x20,D0
+	bsr display_char
+	lea.l tab_mess_exc(PC),A0
+	move.w D7,D0
+	bsr display_tab
+	moveq #13,D0
+	bsr display_char
+	moveq #10,D0
+	bsr display_char
+#ifdef COLDFIRE
+	tst.w D7
+	beq .ex0
+#endif
+	lea.l mess2(PC),A0 // SR
+	bsr display_string
+#ifdef COLDFIRE
+	move.w save_sr,D0  // SR
+#else
+	move.l 0x3C0,A0    //SSP
+	move.w (A0),D0
+#endif
+	bsr hex_word       // SR
+	lea.l mess3(PC),A0
+	bsr display_string
+#ifdef COLDFIRE
+	move.w save_sr,D2  // SR
+	and.l #0xB71F,D2
+#else
+	move.l 0x3C0,A0    //SSP
+	move.w (A0),D2     // SR
+	and.w #0xB71F,D2
+#endif
+	lea.l tab_status(PC),A1
+	moveq #15,D1
+.ex5:
+		btst.l D1,D2
+		beq.s .ex6
+		moveq #0,D0
+		move.b (A1,D1),D0
+		move.w D0,D3
+#ifdef COLDFIRE
+		and.l #0xF8,D3
+		cmp.l #0x30,D3
+#else
+		and.w #0xF8,D3
+		cmp.w #0x30,D3
+#endif
+		bne.s .ex4
+		move.w D0,-(SP)
+		moveq #0x49,D0 // I
+		bsr display_char
+		move.w (SP)+,D0
+.ex4:
+		bsr display_char
+		moveq #0x20,D0
+		bsr display_char
+.ex6:
+#ifdef COLDFIRE
+	subq.l #1,D1
+	bpl.s .ex5
+.ex0:
+#else
+	dbf D1,.ex5
+#endif
+	lea.l mess4(PC),A0 // PC
+	bsr display_string
+#ifdef COLDFIRE
+	move.l save_pc,D0  // PC
+#else
+	move.l 0x3C0,A0    // SSP
+	move.l 2(A0),D0    // PC
+#endif
+	bsr hex_long
+	lea.l mess10(PC),A0 // Basepage
+	bsr display_string
+	move.l 0x6EE4,D0
+	bsr hex_long
+#ifdef COLDFIRE
+	tst.w D7
+	beq .ex2
+#endif
+	lea.l mess5(PC),A0 // CACR
+	bsr display_string  
+#ifdef COLDFIRE
+	.chip 68060
+	movec.l CACR,D0    // from value stored in the CF68KLIB
+	.chip 5200
+	bsr hex_long
+	cmp.l #2,D7
+	bne.s .ex2
+	lea.l mess6(PC),A0 // address fault
+	bsr display_string
+	move.l address_fault,D0 // from value stored in the CF68KLIB
+	bsr hex_long
+#else /* ATARI - CT60 */
+	movec.l CACR,D0
+	bsr hex_long
+	cmp.w #2,D7
+	beq.s .ex3         // Acces Fault
+	cmp.w #3,D7
+	beq.s .ex3         // Adress Error
+	cmp.w #5,D7
+	beq.s .ex3         // Zero Divide
+	cmp.w #9,D7
+	bne .ex2           // <> Trace
+.ex3:
+	lea.l mess6(PC),A0 // address fault
+	bsr display_string
+	move.l 0x3C0,A0    // SSP
+	move.l 8(A0),D0    // address fault
+	bsr hex_long
+	cmp.w #2,D7
+	bne .ex2           // <> Acces Fault
+	lea.l mess7(PC),A0 // FSLW
+	bsr display_string
+	move.l 0x3C0,A0    // SSP
+	move.l 12(A0),D0   // FSLW
+	bsr hex_long
+	lea.l mess3(PC),A0
+	bsr display_string
+	moveq #13,D0
+	bsr display_char
+	moveq #10,D0
+	bsr display_char
+	move.l 0x3C0,A0  // SSP
+	move.l 12(A0),D2 // FSLW
+	and.l #0x0BFFFFFD,D2
+	lea.l tab_fslw1(PC),A1
+	lea.l tab_fslw2(PC),A2
+	lea.l tab_fslw3(PC),A3
+	moveq #31,D1
+	moveq #0,D3
+.ex13:
+		btst.l D1,D2
+		beq.s .ex14
+		moveq #0,D0
+		move.b (A1,D3),D0
+		bsr display_char
+		moveq #0,D0
+		move.b (A2,D3),D0
+		cmp.b #0x20,D0
+		beq.s .ex12
+		bsr display_char
+		moveq #0,D0
+		move.b (A3,D3),D0
+		cmp.b #0x20,D0
+		beq.s .ex12
+		bsr display_char
+.ex12:
+		moveq #0x20,D0
+		bsr display_char
+.ex14:
+		addq.w #1,D3
+	dbf D1,.ex13
+#endif /* COLDFIRE */
+.ex2:
+	lea.l mess8(PC),A0 // SSP
+	bsr display_string
+	move.l 0x3C0,D0    // SSP
+	bsr hex_long
+	lea.l mess9(PC),A0 // USP
+	bsr display_string
+	move.l 0x3C8,D0    // USP
+	bsr hex_long
+	lea.l 0x384,A1     // registers
+	lea.l 32(A1),A2
+	moveq #7,D1
+.ex8:
+		moveq #13,D0
+		bsr display_char
+		moveq #10,D0
+		bsr display_char
+		moveq #0x44,D0
+		bsr display_char
+		moveq #7,D0
+#ifdef COLDFIRE
+		sub.l D1,D0
+		or.l #0x30,D0
+#else
+		sub.w D1,D0
+		or.w #0x30,D0
+#endif
+		move.w D0,-(SP)
+		bsr display_nb
+		move.l (A1),D0
+		bsr hex_long // data registers
+		moveq #0x20,D0
+		bsr display_char
+		tst.w D1
+		beq.s .ex9
+		moveq #0x41,D0
+		bsr display_char
+		move.w (SP),D0
+		bsr display_nb
+		move.l (A2),D0
+		bsr hex_long // address registers
+		moveq #0x20,D0
+		bsr display_char
+.ex9:		
+		addq.l #2,SP
+		addq.l #4,A1
+		addq.l #4,A2
+#ifdef COLDFIRE
+	subq.l #1,D1
+	bpl.s .ex8
+#else
+	dbf D1,.ex8
+#endif
+	moveq #13,D0
+	bsr display_char
+.loop_wait_key:
+#ifdef COLDFIRE
+#ifdef DEBUG
+		move.w #1,-(SP)          // AUX
+#else
+		move.w #2,-(SP)          // CON
+#endif
+#else
+		move.w #2,-(SP)          // CON
+#endif
+		move.w #2,-(SP)          // Bconin
+		trap #13
+		addq.l #4,SP
+		ext.l D0
+		move.l D0,-(SP)
+		move.l #0x5F504349,D0 
+		lea 0xED0000,A0          // 128 KB
+		cmp.l (A0),D0            // _PCI
+		beq.s .pci_drivers
+		lea 0xEC0000,A0          // 192 KB
+		cmp.l (A0),D0            // _PCI
+		beq.s .pci_drivers
+		lea 0xEB0000,A0          // 256 KB
+		cmp.l (A0),D0            // _PCI
+		beq.s .pci_drivers
+		lea 0xEA0000,A0          // 320 KB
+		cmp.l (A0),D0            // _PCI
+		bne.s .no_pci_drivers
+.pci_drivers:
+		jsr 40(A0)               // drivers PCI in flash, add dbug (68k disassembler)
+		move.l D0,(SP)
+		bne .no_pci_drivers
+		addq.l #4,SP
+		bra.s .loop_wait_key
+.no_pci_drivers:
+		move.l (SP)+,D0
+#ifdef COLDFIRE
+		and.l #0xFF,D0
+		cmp.l #0x6D,D0     // m
+#else
+		cmp.b #0x6D,D0     // m
+#endif
+		beq.s .memory_dump
+#ifdef COLDFIRE
+		cmp.l #0x70,D0     // p
+#else
+		cmp.b #0x70,D0     // p
+#endif
+		beq.s .patch_memory
+#ifdef DEBUG
+#ifdef COLDFIRE
+		cmp.l #0x20,D0
+#else
+		cmp.b #0x20,D0
+#endif	
+		bne .loop_wait_key
+		lea mess14(PC),A0
+		bsr display_string
+#endif
+		rts
+.memory_dump:
+		lea mess11(PC),A0  // memory dump
+		bsr display_string
+		bsr get_hex_value	
+		move.l D0,A0
+		bsr dump
+		bra .loop_wait_key
+.patch_memory:
+		lea mess12(PC),A0  // patch memory
+		bsr display_string
+		bsr get_hex_value
+		move.l D0,A1
+		lea mess13(PC),A0  // value
+		bsr display_string		
+		bsr get_hex_value
+		cmp.l #0x100,D0
+		bcc.s .word_value
+		move.b D0,(A1)
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char
+		move.b (A1),D0
+		bsr hex_byte
+		bra .loop_wait_key
+.word_value:
+		cmp.l #0x10000,D0
+		bcc.s .long_value
+		move.w D0,(A1)
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char
+		move.w (A1),D0
+		bsr hex_word	
+		bra .loop_wait_key
+.long_value:
+		move.l D0,(A1)
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char
+		move.l (A1),D0
+		bsr hex_long
+	bra .loop_wait_key
+	
+display_nb:
+
+	bsr display_char
+	moveq #0x3A,D0
+	bsr display_char
+	moveq #0x24,D0
+	bsr display_char
+	rts
+	
+display_tab:
+
+#ifdef COLDFIRE
+	move.l D1,-(SP)
+#endif
+	move.w D0,-(SP)
+	moveq #0,D0
+.dt1:
+#ifdef COLDFIRE
+		move.b (A0),D1
+		extb.l D1
+		cmp.l #-1,D1
+		beq.s .dt3
+		moveq #0,D1
+		move.w (SP),D1
+		cmp.l D1,D0
+#else
+		cmp.b #-1,(A0)
+		beq.s .dt3
+		cmp.w (SP),D0
+#endif
+		beq.s .dt4
+.dt2:
+		tst.b (A0)+
+		bne.s .dt2
+#ifdef COLDFIRE
+		addq.l #1,D0
+#else
+		addq.w #1,D0
+#endif
+	bra.s .dt1
+.dt4:
+	bsr display_string
+.dt3:
+
+	addq.l #2,SP
+#ifdef COLDFIRE
+	move.l (SP)+,D1
+#endif
+	rts
+		
+hex_long:
+	move.l D0,-(SP)
+	swap D0
+	bsr.s hex_word
+	move.l (SP)+,D0
+hex_word:
+	move.w D0,-(SP)
+#ifdef COLDFIRE
+	lsr.l #8,D0          
+	bsr.s hex_byte     
+	move.w (SP)+,D0
+hex_byte:
+	move.w D0,-(SP)
+	lsr.l #4,D0
+	bsr.s hex_char      
+	move.w (SP)+,D0      
+hex_char:
+	and.l #0xF,D0      
+	or.l #0x30,D0      
+	cmp.l #0x3A,D0     
+	bcs.s display_char  
+	addq.l #7,D0
+	    
+display_char:
+	and.l #0xFF,D0
+#ifdef DEBUG /* warning !!! If serial mouse */
+	move.l D1,-(SP)
+.wait_uart:
+	move.b MCF_UART_USR0,D1
+	and.l  #MCF_UART_USR_TXRDY,D1
+	beq.s .wait_uart
+	move.b D0,MCF_UART_UTB0 // send the character
+	move.l (SP)+,D1
+#else
+	lea -24(SP),SP     
+	movem.l D0-D2/A0-A2,(SP)
+	move.w D0,-(sp)
+	move.w #2,-(SP)
+	move.w #3,-(SP)       // Bconout
+	trap #13
+	addq.l #6,SP
+	movem.l (SP),D0-D2/A0-A2
+	lea 24(SP),SP
+#endif /* DEBUG */
+	rts
+#else  /* ATARI */
+	lsr.w #8,D0          
+	bsr.s hex_byte     
+	move.w (SP)+,D0
+hex_byte:
+	move.w D0,-(SP)
+	lsr.b #4,D0        
+	bsr.s hex_char      
+	move.w (SP)+,D0      
+hex_char:
+	and.b #0xF,D0      
+	or.b #0x30,D0      
+	cmp.b #0x3A,D0     
+	bcs.s display_char  
+	addq.b #7,D0   
+	    
+display_char:
+	and.w #0xFF,D0  
+	movem.l D0-D2/A0-A2,-(SP)
+	move.w D0,-(sp)
+	move.w #2,-(SP)
+	move.w #3,-(SP)       // Bconout
+	trap #13
+	addq.l #6,SP
+	movem.l (SP)+,D0-D2/A0-A2
+	rts
+#endif /* COLDFIRE */
+	
+display_string:
+
+#ifdef COLDFIRE
+	move.l D0,-(SP)
+	move.l A0,-(SP)
+#else
+	movem.l D0/A0,-(SP)
+#endif
+.os2:
+	move.b (A0)+,D0
+	beq.s .os1
+	bsr display_char
+	bra.s .os2
+.os1:
+#ifdef COLDFIRE
+	move.l (SP)+,A0
+	move.l (SP)+,D0
+#else
+	movem.l (SP)+,D0/A0
+#endif
+	rts
+	
+get_hex_value:
+
+#ifdef COLDFIRE
+	lea -56(SP),SP
+	movem.l D1-A5,(SP)
+	link A6,#-8
+	moveq #0,D7
+.loop_get_value:
+#ifdef DEBUG
+		move.w #1,-(SP)          // AUX
+#else
+		move.w #2,-(SP)          // CON
+#endif
+		move.w #2,-(SP)          // Bconin
+		trap #13
+		addq.l #4,SP
+		and.l #0xFF,D0
+		cmp.l #13,D0
+		beq.s .conv_get_value
+		cmp.l #8,D0
+		bne.s .not_backspace
+		tst.w D7
+		ble.s .loop_get_value
+		bsr display_char
+		subq.l #1,D7
+		bra.s .loop_get_value
+.not_backspace:
+		cmp.l #0x30,D0
+		bcs.s .loop_get_value
+		cmp.l #0x39,D0
+		bls.s .number_value
+		cmp.l #0x41,D0
+		bcs.s .loop_get_value
+		cmp.l #0x46,D0
+		bls.s .letter_value
+		cmp.l #0x61,D0
+		bcs.s .loop_get_value
+		cmp.l #0x66,D0
+		bhi.s .loop_get_value
+.letter_value:
+		bsr display_char
+		and.l #0x0F,D0
+		add.l #9,D0
+		bra.s .store_value		
+.number_value:
+		bsr display_char
+		and.l #0x0F,D0
+.store_value:
+		move.b D0,-8(A6,D7)
+		addq.l #1,D7
+	cmp.l #8,D7
+	bcs .loop_get_value
+.conv_get_value:
+	moveq #0,D0
+	subq.l #1,D7
+	bmi.s .end_get_value
+	moveq #0,D6
+.loop_value:
+		asl.l #4,D0
+		moveq #0,D1
+		move.b -8(A6,D6),D1 
+		or.l D1,D0
+		addq.l #1,D6
+	subq.l #1,D7
+	bpl.s  .loop_value		
+.end_get_value:	
+	tst.l D0
+	unlk A6
+	movem.l (SP),D1-A5
+	lea 56(SP),SP
+#else /* ATARI */
+	movem.l D1-A5,-(SP)
+	link A6,#-8
+	moveq #0,D7
+.loop_get_value:
+		move.w #2,-(SP)          // CON
+		move.w #2,-(SP)          // Bconin
+		trap #13
+		addq.l #4,SP
+		cmp.b #13,D0
+		beq.s .conv_get_value
+		cmp.b #8,D0
+		bne.s .not_backspace
+		tst.w D7
+		ble.s .loop_get_value
+		bsr display_char
+		subq.w #1,D7
+		bra.s .loop_get_value
+.not_backspace:
+		cmp.b #0x30,D0
+		bcs.s .loop_get_value
+		cmp.b #0x39,D0
+		bls.s .number_value
+		cmp.b #0x41,D0
+		bcs.s .loop_get_value
+		cmp.b #0x46,D0
+		bls.s .letter_value
+		cmp.b #0x61,D0
+		bcs.s .loop_get_value
+		cmp.b #0x66,D0
+		bhi.s .loop_get_value
+.letter_value:
+		bsr display_char
+		and.b #0x0F,D0
+		add.b #9,D0
+		bra.s .store_value		
+.number_value:
+		bsr display_char
+		and.b #0x0F,D0
+.store_value:
+		move.b D0,-8(A6,D7)
+		addq.w #1,D7
+	cmp.w #8,D7
+	bcs.s .loop_get_value
+.conv_get_value:
+	moveq #0,D0
+	subq.w #1,D7
+	bmi.s .end_get_value
+	moveq #0,D6
+.loop_value:
+		asl.l #4,D0
+		or.b -8(A6,D6),D0
+		addq.w #1,D6
+	dbf D7,.loop_value		
+.end_get_value:	
+	tst.l D0
+	unlk A6
+	movem.l (SP)+,D1-A5
+#endif /* COLDFIRE */
+	rts
+	
+dump:
+
+#ifdef COLDFIRE
+	lea -20(SP),SP
+	movem.l D0-D2/A0-A1,(SP)
+#else
+	movem.l D0-D2/A0-A1,-(SP)
+#endif
+	move.l A0,A1
+	moveq #3,D1
+.loop_dump1:
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char		
+		moveq #15,D2
+.loop_dump2:
+			move.b (A1)+,D0
+			bsr hex_byte
+			moveq #0x20,D0
+			bsr display_char
+#ifdef COLDFIRE
+		subq.l #1,D2
+		bpl.s .loop_dump2
+#else
+		dbf D2,.loop_dump2
+#endif
+		lea -16(A1),A1
+		moveq #15,D2
+.loop_dump3:
+			move.b (A1)+,D0
+#ifdef COLDFIRE
+			and.l #0xFF,D0
+			cmp.l #0x20,D0
+			bcs.s .dump_bad_char
+			cmp.l #0x7F,D0
+#else
+			cmp.b #0x20,D0
+			bcs.s .dump_bad_char
+			cmp.b #0x7F,D0
+#endif
+			bcs.s .dump_ok
+.dump_bad_char:
+			moveq #0x2E,D0
+.dump_ok:
+			bsr display_char
+#ifdef COLDFIRE
+		subq.l #1,D2
+		bpl.s .loop_dump3
+	subq.l #1,D1
+	bpl.s .loop_dump1
+	movem.l (SP),D0-D2/A0-A1
+	lea 20(SP),SP
+#else
+		dbf D2,.loop_dump3
+	dbf D1,.loop_dump1
+	movem.l (SP)+,D0-D2/A0-A1
+#endif
+	rts
+	
+crlf:	.byte 13,10,0
+mess1:	.byte 13,10
+	.asciz "EXCEPTION PROCESSING "
+mess2:	.byte 13,10
+	.asciz "Status Register (SR): $"
+mess3:	.asciz ", bits to 1: "
+mess4:	.byte 13,10
+	.asciz "Program Counter (PC): $"
+mess5:	.byte 13,10
+	.asciz "Cache Register (CACR): $"
+mess6:	.byte 13,10
+	.asciz "Address Fault: $"	
+mess7:	.byte 13,10
+	.asciz "Fault Status Word (FSLW): "
+mess8:	.byte 13,10
+	.asciz "Supervisor Stack (SSP): $"
+mess9:	.byte 13,10
+	.asciz "User Stack (USP): $"
+mess10:	.byte 13,10
+	.asciz "Basepage: $"
+mess11:	.byte 13,10	
+	.asciz "Memory dump (hex) ? "
+mess12:	.byte 13,10	
+	.asciz "Patch memory (hex) ? "
+mess13:	.byte 13,10	
+	.asciz "Value (hex) ? "
+mess14:	.byte 13,10	
+	.ascii "Pterm"
+	.byte 13,10,0
+ 
+tab_mess_exc:
+#ifdef COLDFIRE
+	.asciz "Null (jump or call)"
+#else
+	.byte 0
+#endif
+	.byte 0
+	.asciz "Access Fault"
+	.asciz "Address Error"
+	.asciz "Illegal Instruction"
+	.asciz "Integer Zero Divide"
+	.byte 0
+	.byte 0
+	.asciz "Privilege Violation"
+	.asciz "Trace"
+	.asciz "Line A"
+	.asciz "Line F"
+	.asciz "Emulator Interrupt"
+	.byte 0
+	.asciz "Format Error"
+	.asciz "Uninitialised Interrupt"
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.asciz "Spurious Interrupt"
+	.asciz "Interrupt level 1"
+	.asciz "Interrupt level 2" 
+	.asciz "Interrupt level 3" 
+	.asciz "Interrupt level 4"
+	.asciz "Interrupt level 5" 
+	.asciz "Interrupt level 6"
+	.asciz "Interrupt level 7"
+	.asciz "Trap #0"
+	.asciz "Trap #1"
+	.asciz "Trap #2"
+	.asciz "Trap #3"
+	.asciz "Trap #4"
+	.asciz "Trap #5"
+	.asciz "Trap #6"
+	.asciz "Trap #7"
+	.asciz "Trap #8"
+	.asciz "Trap #9"
+	.asciz "Trap #10"
+	.asciz "Trap #11"
+	.asciz "Trap #12"
+	.asciz "Trap #13"
+	.asciz "Trap #14"
+	.asciz "Trap #15"
+	.byte -1
+
+tab_status:	.ascii "CVZNX   012 MS T"
+
+tab_fslw1:	.ascii "    M LRWSSTTTTTIPSPPIPSWTRWTB S"
+tab_fslw2:	.ascii "    A K  ZZTTMMMOBBTTLFPPWEETP S"
+tab_fslw3:	.ascii "         1010210 EEAB    E  RE E"
diff --git a/usb/store/host/aranym/aranym-hcd.c b/usb/store/host/aranym/aranym-hcd.c
new file mode 100644
index 0000000..fe3dbb9
--- /dev/null
+++ b/usb/store/host/aranym/aranym-hcd.c
@@ -0,0 +1,150 @@
+/*
+	NatFeat USB host chip emulator
+
+	ARAnyM (C) 2010 David Gálvez
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with this program; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*--- Include ---*/
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <mint/cookie.h>
+#include <mint/osbind.h>
+
+#include "nf_ops.h"
+#include "usbhost_nfapi.h"
+#include "../../config.h"
+#include "../../asm-m68k/io.h"
+#include "../../usb.h"
+#include "../../debug.h"
+
+/*--- Defines ---*/
+
+#ifndef EINVFN
+#define EINVFN	-32
+#endif
+
+#ifndef DEV_CONSOLE
+#define DEV_CONSOLE	2
+#endif
+
+#define DRIVER_NAME	"ARAnyM USB host chip emulator"
+#define VERSION	"v0.1"
+
+
+/*--- Functions prototypes ---*/
+
+static void press_any_key(void);
+
+
+/*--- Local variables ---*/
+
+static struct nf_ops *nfOps;
+static unsigned long nfUsbHostId;
+
+
+/*--- Functions ---*/
+
+
+static void press_any_key(void)
+{
+
+	(void) Cconws("- Press any key to continue -\r\n");
+	while (Bconstat(DEV_CONSOLE) == 0) { };
+}
+
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_INT_MSG), dev, pipe, buffer, len, interval);
+
+	return 0;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_CONTROL_MSG), dev, pipe, buffer, len, setup);
+
+	return r;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_BULK_MSG), dev, pipe, buffer, len);
+
+	return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+int usb_lowlevel_init(void)
+{
+	int r;
+
+	(void) Cconws(
+		"\033p " DRIVER_NAME " " VERSION " \033q\r\n"
+		"Copyright (c) ARAnyM Development Team, " __DATE__ "\r\n"
+	);
+
+	nfOps = nf_init();
+	if (!nfOps) {
+		(void) Cconws("__NF cookie not present on this system\r\n");
+		press_any_key();
+		return 0;
+	}
+	
+	nfUsbHostId=nfOps->get_id("USBHOST");
+	if (nfUsbHostId == 0) {
+		(void) Cconws("NF USBHOST functions not present on this system\r\n");
+		press_any_key();
+	}
+
+	/* List present devices */
+
+	r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_INIT));
+
+	if (!r) 
+		(void) Cconws(" USB Init \r\n");
+	else
+		(void) Cconws(" Couldn't init aranym host chip emulator \r\n");
+
+	return 0;
+
+}
+
+int usb_lowlevel_stop(void)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_STOP));
+
+	return 0;
+
+}
+
diff --git a/usb/store/host/aranym/natfeat.c b/usb/store/host/aranym/natfeat.c
new file mode 100644
index 0000000..93edd30
--- /dev/null
+++ b/usb/store/host/aranym/natfeat.c
@@ -0,0 +1,118 @@
+/*
+ * ARAnyM native features interface.
+ * (c) 2005-2008 ARAnyM development team
+ *
+ * In 2006 updated with FreeMiNT headers and code.
+ * In 2008 converted from "__NF" cookie to direct usage of NF instructions
+ *
+ **/
+
+/*
+ * Copied from FreeMiNT source tree where Native Features were added recently
+ * 
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-13
+ * 
+ */
+
+# include <compiler.h>
+# include <mint/osbind.h>
+# include "nf_ops.h"
+
+
+#define ARANYM 1
+# ifdef ARANYM
+
+
+static unsigned long nf_get_id_instr = 0x73004e75UL;
+static unsigned long nf_call_instr = 0x73014e75UL;
+
+static struct nf_ops _nf_ops = { (void*)&nf_get_id_instr, (void*)&nf_call_instr }; 
+static struct nf_ops *nf_ops = 0UL; 
+
+extern int detect_native_features(void);
+
+struct nf_ops *
+nf_init(void)
+{
+	if (Supexec(detect_native_features))
+	{
+		nf_ops = &_nf_ops;
+		return nf_ops;
+	}
+	
+	return 0UL;
+}
+
+
+const char *
+nf_name(void)
+{
+	static char buf[64] = "Unknown emulator";
+	
+	if (nf_ops)
+	{
+		static int done = 0;
+		
+		if (!done)
+		{
+			long nfid_name = nf_ops->get_id("NF_NAME");
+			
+			if (nfid_name)
+				nf_ops->call(nfid_name, buf, sizeof(buf));
+			
+			done = 1;
+		}
+	}
+        
+	return buf;
+}
+
+int
+nf_debug(const char *msg)
+{
+	if (nf_ops)
+	{
+		long nfid_stderr = nf_ops->get_id("NF_STDERR");
+		
+		if (nfid_stderr)
+		{
+			nf_ops->call(nfid_stderr, msg);
+			return 1;
+		}
+	}
+	
+	return 0;
+}
+
+void
+nf_shutdown(void)
+{
+	if (nf_ops)
+	{
+		long shutdown_id = nf_ops->get_id("NF_SHUTDOWN");
+		
+		if (shutdown_id)
+        		nf_ops->call(shutdown_id);
+	}
+}
+
+# endif
diff --git a/usb/store/host/aranym/natfeat_asm.S b/usb/store/host/aranym/natfeat_asm.S
new file mode 100644
index 0000000..e1b75b3
--- /dev/null
+++ b/usb/store/host/aranym/natfeat_asm.S
@@ -0,0 +1,76 @@
+/*
+ * ARAnyM native features interface.
+ * (c) 2005-2008 ARAnyM development team
+ *
+ * In 2006 updated with FreeMiNT headers and code.
+ * In 2008 converted from "__NF" cookie to direct usage of NF instructions
+ *
+ **/
+
+/*
+ * Copied from FreeMiNT source tree where Native Features were added recently
+ *
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-13
+ * 
+ * please send suggestions, patches or bug reports to me or
+ * the MiNT mailing list
+ * 
+ */
+
+#define ARANYM 1
+# ifdef ARANYM
+
+	.text
+
+	.globl	_detect_native_features
+
+/* 
+ * NatFeats test (routine retuns TRUE/FALSE (1/0) in D0)
+ */
+_detect_native_features:
+
+	clr.l	d0			// assume no NatFeats available
+	move.l	sp,a1			// save the ssp
+	move.l	(0x0010).w,a0		// illegal instruction vector
+	move.l	#fail_natfeat,(0x0010).w
+
+	nop				// flush pipelines (for 68040+)
+
+	pea	(nf_version_name).w(pc)
+	subq.l	#4,sp
+	dc.w	0x7300			// Jump to NATFEAT_ID
+	tst.l	d0
+	beq.s	fail_natfeat
+	moveq	#1,d0			// NatFeats detected
+
+fail_natfeat:
+	move.l	a1,sp
+	move.l	a0,(0x0010).w
+
+	nop				// flush pipelines (for 68040+)
+
+	rts
+
+nf_version_name:
+	.ascii	"NF_VERSION\0"
+
+# endif
diff --git a/usb/store/host/aranym/nf_ops.h b/usb/store/host/aranym/nf_ops.h
new file mode 100644
index 0000000..b8d1e79
--- /dev/null
+++ b/usb/store/host/aranym/nf_ops.h
@@ -0,0 +1,63 @@
+/*
+ * $Id: nf_ops.h,v 1.2 2006-01-31 16:21:22 standa Exp $
+ * 
+ * ARAnyM Native Features suite.
+ *
+ * This file was taken from FreeMiNT.
+ * 
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-14
+ * 
+ * Please send suggestions, patches or bug reports to me or
+ * the MiNT mailing list.
+ * 
+ */
+
+# ifndef _m68k_nf_ops_h
+# define _m68k_nf_ops_h
+
+#include <compiler.h>	/* for __CDECL */
+
+
+struct nf_ops
+{
+	long __CDECL (*get_id)(const char *);
+	long __CDECL (*call)(long id, ...);
+	long res[3];
+};
+
+
+/**
+ * Use this function to intialize Native Features.
+ *
+ * @return the pointer to 'struct nf_ops' or NULL when
+ *         not available.
+ **/
+struct nf_ops *nf_init(void);
+
+
+/* basic set native feature functions */
+const char *nf_name(void);
+int  nf_debug(const char *msg);
+void nf_shutdown(void);
+
+
+# endif /* _m68k_nf_ops_h */
diff --git a/usb/store/host/aranym/usbhost_nfapi.h b/usb/store/host/aranym/usbhost_nfapi.h
new file mode 100644
index 0000000..e8ffa2e
--- /dev/null
+++ b/usb/store/host/aranym/usbhost_nfapi.h
@@ -0,0 +1,40 @@
+/*
+	NatFeat USB Host chip emulator
+
+	ARAnyM (C) 2010 David Gálvez
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with this program; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef _USBHOST_NFAPI_H
+#define _USBHOST_NFAPI_H
+
+/* if you change anything in the enum {} below you have to increase 
+   this ARAUSBHOST_NFAPI_VERSION!
+*/
+#define ARAUSBHOST_NFAPI_VERSION	0x00000000
+
+enum {
+	GET_VERSION = 0,	/* no parameters, return NFAPI_VERSION in d0 */
+	USBHOST_LOWLEVEL_INIT,
+	USBHOST_LOWLEVEL_STOP,
+	USBHOST_SUBMIT_CONTROL_MSG,
+	USBHOST_SUBMIT_INT_MSG,
+	USBHOST_SUBMIT_BULK_MSG
+};
+
+#define USBHOST(a)	(nfUsbHostId + a)
+
+#endif /* _USBHOST_NFAPI_H */
diff --git a/usb/store/host/ethernat/isp116x-hcd.c b/usb/store/host/ethernat/isp116x-hcd.c
new file mode 100644
index 0000000..fbfa611
--- /dev/null
+++ b/usb/store/host/ethernat/isp116x-hcd.c
@@ -0,0 +1,1583 @@
+/*
+ * Modified for Atari-EtherNat by David Gálvez 2010
+ *
+ * ISP116x HCD (Host Controller Driver) for u-boot.
+ *
+ * Copyright (C) 2006-2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2006-2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
+ * (original copyright message follows):
+ *
+ *    (C) Copyright 2004
+ *    Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ *    This code is based on linux driver for sl811hs chip, source at
+ *    drivers/usb/host/sl811.c:
+ *
+ *    SL811 Host Controller Interface driver for USB.
+ *
+ *    Copyright (c) 2003/06, Courage Co., Ltd.
+ *
+ *    Based on:
+ *         1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap,
+ *           Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber,
+ *           Adam Richter, Gregory P. Smith;
+ *         2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com>
+ *         3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c"
+ * (original copyright message follows):
+ *
+ *    URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ *    (C) Copyright 2003
+ *    Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ *    Note: Part of this code has been derived from linux
+ */
+#include "../../config.h"
+#include "../../asm-m68k/io.h"
+#include "../../usb.h"
+#include "../../debug.h"
+
+void udelay(unsigned long usec);
+
+//extern void boot_printf(const char *fmt, ...);
+
+
+/*
+ * ISP116x chips require certain delays between accesses to its
+ * registers. The following timing options exist.
+ *
+ * 1. Configure your memory controller (the best)
+ * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
+ *
+ * Value is in microseconds.
+ */
+#ifdef ISP116X_HCD_USE_UDELAY
+#define UDELAY		1
+#endif
+
+/*
+ * On some (slowly?) machines an extra delay after data packing into
+ * controller's FIFOs is required, * otherwise you may get the following
+ * error:
+ *
+ *   uboot> usb start
+ *   (Re)start USB...
+ *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
+ *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
+ *
+ *         USB device not responding, giving up (status=4)
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         3 USB Device(s) found
+ *                scanning bus for storage devices... 0 Storage Device(s) found
+ *
+ * Value is in milliseconds.
+ */
+#ifdef ISP116X_HCD_USE_EXTRA_DELAY
+#define EXTRA_DELAY	2
+#endif
+
+/*
+ * Enable the following defines if you wish enable extra debugging messages.
+ * Normal debug messages controlled from config.h.
+ */
+
+//#define TRACE			/* enable tracing code */
+//#define VERBOSE		/* verbose debugging messages */
+
+#include "isp116x.h"
+
+#define DRIVER_VERSION	"08 Jan 2007"
+static const char hcd_name[] = "isp116x-hcd";
+
+struct isp116x isp116x_dev;
+struct isp116x_platform_data isp116x_board;
+static int got_rhsc;		/* root hub status change */
+struct usb_device *devgone;	/* device which was disconnected */
+static int rh_devnum;		/* address of Root Hub endpoint */
+
+/* ------------------------------------------------------------------------- */
+
+#define ALIGN(x,a)	(((x)+(a)-1UL)&~((a)-1UL))
+#define min1_t(type,x,y)	\
+	({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
+
+/* Galvez: added to avoid shadow warnings */
+#define min2_t(type,x,y)	\
+	({ type __a = (x); type __b = (y); __a < __b ? __a : __b; })
+
+/* ------------------------------------------------------------------------- */
+
+
+static int isp116x_reset(struct isp116x *isp116x);
+
+/* --- Debugging functions ------------------------------------------------- */
+
+#define isp116x_show_reg(d, r) {				\
+	if ((r) < 0x20) {					\
+		DEBUG_HOST("%-12s[%02x]: %08x", #r,			\
+			r, isp116x_read_reg32(d, r));		\
+	} else {						\
+		DEBUG_HOST("%-12s[%02x]:     %04x", #r,		\
+			r, isp116x_read_reg16(d, r));		\
+	}							\
+}
+
+#define isp116x_show_regs(d) {					\
+	isp116x_show_reg(d, HCREVISION);			\
+	isp116x_show_reg(d, HCCONTROL);				\
+	isp116x_show_reg(d, HCCMDSTAT);				\
+	isp116x_show_reg(d, HCINTSTAT);				\
+	isp116x_show_reg(d, HCINTENB);				\
+	isp116x_show_reg(d, HCFMINTVL);				\
+	isp116x_show_reg(d, HCFMREM);				\
+	isp116x_show_reg(d, HCFMNUM);				\
+	isp116x_show_reg(d, HCLSTHRESH);			\
+	isp116x_show_reg(d, HCRHDESCA);				\
+	isp116x_show_reg(d, HCRHDESCB);				\
+	isp116x_show_reg(d, HCRHSTATUS);			\
+	isp116x_show_reg(d, HCRHPORT1);				\
+	isp116x_show_reg(d, HCRHPORT2);				\
+	isp116x_show_reg(d, HCHWCFG);				\
+	isp116x_show_reg(d, HCDMACFG);				\
+	isp116x_show_reg(d, HCXFERCTR);				\
+	isp116x_show_reg(d, HCuPINT);				\
+	isp116x_show_reg(d, HCuPINTENB);			\
+	isp116x_show_reg(d, HCCHIPID);				\
+	isp116x_show_reg(d, HCSCRATCH);				\
+	isp116x_show_reg(d, HCITLBUFLEN);			\
+	isp116x_show_reg(d, HCATLBUFLEN);			\
+	isp116x_show_reg(d, HCBUFSTAT);				\
+	isp116x_show_reg(d, HCRDITL0LEN);			\
+	isp116x_show_reg(d, HCRDITL1LEN);			\
+}
+
+#if defined(TRACE)
+
+static int isp116x_get_current_frame_number(struct usb_device *usb_dev)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	return isp116x_read_reg32(isp116x, HCFMNUM);
+}
+
+static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		     int len, char *str)
+{
+#if defined(VERBOSE)
+	int i;
+#endif
+	DEBUG_HOST("%s URB:[%4x] dev:%2ld,ep:%2ld-%c,type:%s,len:%d stat:%#lx",
+	    str,
+	    isp116x_get_current_frame_number(dev),
+	    usb_pipedevice(pipe),
+	    usb_pipeendpoint(pipe),
+	    usb_pipeout(pipe) ? 'O' : 'I',
+	    usb_pipetype(pipe) < 2 ?
+	    (usb_pipeint(pipe) ?
+	     "INTR" : "ISOC") :
+	    (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status);
+#if defined(VERBOSE)
+	debug_init("usb.log");
+	if (len > 0 && buffer) {
+		debug(__FILE__ ": data(%d):", len);
+		for (i = 0; i < 16 && i < len; i++)
+			debug(" %02x", ((__u8 *) buffer)[i]);
+		debug("%s\r\n", i < len ? "..." : "");
+	}
+	debug_exit();
+#endif
+}
+
+#define PTD_DIR_STR(ptd)  ({char __c;		\
+	switch(PTD_GET_DIR(ptd)){		\
+	case 0:  __c = 's'; break;		\
+	case 1:  __c = 'o'; break;		\
+	default: __c = 'i'; break;		\
+	}; __c;})
+
+/*
+  Dump PTD info. The code documents the format
+  perfectly, right :)
+*/
+static inline void dump_ptd(struct ptd *ptd)
+{
+#if defined(VERBOSE)
+	int k;
+#endif
+
+	DEBUG_HOST("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x",
+	    PTD_GET_CC(ptd),
+	    PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
+	    PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
+	    PTD_GET_TOGGLE(ptd),
+	    PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
+#if defined(VERBOSE)
+	debug_init("usb.log");
+	debug("isp116x: %s: PTD(byte): ", __FUNCTION__);
+	for (k = 0; k < sizeof(struct ptd); ++k) {
+		debug("%02x ", ((u8 *) ptd)[k]);
+	}
+	debug("\n\r");
+	debug_exit();
+#endif
+}
+
+static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type)
+{
+#if defined(VERBOSE)
+	int k;
+	
+	debug_init("usb.log");
+	if (type == 0 /* 0ut data */ ) {
+		debug("isp116x: %s: out data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_LEN(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	if (type == 1 /* 1n data */ ) {
+		debug("isp116x: %s: in data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_COUNT(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	
+	debug_exit();
+	
+	if (PTD_GET_LAST(ptd)) {
+		DEBUG_HOST("--- last PTD ---");
+	}
+#endif
+}
+
+#else
+
+#define dump_msg(dev, pipe, buffer, len, str)			do { } while (0)
+#define dump_pkt(dev, pipe, buffer, len, setup, str, small)	do {} while (0)
+
+#define dump_ptd(ptd)			do {} while (0)
+#define dump_ptd_data(ptd, buf, type)	do {} while (0)
+
+#endif
+
+/* --- Virtual Root Hub ---------------------------------------------------- */
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x10,			/*  __u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x00,			/*  __u8  iManufacturer; */
+	0x01,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+	/* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+	/* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x00,			/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x02,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] = {
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+	0x22,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'I',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'S',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'P',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'6',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'x',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+};
+
+/*
+ * Hub class-specific descriptor is constructed dynamically
+ */
+
+/* --- Virtual root hub management functions ------------------------------- */
+
+static int rh_check_port_status(struct isp116x *isp116x)
+{
+	u32 temp, ndp, i;
+	int res;
+
+	res = -1;
+	temp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+	ndp = (temp & RH_A_NDP);
+	for (i = 0; i < ndp; i++) {
+		temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+		     (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+/* --- HC management functions --------------------------------------------- */
+
+/* Write len bytes to fifo, pad till 32-bit boundary
+ */
+static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+	
+/* For EtherNat, take the raw_write out in write functions, here we don't
+ * like that EtherNat swap the bytes for us, so we swap them before we send
+ * them, then the bytes will arrive to the USB device with the correct positions
+ */
+ 	if ((unsigned long)dp2 & 1) {
+	DEBUG_HOST("---not aligned ---");
+		/* not aligned */
+		for (; len > 1; len -= 2) {
+			w = *dp++;
+			w |= *dp++ << 8;
+			isp116x_write_data16(isp116x, w);
+		}
+		if (len)
+			isp116x_write_data16(isp116x, (u16) * dp);
+	} else {
+	DEBUG_HOST("---aligned ---");
+		/* aligned */
+		for (; len > 1; len -= 2)
+			isp116x_write_data16(isp116x, *dp2++);
+		if (len){DEBUG_HOST("write_data16\r\n"); /* GALVEZ: DEBUG */
+			isp116x_raw_write_data16(isp116x, 0xff & *((u8 *) dp2));}
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_write_data16(isp116x, 0);
+}
+
+/* Read len bytes from fifo and then read till 32-bit boundary
+ */
+static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+
+/* For EtherNAT, take the raw_read out from read functions, we want to swap the bytes
+   to read correct values because EtherNat swapped the bytes by hardware before we read 
+   them */
+
+	if ((unsigned long)dp2 & 1) {
+		/* not aligned */
+		DEBUG_HOST("---not aligned ---");
+		for (; len > 1; len -= 2) {
+			w = isp116x_read_data16(isp116x);
+			*dp++ = w & 0xff;
+			*dp++ = (w >> 8) & 0xff;
+		}
+		if (len)
+			*dp = 0xff & isp116x_read_data16(isp116x);
+	} else {
+		/* aligned */
+		DEBUG_HOST("---aligned ---");
+		for (; len > 1; len -= 2)
+			*dp2++ = isp116x_read_data16(isp116x);
+		if (len)
+			*(u8 *) dp2 = 0xff & isp116x_raw_read_data16(isp116x);
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_read_data16(isp116x);
+}
+
+/* Write PTD's and data for scheduled transfers into the fifo ram.
+ * Fifo must be empty and ready */
+static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		      unsigned long pipe, struct ptd *ptd, int n, void *data,
+		      int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done;
+
+	DEBUG_HOST("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
+	
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET);
+
+	done = 0;
+	for (i = 0; i < n; i++) {
+		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+
+/* For EtherNAT, use raw_write to don't swap bytes */
+		dump_ptd(&ptd[i]);
+		isp116x_raw_write_data16(isp116x, ptd[i].count);
+		isp116x_raw_write_data16(isp116x, ptd[i].mps);
+		isp116x_raw_write_data16(isp116x, ptd[i].len);
+		isp116x_raw_write_data16(isp116x, ptd[i].faddr);
+
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 0);
+
+		write_ptddata_to_fifo(isp116x,
+				      (__u8 *) data + done,
+				      PTD_GET_LEN(&ptd[i]));
+
+		done += PTD_GET_LEN(&ptd[i]);
+	}
+}
+
+/* Read the processed PTD's and data from fifo ram back to URBs' buffers.
+ * Fifo must be full and done */
+static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		       unsigned long pipe, struct ptd *ptd, int n, void *data,
+		       int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done, cc, ret;
+
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT);
+
+	ret = TD_CC_NOERROR;
+	done = 0;
+	for (i = 0; i < n; i++) {
+		/* Galvez: DEBUG */
+//		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+		DEBUG_HOST("i=%d n=%d - done=%d - len= %d ptd_len=%d\n\r", i,n, done, len, PTD_GET_LEN(&ptd[i]));
+		/*****************/
+		
+	/* For EtherNAT, use raw_read to don't swap bytes */
+		ptd[i].count = isp116x_raw_read_data16(isp116x);
+		ptd[i].mps = isp116x_raw_read_data16(isp116x);
+		ptd[i].len = isp116x_raw_read_data16(isp116x);
+		ptd[i].faddr = isp116x_raw_read_data16(isp116x);
+		dump_ptd(&ptd[i]);
+		
+		/* when cc is 15 the data has not being touch by the HC
+		 * so we have to read all to empty completly the buffer
+		 */
+//		if ( PTD_GET_COUNT(ptd) != 0 || PTD_GET_CC(ptd) == 15 )
+			read_ptddata_from_fifo(isp116x,
+					       (__u8 *) data + done,
+					       PTD_GET_LEN(&ptd[i]));
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 1);
+
+		done += PTD_GET_LEN(&ptd[i]);
+	
+		cc = PTD_GET_CC(&ptd[i]);
+	
+		/* Data underrun means basically that we had more buffer space than
+		 * the function had data. It is perfectly normal but upper levels have
+		 * to know how much we actually transferred.
+		 */
+		if (cc == TD_NOTACCESSED ||
+				(cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
+			ret = cc;
+	}
+
+	DEBUG_HOST("--- unpack buffer %p - %d bytes (fifo %d) count: %d---\n", data, len, buflen, PTD_GET_COUNT(ptd));
+
+	return ret;
+}
+
+/* Interrupt handling
+ */
+static int isp116x_interrupt(struct isp116x *isp116x)
+{
+	u16 irqstat;
+	u32 intstat;
+	int ret = 0;
+
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+	irqstat = isp116x_read_reg16(isp116x, HCuPINT);
+	isp116x_write_reg16(isp116x, HCuPINT, irqstat);
+	DEBUG_HOST(">>>>>> irqstat %x <<<<<<", irqstat);
+	
+	if (irqstat & HCuPINT_ATL) {
+		DEBUG_HOST(">>>>>> HCuPINT_ATL <<<<<<");
+		udelay(500);
+		ret = 1;
+	}
+
+	if (irqstat & HCuPINT_OPR) {
+		intstat = isp116x_read_reg32(isp116x, HCINTSTAT);
+		isp116x_write_reg32(isp116x, HCINTSTAT, intstat);
+		DEBUG_HOST(">>>>>> HCuPINT_OPR %x <<<<<<", intstat);
+
+		if (intstat & HCINT_UE) {
+			ERR("unrecoverable error, controller disabled");
+
+			/* FIXME: be optimistic, hope that bug won't repeat
+			 * often. Make some non-interrupt context restart the
+			 * controller. Count and limit the retries though;
+			 * either hardware or software errors can go forever...
+			 */
+			isp116x_reset(isp116x);
+			ret = -1;
+			return -1;
+		}
+
+		if (intstat & HCINT_RHSC) {
+			got_rhsc = 1;
+			ret = 1;
+			/* When root hub or any of its ports is going
+			   to come out of suspend, it may take more
+			   than 10ms for status bits to stabilize. */
+			wait_ms(20);
+		}
+
+		if (intstat & HCINT_SO) {
+			ERR("schedule overrun");
+			ret = -1;
+		}
+
+		irqstat &= ~HCuPINT_OPR;
+	}
+
+	return ret;
+}
+
+/* With one PTD we can transfer almost 1K in one go;
+ * HC does the splitting into endpoint digestible transactions
+ */
+struct ptd ptd[1];
+
+static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
+{
+	unsigned mpck = usb_maxpacket(dev, pipe);
+
+	/* One PTD can transfer 1023 bytes but try to always
+	 * transfer multiples of endpoint buffer size
+	 */
+	return 1023 / mpck * mpck;
+}
+
+/* Do an USB transfer
+ */
+static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
+			      int dir, void *buffer, int len)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	int type = usb_pipetype(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = usb_maxpacket(dev, pipe);
+	int dir_out = usb_pipeout(pipe);
+	int speed_low = usb_pipeslow(pipe);
+	int i, done = 0, stat, timeout, cc;
+
+	/* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
+	int retries = 500;
+
+
+	DEBUG_HOST("------------------------------------------------");
+	dump_msg(dev, pipe, buffer, len, "SUBMIT");
+	DEBUG_HOST("------------------------------------------------");
+	
+	if (len >= 1024) {
+		ERR("Too big job");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (isp116x->disabled) {
+		ERR("EPIPE");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	/* device pulled? Shortcut the action. */
+	if (devgone == dev) {
+		ERR("ENODEV");
+		dev->status = USB_ST_CRC_ERR;
+		return USB_ST_CRC_ERR;
+	}
+
+	if (!max) {
+		ERR("pipesize for pipe %lx is zero", pipe);
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (type == PIPE_ISOCHRONOUS) {
+		ERR("isochronous transfers not supported");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+	
+	/* FIFO not empty? */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+
+retry:
+	isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
+	/* Prepare the PTD data */
+	ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
+		PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
+	ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
+	ptd->len = PTD_LEN(len) | PTD_DIR(dir);
+	ptd->faddr = PTD_FA(usb_pipedevice(pipe));
+
+	
+retry_same:
+
+	/* FIFO not empty? */ /* GALVEZ: DEBUG */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+
+	/* Pack data into FIFO ram */
+	pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+#ifdef EXTRA_DELAY
+	wait_ms(EXTRA_DELAY);
+#endif
+
+	/* Start the data transfer */
+
+	/* Allow more time for a BULK device to react - some are slow */
+	if (usb_pipebulk(pipe))
+		timeout = 5000; /* Galvez: default = 5000 */
+	else
+		timeout = 100;
+
+	/* Wait for it to complete */
+	for (;;) {
+		/* Check whether the controller is done */
+		stat = isp116x_interrupt(isp116x);
+
+		if (stat < 0) {
+			dev->status = USB_ST_CRC_ERR;
+			break;
+		}
+		if (stat > 0)
+			break;
+
+		/* Check the timeout */
+		if (--timeout)
+			udelay(1);
+		else {
+			ERR("CTL:TIMEOUT ");
+			printf("CTL:TIMEOUT ");
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+	}
+
+	/* We got an Root Hub Status Change interrupt */
+	if (got_rhsc) {
+		isp116x_show_regs(isp116x);
+
+		got_rhsc = 0;
+
+		/* Abuse timeout */
+		timeout = rh_check_port_status(isp116x);
+		if (timeout >= 0) {
+			/*
+			 * FIXME! NOTE! AAAARGH!
+			 * This is potentially dangerous because it assumes
+			 * that only one device is ever plugged in!
+			 */
+			devgone = dev;
+		}
+	}
+
+
+	/* Ok, now we can read transfer status */
+
+	/* FIFO not ready? */
+	if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) {
+		DEBUG_HOST("****** FIFO not ready! ******");
+		printf("****** FIFO not ready! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+	
+	
+	/* Unpack data from FIFO ram */
+	cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+	i = PTD_GET_COUNT(ptd);
+	done += i;
+	buffer += i;
+	len -= i;
+	
+	
+	/* There was some kind of real problem; Prepare the PTD again
+	 * and retry from the failed transaction on
+	 */
+	if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
+	DEBUG_HOST("PROBLEM cc: %d", cc);
+		if (retries >= 100) {
+			retries -= 100;
+			/* The chip will have toggled the toggle bit for the failed
+			 * transaction too. We have to toggle it back.
+			 */
+			usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+	/* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
+	 * the transactions from the first on for the whole frame. It may be busy and we retry
+	 * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
+	 * PTD didn't make it because the function was busy or the frame ended before the PTD
+	 * finished. We prepare the rest of the data and try again.
+	 */
+	else if ( cc == TD_NOTACCESSED ||  PTD_GET_ACTIVE(ptd) ||  ( cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
+		DEBUG_HOST("NORMAL ERROR");
+		if (retries) {
+			--retries;
+			if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) {
+				goto retry_same;
+			}
+			usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+
+
+	if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
+		DEBUG_HOST("****** completition code error %x ******", cc);
+		switch (cc) {
+		case TD_CC_BITSTUFFING:
+			dev->status = USB_ST_BIT_ERR;
+			break;
+		case TD_CC_STALL:
+			dev->status = USB_ST_STALLED;
+			break;
+		case TD_BUFFEROVERRUN:
+		case TD_BUFFERUNDERRUN:
+			dev->status = USB_ST_BUF_ERR;
+			break;
+		default:
+			dev->status = USB_ST_CRC_ERR;
+		}
+		return -cc;
+	}
+	else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+
+	dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
+
+	dev->status = 0;
+	return done;
+}
+
+/* Adapted from au1x00_usb_ohci.c
+ */
+static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+				 void *buffer, int transfer_len,
+				 struct devrequest *cmd)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	u32 tmp = 0;
+
+	int leni = transfer_len;
+	int len = 0;
+	int stat = 0;
+	u32 datab[4];
+	u8 *data_buf = (u8 *) datab;
+	u16 bmRType_bReq;
+	u16 wValue;
+	u16 wIndex;
+	u16 wLength;
+
+	if (usb_pipeint(pipe)) {
+		INFO("Root-Hub submit IRQ: NOT implemented");
+		return 0;
+	}
+
+	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+
+	DEBUG_HOST("--- HUB ----------------------------------------");
+	DEBUG_HOST("submit rh urb, req=%x val=%#x index=%#x len=%d",
+	    bmRType_bReq, wValue, wIndex, wLength);
+	dump_msg(dev, pipe, buffer, transfer_len, "RH");
+	DEBUG_HOST("------------------------------------------------");
+
+	switch (bmRType_bReq) {
+	case RH_GET_STATUS:
+		DEBUG_HOST("RH_GET_STATUS");
+
+		*(__u16 *) data_buf = swap_16(1);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_INTERFACE:
+		DEBUG_HOST("RH_GET_STATUS | RH_INTERFACE");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_ENDPOINT:
+		DEBUG_HOST("RH_GET_STATUS | RH_ENDPOINT");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+		*(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE));
+		len = 4;
+		break;
+
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_OTHER | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1);
+		*(__u32 *) data_buf = swap_32(tmp);
+		isp116x_show_regs(isp116x);
+		len = 4;
+		break;
+
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_ENDPOINT");
+
+		switch (wValue) {
+		case RH_ENDPOINT_STALL:
+			DEBUG_HOST("C_HUB_ENDPOINT_STALL");
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_CLASS");
+
+		switch (wValue) {
+		case RH_C_HUB_LOCAL_POWER:
+			DEBUG_HOST("C_HUB_LOCAL_POWER");
+			len = 0;
+			break;
+
+		case RH_C_HUB_OVER_CURRENT:
+			DEBUG_HOST("C_HUB_OVER_CURRENT");
+			isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC);
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CCS);
+			len = 0;
+			break;
+
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_LSDA);
+			len = 0;
+			break;
+
+		case RH_C_PORT_CONNECTION:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PESC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_OVER_CURRENT:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_C_PORT_RESET:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRSC);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_SET_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSS);
+			len = 0;
+			break;
+
+		case RH_PORT_RESET:
+			/* Spin until any current reset finishes */
+			while (1) {
+				tmp =
+				    isp116x_read_reg32(isp116x,
+						       HCRHPORT1 + wIndex - 1);
+				if (!(tmp & RH_PS_PRS))
+					break;
+				wait_ms(1);
+			}
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRS);
+			wait_ms(10);
+
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PPS);
+			len = 0;
+			break;
+
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PES);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_ADDRESS:
+		DEBUG_HOST("RH_SET_ADDRESS");
+
+		rh_devnum = wValue;
+		len = 0;
+		break;
+
+	case RH_GET_DESCRIPTOR:
+		DEBUG_HOST("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength);
+
+		switch (wValue) {
+		case (USB_DT_DEVICE << 8):	/* device descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_dev_des),
+						wLength));
+			data_buf = root_hub_dev_des;
+			break;
+
+		case (USB_DT_CONFIG << 8):	/* configuration descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_config_des),
+						wLength));
+			data_buf = root_hub_config_des;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x00):	/* string 0 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index0),
+						wLength));
+			data_buf = root_hub_str_index0;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x01):	/* string 1 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index1),
+						wLength));
+			data_buf = root_hub_str_index1;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		DEBUG_HOST("RH_GET_DESCRIPTOR | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+		data_buf[0] = 0x09;	/* min length; */
+		data_buf[1] = 0x29;
+		data_buf[2] = tmp & RH_A_NDP;
+		data_buf[3] = 0;
+		if (tmp & RH_A_PSM)	/* per-port power switching? */
+			data_buf[3] |= 0x01;
+		if (tmp & RH_A_NOCP)	/* no overcurrent reporting? */
+			data_buf[3] |= 0x10;
+		else if (tmp & RH_A_OCPM)	/* per-port overcurrent rep? */
+			data_buf[3] |= 0x08;
+
+		/* Corresponds to data_buf[4-7] */
+		datab[1] = 0;
+		data_buf[5] = (tmp & RH_A_POTPGT) >> 24;
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+		data_buf[7] = tmp & RH_B_DR;
+		if (data_buf[2] < 7)
+			data_buf[8] = 0xff;
+		else {
+			data_buf[0] += 2;
+			data_buf[8] = (tmp & RH_B_DR) >> 8;
+			data_buf[10] = data_buf[9] = 0xff;
+		}
+
+		len = min1_t(unsigned int, leni,
+			    min2_t(unsigned int, data_buf[0], wLength));
+		break;
+
+	case RH_GET_CONFIGURATION:
+		DEBUG_HOST("RH_GET_CONFIGURATION");
+
+		*(__u8 *) data_buf = 0x01;
+		len = 1;
+		break;
+
+	case RH_SET_CONFIGURATION:
+		DEBUG_HOST("RH_SET_CONFIGURATION");
+
+		isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC);
+		len = 0;
+		break;
+
+	default:
+		ERR("*** *** *** unsupported root hub command *** *** ***");
+		stat = USB_ST_STALLED;
+	}
+
+	len = min1_t(int, len, leni);
+	if (buffer != data_buf)
+		memcpy(buffer, data_buf, len);
+
+	dev->act_len = len;
+	dev->status = stat;
+	DEBUG_HOST("dev act_len %d, status %ld", dev->act_len, dev->status);
+
+	dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)");
+
+	return stat;
+}
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	DEBUG_HOST("dev=%p pipe=%#lx buf=%p size=%d int=%d",
+	    dev, pipe, buffer, len, interval);
+
+	return -1;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	int devnum = usb_pipedevice(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int dir_in = usb_pipein(pipe);
+	int done, ret;
+	
+	
+	/* Control message is for the HUB? */
+	if (devnum == rh_devnum)
+		return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup);
+
+	/* Ok, no HUB message so send the message to the device */
+
+	/* Setup phase */
+	DEBUG_HOST("--- SETUP PHASE --------------------------------");
+	usb_settoggle(dev, epnum, 1, 0);
+	
+	
+	ret = isp116x_submit_job(dev, pipe,
+				PTD_DIR_SETUP,
+				 setup, sizeof(struct devrequest));
+	if (ret < 0) {
+		DEBUG_HOST("control setup phase error (ret = %d", ret);
+		return -1;
+	}
+
+	/* Data phase */
+	DEBUG_HOST("--- DATA PHASE ---------------------------------");
+	done = 0;
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	while (done < len) {
+		ret = isp116x_submit_job(dev, pipe,
+					 dir_in ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+		if (ret < 0) {
+			DEBUG_HOST("control data phase error (ret = %d)", ret);
+			return -1;
+		}
+		done += ret;
+
+		if (dir_in && ret < max)	/* short packet */
+			break;
+	}
+
+	/* Status phase */
+	DEBUG_HOST("--- STATUS PHASE -------------------------------");
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	ret = isp116x_submit_job(dev, pipe,
+				 !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0);
+	if (ret < 0) {
+		DEBUG_HOST("control status phase error (ret = %d", ret);
+		return -1;
+	}
+
+	dev->act_len = done;
+
+	dump_msg(dev, pipe, buffer, len, "DEV(ret)");
+
+	return done;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int dir_out = usb_pipeout(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int done, ret;
+	
+	DEBUG_HOST("--- BULK ---------------------------------------");
+	DEBUG_HOST("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d",
+	    usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out);
+
+	done = 0;
+	while (done < len) {
+
+		ret = isp116x_submit_job(dev, pipe,
+					 !dir_out ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+
+		if (ret < 0) {
+			DEBUG_HOST("error on bulk message (ret = %d)", ret);
+			return -1;
+		}
+
+		done += ret;
+
+		if (!dir_out && ret < max)	/* short packet */
+			break;
+	}
+
+	dev->act_len = done;
+
+	return 0;
+}
+
+/* --- Basic functions ----------------------------------------------------- */
+
+
+#if 0
+/* GALVEZ: Test function */
+static int GALVEZ_test_function( struct isp116x *isp116x )
+{
+	short rwc;
+
+	rwc = isp116x_read_reg16(isp116x, HCCONTROL) & HCCONTROL_RWC;
+	if (rwc) {
+		INFO ("remote wake-up supported \n\r");
+	}
+	return 0;
+
+}
+#endif
+
+static int isp116x_sw_reset(struct isp116x *isp116x)
+{
+	int retries = 15;
+	int ret = 0;
+
+	DEBUG_HOST("");
+
+	isp116x->disabled = 1;
+
+	isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC);
+	isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR);
+	
+	while (--retries) {
+		/* It usually resets within 1 ms */
+		/* GALVEZ: not enough for TOS, try 7 ms */
+		wait_ms(7);
+		if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR))
+			break;
+	}
+	
+	if (!retries) {
+		ERR("software reset timeout");
+		ret = -1;
+	}
+
+#if 0
+	/* GALVEZ: DEBUG SOFTWARE RESET */
+		
+	retries = 5000;
+	
+	while (--retries){
+		if ((isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) {
+			INFO ("HCR: 1 retries: %d\n\r",retries);
+		}
+	}
+#endif /* END DEBUG */
+
+	return ret;
+}
+
+static int isp116x_reset(struct isp116x *isp116x)
+{
+	unsigned long t;
+	u16 clkrdy = 0;
+	int ret, timeout = 15;/* ms
+				* Galvez: 15 ms sometimes isn't enough,
+				* for EtherNat under TOS ??????? increased to 150 ms 
+				*/ 
+
+	DEBUG_HOST("");
+
+	ret = isp116x_sw_reset(isp116x);
+
+	if (ret)
+		return ret;
+
+	for (t = 0; t < timeout; t++) {
+		clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY;
+		if (clkrdy)
+			break;
+		wait_ms(1);
+	}
+	if (!clkrdy) {
+		ERR("clock not ready after %dms", timeout);
+		/* After sw_reset the clock won't report to be ready, if
+		   H_WAKEUP pin is high. */
+		ERR("please make sure that the H_WAKEUP pin is pulled low!");
+		ret = -1;
+	}
+	return ret;
+}
+
+static void isp116x_stop(struct isp116x *isp116x)
+{
+	u32 val;
+	
+	DEBUG_HOST("");
+	
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	/* Switch off ports' power, some devices don't come up
+	   after next 'start' without this */
+	val = isp116x_read_reg32(isp116x, HCRHDESCA);
+	val &= ~(RH_A_NPS | RH_A_PSM);
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS);
+	
+	isp116x_sw_reset(isp116x);
+	
+#if 0	
+	/* EtherNAT control register, disamble interrupt for USB */
+	u8 *cpld_cr, value;
+	p = SuperFromUser();
+	cpld_cr = ETHERNAT_CPLD_CR;
+	value = *cpld_cr;
+	INFO ("ETHERNAT_CPLD_CR %x", value);
+	value &= 0xFB;
+	INFO ("ETHERNAT_CPLD_CR %x", value);
+	*cpld_cr = value;
+	SuperToUser(p);
+#endif
+}
+
+/*
+ *  Configure the chip. The chip must be successfully reset by now.
+ */
+static int isp116x_start(struct isp116x *isp116x)
+{
+	struct isp116x_platform_data *board = isp116x->board;
+	u32 val;
+	
+	DEBUG_HOST("");
+
+	/* Clear interrupt status and disable all interrupt sources */
+	isp116x_write_reg16(isp116x, HCuPINT, 0xff);
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE);
+	isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE);
+
+	/* Hardware configuration */
+	val = HCHWCFG_DBWIDTH(1);
+
+	if (board->sel15Kres)
+		val |= HCHWCFG_15KRSEL;
+	/* Remote wakeup won't work without working clock */
+	if (board->remote_wakeup_enable)
+		val |= HCHWCFG_CLKNOTSTOP;
+	if (board->oc_enable)
+		val |= HCHWCFG_ANALOG_OC;
+	isp116x_write_reg16(isp116x, HCHWCFG, val);
+
+#if 0
+	/* EtherNAT control register, enable interrupt for USB */
+	u8 *cpld_cr, value;
+	p = SuperFromUser();
+	cpld_cr = ETHERNAT_CPLD_CR;
+	INFO ("%s: ETHERNAT_CPLD_CR reg: %x",__FUNCTION__, *cpld_cr);
+	value = *cpld_cr;
+	value |= 0x04;
+	Bconin(DEV_CONSOLE);
+	*cpld_cr = value;
+	Bconin(DEV_CONSOLE);
+	INFO ("%s: ETHERNAT_CPLD_CR reg:%x", __FUNCTION__, *cpld_cr);
+	SuperToUser(p);
+#endif	
+	/* --- Root hub configuration */
+	val = (25 << 24) & RH_A_POTPGT;
+	/* AN10003_1.pdf recommends RH_A_NPS (no power switching) to
+	   be always set. Yet, instead, we request individual port
+	   power switching. */
+	val |= RH_A_PSM;
+	/* Report overcurrent per port */
+	val |= RH_A_OCPM;
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+	val = RH_B_PPCM;
+	isp116x_write_reg32(isp116x, HCRHDESCB, val);
+	isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+	val = 0;
+	if (board->remote_wakeup_enable)
+		val |= RH_HS_DRWE;
+	isp116x_write_reg32(isp116x, HCRHSTATUS, val);
+	isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+	isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf);
+
+	/* Go operational */
+	val = HCCONTROL_USB_OPER;
+	if (board->remote_wakeup_enable)
+		val |= HCCONTROL_RWE;
+	isp116x_write_reg32(isp116x, HCCONTROL, val);
+
+	/* Disable ports to avoid race in device enumeration */
+	isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS);
+	isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS);
+
+	isp116x_show_regs(isp116x);
+
+	isp116x->disabled = 0;
+
+	return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+
+
+int isp116x_check_id(struct isp116x *isp116x)
+{
+	u16 val;
+
+	val = isp116x_read_reg16(isp116x, HCCHIPID);
+	DEBUG_HOST("chip ID: %04x", val);
+
+	if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) {
+		printf("invalid chip ID %04x", val);
+		return -1;
+	}
+
+	return 0;
+}
+
+
+int usb_lowlevel_init(void)
+{
+//	u16 val;
+
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	got_rhsc = rh_devnum = 0;
+
+	/* Init device registers addr */
+	isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR;
+	isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;
+
+	/* Setup specific board settings */
+#ifdef ISP116X_HCD_SEL15kRES
+	isp116x_board.sel15Kres = 1;
+#endif
+#ifdef ISP116X_HCD_OC_ENABLE
+	isp116x_board.oc_enable = 1;
+#endif
+#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+	isp116x_board.remote_wakeup_enable = 1;
+#endif
+	isp116x->board = &isp116x_board;
+
+	/* Try to get ISP116x silicon chip ID */
+	if (isp116x_check_id(isp116x) < 0)
+		return (-1);
+		
+	isp116x->disabled = 1;
+	isp116x->sleeping = 0;
+
+	isp116x_reset(isp116x);
+	isp116x_start(isp116x);
+
+	return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	if (!isp116x->disabled)
+		isp116x_stop(isp116x);
+
+	return 0;
+}
diff --git a/usb/store/host/ethernat/isp116x.h b/usb/store/host/ethernat/isp116x.h
new file mode 100644
index 0000000..26678ba
--- /dev/null
+++ b/usb/store/host/ethernat/isp116x.h
@@ -0,0 +1,542 @@
+/*
+ * Modified for Atari-EtherNat by David Gálvez 2010
+ *
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ETHERNAT_ISP116X_H
+#define _ETHERNAT_ISP116X_H
+
+
+#define ERR(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define WARN(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define INFO(fmt, args...)	printf("isp116x: " fmt "\n\r" , ## args)
+
+/* ------------------------------------------------------------------------- */
+
+/* us of 1ms frame */
+#define  MAX_LOAD_LIMIT		850
+
+/* Full speed: max # of bytes to transfer for a single urb
+   at a time must be < 1024 && must be multiple of 64.
+   832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED	832
+
+/* Low speed: there is no reason to schedule in very big
+   chunks; often the requested long transfers are for
+   string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED	64
+
+/* Bytetime (us), a rough indication of how much time it
+   would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED	1
+#define BYTE_TIME_LOWSPEED	20
+
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE	4096
+#define ISP116x_ITL_BUFSIZE	0
+#define ISP116x_ATL_BUFSIZE	((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+
+#define ISP116x_WRITE_OFFSET	0x80
+
+/* --- ISP116x address registers in EtherNAT --------------------------------*/
+
+#define ISP116X_HCD_ADDR	0x80000016
+#define ISP116X_HCD_DATA	0x80000012
+#define ETHERNAT_CPLD_CR	0x80000023   /* 0x80000023 - 1 */
+
+/* --- ISP116x registers/bits ---------------------------------------------- */
+
+#define	HCREVISION	0x00
+#define	HCCONTROL	0x01
+#define		HCCONTROL_HCFS	(3 << 6)	/* host controller
+						   functional state */
+#define		HCCONTROL_USB_RESET	(0 << 6)
+#define		HCCONTROL_USB_RESUME	(1 << 6)
+#define		HCCONTROL_USB_OPER	(2 << 6)
+#define		HCCONTROL_USB_SUSPEND	(3 << 6)
+#define		HCCONTROL_RWC	(1 << 9)	/* remote wakeup connected */
+#define		HCCONTROL_RWE	(1 << 10)	/* remote wakeup enable */
+#define	HCCMDSTAT	0x02
+#define		HCCMDSTAT_HCR	(1 << 0)	/* host controller reset */
+#define		HCCMDSTAT_SOC	(3 << 16)	/* scheduling overrun count */
+#define	HCINTSTAT	0x03
+#define		HCINT_SO	(1 << 0)	/* scheduling overrun */
+#define		HCINT_WDH	(1 << 1)	/* writeback of done_head */
+#define		HCINT_SF	(1 << 2)	/* start frame */
+#define		HCINT_RD	(1 << 3)	/* resume detect */
+#define		HCINT_UE	(1 << 4)	/* unrecoverable error */
+#define		HCINT_FNO	(1 << 5)	/* frame number overflow */
+#define		HCINT_RHSC	(1 << 6)	/* root hub status change */
+#define		HCINT_OC	(1 << 30)	/* ownership change */
+#define		HCINT_MIE	(1 << 31)	/* master interrupt enable */
+#define	HCINTENB	0x04
+#define	HCINTDIS	0x05
+#define	HCFMINTVL	0x0d
+#define	HCFMREM		0x0e
+#define	HCFMNUM		0x0f
+#define	HCLSTHRESH	0x11
+#define	HCRHDESCA	0x12
+#define		RH_A_NDP	(0x3 << 0)	/* # downstream ports */
+#define		RH_A_PSM	(1 << 8)	/* power switching mode */
+#define		RH_A_NPS	(1 << 9)	/* no power switching */
+#define		RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define		RH_A_OCPM	(1 << 11)	/* overcurrent protection
+						   mode */
+#define		RH_A_NOCP	(1 << 12)	/* no overcurrent protection */
+#define		RH_A_POTPGT	(0xff << 24)	/* power on -> power good
+						   time */
+#define	HCRHDESCB	0x13
+#define		RH_B_DR		(0xffff << 0)	/* device removable flags */
+#define		RH_B_PPCM	(0xffff << 16)	/* port power control mask */
+#define	HCRHSTATUS	0x14
+#define		RH_HS_LPS	(1 << 0)	/* local power status */
+#define		RH_HS_OCI	(1 << 1)	/* over current indicator */
+#define		RH_HS_DRWE	(1 << 15)	/* device remote wakeup
+						   enable */
+#define		RH_HS_LPSC	(1 << 16)	/* local power status change */
+#define		RH_HS_OCIC	(1 << 17)	/* over current indicator
+						   change */
+#define		RH_HS_CRWE	(1 << 31)	/* clear remote wakeup
+						   enable */
+#define	HCRHPORT1	0x15
+#define		RH_PS_CCS	(1 << 0)	/* current connect status */
+#define		RH_PS_PES	(1 << 1)	/* port enable status */
+#define		RH_PS_PSS	(1 << 2)	/* port suspend status */
+#define		RH_PS_POCI	(1 << 3)	/* port over current
+						   indicator */
+#define		RH_PS_PRS	(1 << 4)	/* port reset status */
+#define		RH_PS_PPS	(1 << 8)	/* port power status */
+#define		RH_PS_LSDA	(1 << 9)	/* low speed device attached */
+#define		RH_PS_CSC	(1 << 16)	/* connect status change */
+#define		RH_PS_PESC	(1 << 17)	/* port enable status change */
+#define		RH_PS_PSSC	(1 << 18)	/* port suspend status
+						   change */
+#define		RH_PS_OCIC	(1 << 19)	/* over current indicator
+						   change */
+#define		RH_PS_PRSC	(1 << 20)	/* port reset status change */
+#define		HCRHPORT_CLRMASK	(0x1f << 16)
+#define	HCRHPORT2	0x16
+#define	HCHWCFG		0x20
+#define		HCHWCFG_15KRSEL		(1 << 12)
+#define		HCHWCFG_CLKNOTSTOP	(1 << 11)
+#define		HCHWCFG_ANALOG_OC	(1 << 10)
+#define		HCHWCFG_DACK_MODE	(1 << 8)
+#define		HCHWCFG_EOT_POL		(1 << 7)
+#define		HCHWCFG_DACK_POL	(1 << 6)
+#define		HCHWCFG_DREQ_POL	(1 << 5)
+#define		HCHWCFG_DBWIDTH_MASK	(0x03 << 3)
+#define		HCHWCFG_DBWIDTH(n)	(((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define		HCHWCFG_INT_POL		(1 << 2)
+#define		HCHWCFG_INT_TRIGGER	(1 << 1)
+#define		HCHWCFG_INT_ENABLE	(1 << 0)
+#define	HCDMACFG	0x21
+#define		HCDMACFG_BURST_LEN_MASK	(0x03 << 5)
+#define		HCDMACFG_BURST_LEN(n)	(((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define		HCDMACFG_BURST_LEN_1	HCDMACFG_BURST_LEN(0)
+#define		HCDMACFG_BURST_LEN_4	HCDMACFG_BURST_LEN(1)
+#define		HCDMACFG_BURST_LEN_8	HCDMACFG_BURST_LEN(2)
+#define		HCDMACFG_DMA_ENABLE	(1 << 4)
+#define		HCDMACFG_BUF_TYPE_MASK	(0x07 << 1)
+#define		HCDMACFG_CTR_SEL	(1 << 2)
+#define		HCDMACFG_ITLATL_SEL	(1 << 1)
+#define		HCDMACFG_DMA_RW_SELECT	(1 << 0)
+#define	HCXFERCTR	0x22
+#define	HCuPINT		0x24
+#define		HCuPINT_SOF		(1 << 0)
+#define		HCuPINT_ATL		(1 << 1)
+#define		HCuPINT_AIIEOT		(1 << 2)
+#define		HCuPINT_OPR		(1 << 4)
+#define		HCuPINT_SUSP		(1 << 5)
+#define		HCuPINT_CLKRDY		(1 << 6)
+#define	HCuPINTENB	0x25
+#define	HCCHIPID	0x27
+#define		HCCHIPID_MASK		0xff00
+#define		HCCHIPID_MAGIC		0x6100
+#define	HCSCRATCH	0x28
+#define	HCSWRES		0x29
+#define		HCSWRES_MAGIC		0x00f6
+#define	HCITLBUFLEN	0x2a
+#define	HCATLBUFLEN	0x2b
+#define	HCBUFSTAT	0x2c
+#define		HCBUFSTAT_ITL0_FULL	(1 << 0)
+#define		HCBUFSTAT_ITL1_FULL	(1 << 1)
+#define		HCBUFSTAT_ATL_FULL	(1 << 2)
+#define		HCBUFSTAT_ITL0_DONE	(1 << 3)
+#define		HCBUFSTAT_ITL1_DONE	(1 << 4)
+#define		HCBUFSTAT_ATL_DONE	(1 << 5)
+#define	HCRDITL0LEN	0x2d
+#define	HCRDITL1LEN	0x2e
+#define	HCITLPORT	0x40
+#define	HCATLPORT	0x41
+
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p)	(((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v)		(((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p)	(((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v)		(((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p)	(((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v)		(((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p)		(((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v)		(((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p)		(((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v)		(((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p)		(((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v)		(((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p)		(((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v)		(((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p)		(((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v)		(((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p)		(((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v)		(((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p)		(((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v)		(((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p)		(((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v)		(((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p)		(((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v)		(((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p)		(((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v)		(((v) << 7) & PTD_FMT_MSK)
+
+/*  Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+    /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+    /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED     0x0F
+
+/* ------------------------------------------------------------------------- */
+
+#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
+#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
+
+/* Philips transfer descriptor */
+struct ptd {
+	u16 count;
+#define	PTD_COUNT_MSK	(0x3ff << 0)
+#define	PTD_TOGGLE_MSK	(1 << 10)
+#define	PTD_ACTIVE_MSK	(1 << 11)
+#define	PTD_CC_MSK	(0xf << 12)
+	u16 mps;
+#define	PTD_MPS_MSK	(0x3ff << 0)
+#define	PTD_SPD_MSK	(1 << 10)
+#define	PTD_LAST_MSK	(1 << 11)
+#define	PTD_EP_MSK	(0xf << 12)
+	u16 len;
+#define	PTD_LEN_MSK	(0x3ff << 0)
+#define	PTD_DIR_MSK	(3 << 10)
+#define	PTD_DIR_SETUP	(0)
+#define	PTD_DIR_OUT	(1)
+#define	PTD_DIR_IN	(2)
+#define	PTD_B5_5_MSK	(1 << 13)
+	u16 faddr;
+#define	PTD_FA_MSK	(0x7f << 0)
+#define	PTD_FMT_MSK	(1 << 7)
+} __attribute__ ((packed, aligned(2)));
+
+struct isp116x_ep {
+	struct usb_device *udev;
+	struct ptd ptd;
+
+	u8 maxpacket;
+	u8 epnum;
+	u8 nextpid;
+
+	u16 length;		/* of current packet */
+	unsigned char *data;	/* to databuf */
+
+	u16 error_count;
+};
+
+/* URB struct */
+#define N_URB_TD		48
+#define URB_DEL			1
+typedef struct {
+	struct isp116x_ep *ed;
+	void *transfer_buffer;	/* (in) associated data buffer */
+	int actual_length;	/* (return) actual transfer length */
+	unsigned long pipe;	/* (in) pipe information */
+#if 0
+	int state;
+#endif
+} urb_priv_t;
+
+struct isp116x_platform_data {
+	/* Enable internal resistors on downstream ports */
+	unsigned sel15Kres:1;
+	/* On-chip overcurrent detection */
+	unsigned oc_enable:1;
+	/* Enable wakeup by devices on usb bus (e.g. wakeup
+	   by attachment/detachment or by device activity
+	   such as moving a mouse). When chosen, this option
+	   prevents stopping internal clock, increasing
+	   thereby power consumption in suspended state. */
+	unsigned remote_wakeup_enable:1;
+};
+
+struct isp116x {
+	u16 *addr_reg;
+	u16 *data_reg;
+
+	struct isp116x_platform_data *board;
+
+	struct dentry *dentry;
+	unsigned long stat1, stat2, stat4, stat8, stat16;
+
+	/* Status flags */
+	unsigned disabled:1;
+	unsigned sleeping:1;
+
+	/* Root hub registers */
+	u32 rhdesca;
+	u32 rhdescb;
+	u32 rhstatus;
+	u32 rhport[2];
+
+	/* Schedule for the current frame */
+	struct isp116x_ep *atl_active;
+	int atl_buflen;
+	int atl_bufshrt;
+	int atl_last_dir;
+	int atl_finishing;
+};
+
+/* ------------------------------------------------- */
+
+/* Inter-io delay (ns). The chip is picky about access timings; it
+ * expects at least:
+ * 150ns delay between consecutive accesses to DATA_REG,
+ * 300ns delay between access to ADDR_REG and DATA_REG
+ * OE, WE MUST NOT be changed during these intervals
+ */
+#if defined(UDELAY)
+#define	isp116x_delay(h,d)	udelay(d)
+#else
+#define	isp116x_delay(h,d)	do {} while (0)
+#endif
+
+#include "../../super.h"	/*
+	 		 * Functions to call supervisor mode
+		 	 * Super() in TOS is buggy
+			 */
+
+u32 p;	
+			 
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+//	p = SuperFromUser( );
+	__raw_writew(reg & 0xff, isp116x->addr_reg );
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+//	p = SuperFromUser( );
+	writew(val, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+//	p = SuperFromUser( );
+	__raw_writew(val, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+//	p = SuperFromUser( );
+	val = readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+//	p = SuperFromUser( );
+	val = __raw_readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+/*
+ * Added for EtherNat, to write HC registers without swaping them
+ * EtherNat already swap them by hardware (i suppose.....)
+ */
+static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	__raw_writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	__raw_writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+/***********************************************/
+
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+//	p = SuperFromUser( );
+	val = (u32) readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+/*
+ * Added for EtherNat, to read HC registers without swaping them
+ * EtherNat already swap them by hardware (i suppose.....)
+ */
+static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+//	p = SuperFromUser( );
+	val = (u32) __raw_readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) __raw_readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+/*******************************************************************/
+
+/* Let's keep register access functions out of line. Hint:
+   we wait at least 150 ns at every access.
+*/
+
+/* with EtherNat use raw_read to avoid swaping bytes*/
+
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data16(isp116x);
+}
+
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data32(isp116x);
+}
+
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff));
+}
+
+/* with Etehrnat used raw_write to avoid swaping bytes by software */
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data32(isp116x, (u32) val);
+}
+
+/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
+
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+#endif /* _ETHERNAT_ISP116X_H */
diff --git a/usb/store/host/netusbee/isp116x-hcd.c b/usb/store/host/netusbee/isp116x-hcd.c
new file mode 100644
index 0000000..c26e6e1
--- /dev/null
+++ b/usb/store/host/netusbee/isp116x-hcd.c
@@ -0,0 +1,1561 @@
+/*
+ * Modified for Atari-NetUSBee by David Gálvez 2010
+ *
+ * ISP116x HCD (Host Controller Driver) for u-boot.
+ *
+ * Copyright (C) 2006-2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2006-2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
+ * (original copyright message follows):
+ *
+ *    (C) Copyright 2004
+ *    Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ *    This code is based on linux driver for sl811hs chip, source at
+ *    drivers/usb/host/sl811.c:
+ *
+ *    SL811 Host Controller Interface driver for USB.
+ *
+ *    Copyright (c) 2003/06, Courage Co., Ltd.
+ *
+ *    Based on:
+ *         1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap,
+ *           Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber,
+ *           Adam Richter, Gregory P. Smith;
+ *         2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com>
+ *         3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c"
+ * (original copyright message follows):
+ *
+ *    URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ *    (C) Copyright 2003
+ *    Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ *    Note: Part of this code has been derived from linux
+ */
+
+#include "../../config.h"
+#include "../../asm-m68k/io.h"
+#include "../../usb.h"
+#include "../../debug.h"
+
+void udelay (unsigned long usec);
+
+//extern void boot_printf (const char *fmt, ...);
+
+
+/*
+ * ISP116x chips require certain delays between accesses to its
+ * registers. The following timing options exist.
+ *
+ * 1. Configure your memory controller (the best)
+ * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
+ *
+ * Value is in microseconds.
+ */
+#ifdef ISP116X_HCD_USE_UDELAY
+#define UDELAY		1
+#endif
+
+/*
+ * On some (slowly?) machines an extra delay after data packing into
+ * controller's FIFOs is required, * otherwise you may get the following
+ * error:
+ *
+ *   uboot> usb start
+ *   (Re)start USB...
+ *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
+ *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
+ *
+ *         USB device not responding, giving up (status=4)
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         3 USB Device(s) found
+ *                scanning bus for storage devices... 0 Storage Device(s) found
+ *
+ * Value is in milliseconds.
+ */
+#ifdef ISP116X_HCD_USE_EXTRA_DELAY
+#define EXTRA_DELAY	50
+#endif
+
+/*
+ * Enable the following defines if you wish enable extra debugging messages.
+ * Normal debug messages controlled from config.h.
+ */
+
+//#define TRACE		/* enable tracing code */
+//#define VERBOSE		/* verbose debugging messages */
+
+#include "isp116x.h"
+
+#define DRIVER_VERSION	"08 Jan 2007"
+static const char hcd_name[] = "isp116x-hcd";
+
+struct isp116x isp116x_dev;
+struct isp116x_platform_data isp116x_board;
+static int got_rhsc;		/* root hub status change */
+struct usb_device *devgone;	/* device which was disconnected */
+static int rh_devnum;		/* address of Root Hub endpoint */
+
+/* ------------------------------------------------------------------------- */
+
+#define ALIGN(x,a)	(((x)+(a)-1UL)&~((a)-1UL))
+#define min1_t(type,x,y)	\
+	({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
+
+/*Galvez: added to avoid shadow warnings */
+#define min2_t(type,x,y)	\
+	({ type __a = (x); type __b = (y); __a < __b ? __a : __b; })
+
+/* ------------------------------------------------------------------------- */
+
+
+static int isp116x_reset(struct isp116x *isp116x);
+
+/* --- Debugging functions ------------------------------------------------- */
+
+#define isp116x_show_reg(d, r) {				\
+	if ((r) < 0x20) {					\
+		DEBUG_HOST("%-12s[%02x]: %08x", #r,			\
+			r, isp116x_read_reg32(d, r));		\
+	} else {						\
+		DEBUG_HOST("%-12s[%02x]:     %04x", #r,		\
+			r, isp116x_read_reg16(d, r));		\
+	}							\
+}
+
+#define isp116x_show_regs(d) {					\
+	isp116x_show_reg(d, HCREVISION);			\
+	isp116x_show_reg(d, HCCONTROL);				\
+	isp116x_show_reg(d, HCCMDSTAT);				\
+	isp116x_show_reg(d, HCINTSTAT);				\
+	isp116x_show_reg(d, HCINTENB);				\
+	isp116x_show_reg(d, HCFMINTVL);				\
+	isp116x_show_reg(d, HCFMREM);				\
+	isp116x_show_reg(d, HCFMNUM);				\
+	isp116x_show_reg(d, HCLSTHRESH);			\
+	isp116x_show_reg(d, HCRHDESCA);				\
+	isp116x_show_reg(d, HCRHDESCB);				\
+	isp116x_show_reg(d, HCRHSTATUS);			\
+	isp116x_show_reg(d, HCRHPORT1);				\
+	isp116x_show_reg(d, HCRHPORT2);				\
+	isp116x_show_reg(d, HCHWCFG);				\
+	isp116x_show_reg(d, HCDMACFG);				\
+	isp116x_show_reg(d, HCXFERCTR);				\
+	isp116x_show_reg(d, HCuPINT);				\
+	isp116x_show_reg(d, HCuPINTENB);			\
+	isp116x_show_reg(d, HCCHIPID);				\
+	isp116x_show_reg(d, HCSCRATCH);				\
+	isp116x_show_reg(d, HCITLBUFLEN);			\
+	isp116x_show_reg(d, HCATLBUFLEN);			\
+	isp116x_show_reg(d, HCBUFSTAT);				\
+	isp116x_show_reg(d, HCRDITL0LEN);			\
+	isp116x_show_reg(d, HCRDITL1LEN);			\
+}
+
+#if defined(TRACE)
+
+static int isp116x_get_current_frame_number(struct usb_device *usb_dev)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	return isp116x_read_reg32(isp116x, HCFMNUM);
+}
+
+static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		     int len, char *str)
+{
+#if defined(VERBOSE)
+	int i;
+#endif
+	DEBUG_HOST("%s URB:[%4x] dev:%2ld,ep:%2ld-%c,type:%s,len:%d stat:%#lx",
+	    str,
+	    isp116x_get_current_frame_number(dev),
+	    usb_pipedevice(pipe),
+	    usb_pipeendpoint(pipe),
+	    usb_pipeout(pipe) ? 'O' : 'I',
+	    usb_pipetype(pipe) < 2 ?
+	    (usb_pipeint(pipe) ?
+	     "INTR" : "ISOC") :
+	    (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status);
+#if defined(VERBOSE)
+	debug_init ("usb.log");
+	if (len > 0 && buffer) {
+		debug(__FILE__ ": data(%d):", len);
+		for (i = 0; i < 16 && i < len; i++)
+			debug(" %02x", ((__u8 *) buffer)[i]);
+		debug("%s\r\n", i < len ? "..." : "");
+	}
+	debug_exit ( );
+#endif
+}
+
+#define PTD_DIR_STR(ptd)  ({char __c;		\
+	switch(PTD_GET_DIR(ptd)){		\
+	case 0:  __c = 's'; break;		\
+	case 1:  __c = 'o'; break;		\
+	default: __c = 'i'; break;		\
+	}; __c;})
+
+/*
+  Dump PTD info. The code documents the format
+  perfectly, right :)
+*/
+static inline void dump_ptd(struct ptd *ptd)
+{
+#if defined(VERBOSE)
+	int k;
+#endif
+
+	DEBUG_HOST("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x",
+	    PTD_GET_CC(ptd),
+	    PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
+	    PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
+	    PTD_GET_TOGGLE(ptd),
+	    PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
+#if defined(VERBOSE)
+	debug_init ("usb.log");
+	debug("isp116x: %s: PTD(byte): ", __FUNCTION__);
+	for (k = 0; k < sizeof(struct ptd); ++k) {
+		debug("%02x ", ((u8 *) ptd)[k]);
+	}
+	debug("\n\r");
+	debug_exit ( );
+#endif
+}
+
+static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type)
+{
+#if defined(VERBOSE)
+	int k;
+	
+	debug_init ("usb.log");
+	if (type == 0 /* 0ut data */ ) {
+		debug("isp116x: %s: out data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_LEN(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	if (type == 1 /* 1n data */ ) {
+		debug("isp116x: %s: in data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_COUNT(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	
+	debug_exit ( );
+	
+	if (PTD_GET_LAST(ptd)) {
+		DEBUG_HOST("--- last PTD ---");
+	}
+#endif
+}
+
+#else
+
+#define dump_msg(dev, pipe, buffer, len, str)			do { } while (0)
+#define dump_pkt(dev, pipe, buffer, len, setup, str, small)	do {} while (0)
+
+#define dump_ptd(ptd)			do {} while (0)
+#define dump_ptd_data(ptd, buf, type)	do {} while (0)
+
+#endif
+
+/* --- Virtual Root Hub ---------------------------------------------------- */
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x10,			/*  __u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x00,			/*  __u8  iManufacturer; */
+	0x01,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+	/* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+	/* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x00,			/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x02,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] = {
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+	0x22,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'I',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'S',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'P',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'6',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'x',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+};
+
+/*
+ * Hub class-specific descriptor is constructed dynamically
+ */
+
+/* --- Virtual root hub management functions ------------------------------- */
+
+static int rh_check_port_status(struct isp116x *isp116x)
+{
+	u32 temp, ndp, i;
+	int res;
+
+	res = -1;
+	temp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+	ndp = (temp & RH_A_NDP);
+	for (i = 0; i < ndp; i++) {
+		temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+		     (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+/* --- HC management functions --------------------------------------------- */
+
+/* Write len bytes to fifo, pad till 32-bit boundary
+ */
+static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+	
+/* For NetUSBee, take the raw_write out in write functions, here we don't
+ * like that NetUSBee swap the bytes for us, so we swap them before we send
+ * them, then the bytes will arrive to the USB device with the correct positions
+ */
+ 	if ((unsigned long)dp2 & 1) {
+	DEBUG_HOST("---not aligned ---");
+		/* not aligned */
+		for (; len > 1; len -= 2) {
+			w = *dp++;
+			w |= *dp++ << 8;
+			isp116x_write_data16(isp116x, w);
+		}
+		if (len)
+			isp116x_write_data16(isp116x, (u16) * dp);
+	} else {
+	DEBUG_HOST("---aligned ---");
+		/* aligned */
+		for (; len > 1; len -= 2)
+			isp116x_write_data16(isp116x, *dp2++);
+		if (len){DEBUG_HOST("write_data16\r\n"); /*GALVEZ: DEBUG */
+			isp116x_raw_write_data16(isp116x, 0xff & *((u8 *) dp2));}
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_write_data16(isp116x, 0);
+}
+
+/* Read len bytes from fifo and then read till 32-bit boundary
+ */
+static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+
+/* For NetUSBee, take the raw_read out from read functions, we want to swap the bytes
+   to read correct values because NetUSBee swaped the bytes by hardware before we read 
+   them */
+
+	if ((unsigned long)dp2 & 1) {
+		/* not aligned */
+		DEBUG_HOST("---not aligned ---");
+		for (; len > 1; len -= 2) {
+			w = isp116x_read_data16(isp116x);
+			*dp++ = w & 0xff;
+			*dp++ = (w >> 8) & 0xff;
+		}
+		if (len)
+			*dp = 0xff & isp116x_read_data16(isp116x);
+	} else {
+		/* aligned */
+		DEBUG_HOST("---aligned ---");
+		for (; len > 1; len -= 2)
+			*dp2++ = isp116x_read_data16(isp116x);
+		if (len)
+			*(u8 *) dp2 = 0xff & isp116x_raw_read_data16(isp116x);
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_read_data16(isp116x);
+}
+
+/* Write PTD's and data for scheduled transfers into the fifo ram.
+ * Fifo must be empty and ready */
+static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		      unsigned long pipe, struct ptd *ptd, int n, void *data,
+		      int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done;
+
+	DEBUG_HOST("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
+	
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET);
+
+	done = 0;
+	for (i = 0; i < n; i++) {
+		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+
+/* For NetUSBee, use raw_write to don't swap bytes */
+		dump_ptd(&ptd[i]);
+		isp116x_raw_write_data16(isp116x, ptd[i].count);
+		isp116x_raw_write_data16(isp116x, ptd[i].mps);
+		isp116x_raw_write_data16(isp116x, ptd[i].len);
+		isp116x_raw_write_data16(isp116x, ptd[i].faddr);
+
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 0);
+
+		write_ptddata_to_fifo(isp116x,
+				      (__u8 *) data + done,
+				      PTD_GET_LEN(&ptd[i]));
+
+		done += PTD_GET_LEN(&ptd[i]);
+	}
+}
+
+/* Read the processed PTD's and data from fifo ram back to URBs' buffers.
+ * Fifo must be full and done */
+static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		       unsigned long pipe, struct ptd *ptd, int n, void *data,
+		       int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done, cc, ret;
+
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT);
+
+	ret = TD_CC_NOERROR;
+	done = 0;
+	for (i = 0; i < n; i++) {
+		/* Galvez: DEBUG */
+//		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+		DEBUG_HOST("i=%d n=%d - done=%d - len= %d ptd_len=%d\n\r", i,n, done, len, PTD_GET_LEN(&ptd[i]));
+		/*****************/
+		
+	/* For NetUSBee, use raw_read to don't swap bytes */
+		ptd[i].count = isp116x_raw_read_data16(isp116x);
+		ptd[i].mps = isp116x_raw_read_data16(isp116x);
+		ptd[i].len = isp116x_raw_read_data16(isp116x);
+		ptd[i].faddr = isp116x_raw_read_data16(isp116x);
+		dump_ptd(&ptd[i]);
+		
+		/* when cc is 15 the data has not being touch by the HC
+		 * so we have to read all to empty completly the buffer
+		 */
+//		if ( PTD_GET_COUNT(ptd) != 0 || PTD_GET_CC(ptd) == 15 )
+			read_ptddata_from_fifo(isp116x,
+					       (__u8 *) data + done,
+					       PTD_GET_LEN(&ptd[i]));
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 1);
+
+		done += PTD_GET_LEN(&ptd[i]);
+	
+		cc = PTD_GET_CC(&ptd[i]);
+	
+		/* Data underrun means basically that we had more buffer space than
+		 * the function had data. It is perfectly normal but upper levels have
+		 * to know how much we actually transferred.
+		 */
+		if (cc == TD_NOTACCESSED ||
+				(cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
+			ret = cc;
+	}
+
+	DEBUG_HOST("--- unpack buffer %p - %d bytes (fifo %d) count: %d---\n", data, len, buflen, PTD_GET_COUNT(ptd));
+
+	return ret;
+}
+
+/* Interrupt handling
+ */
+static int isp116x_interrupt(struct isp116x *isp116x)
+{
+	u16 irqstat;
+	u32 intstat;
+	int ret = 0;
+
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+	irqstat = isp116x_read_reg16(isp116x, HCuPINT);
+	isp116x_write_reg16(isp116x, HCuPINT, irqstat);
+	DEBUG_HOST(">>>>>> irqstat %x <<<<<<", irqstat);
+	
+	if (irqstat & HCuPINT_ATL) {
+		DEBUG_HOST(">>>>>> HCuPINT_ATL <<<<<<");
+		udelay(500);
+		ret = 1;
+	}
+
+	if (irqstat & HCuPINT_OPR) {
+		intstat = isp116x_read_reg32(isp116x, HCINTSTAT);
+		isp116x_write_reg32(isp116x, HCINTSTAT, intstat);
+		DEBUG_HOST(">>>>>> HCuPINT_OPR %x <<<<<<", intstat);
+
+		if (intstat & HCINT_UE) {
+			ERR("unrecoverable error, controller disabled");
+
+			/* FIXME: be optimistic, hope that bug won't repeat
+			 * often. Make some non-interrupt context restart the
+			 * controller. Count and limit the retries though;
+			 * either hardware or software errors can go forever...
+			 */
+			isp116x_reset(isp116x);
+			ret = -1;
+			return -1;
+		}
+
+		if (intstat & HCINT_RHSC) {
+			got_rhsc = 1;
+			ret = 1;
+			/* When root hub or any of its ports is going
+			   to come out of suspend, it may take more
+			   than 10ms for status bits to stabilize. */
+			wait_ms(20);
+		}
+
+		if (intstat & HCINT_SO) {
+			ERR("schedule overrun");
+			ret = -1;
+		}
+
+		irqstat &= ~HCuPINT_OPR;
+	}
+
+	return ret;
+}
+
+/* With one PTD we can transfer almost 1K in one go;
+ * HC does the splitting into endpoint digestible transactions
+ */
+struct ptd ptd[1];
+
+static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
+{
+	unsigned mpck = usb_maxpacket(dev, pipe);
+
+	/* One PTD can transfer 1023 bytes but try to always
+	 * transfer multiples of endpoint buffer size
+	 */
+	return 1023 / mpck * mpck;
+}
+
+/* Do an USB transfer
+ */
+static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
+			      int dir, void *buffer, int len)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	int type = usb_pipetype(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = usb_maxpacket(dev, pipe);
+	int dir_out = usb_pipeout(pipe);
+	int speed_low = usb_pipeslow(pipe);
+	int i, done = 0, stat, timeout, cc;
+
+	/* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
+	int retries = 500;
+
+
+	DEBUG_HOST("------------------------------------------------");
+	dump_msg(dev, pipe, buffer, len, "SUBMIT");
+	DEBUG_HOST("------------------------------------------------");
+	
+	if (len >= 1024) {
+		ERR("Too big job");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (isp116x->disabled) {
+		ERR("EPIPE");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	/* device pulled? Shortcut the action. */
+	if (devgone == dev) {
+		ERR("ENODEV");
+		dev->status = USB_ST_CRC_ERR;
+		return USB_ST_CRC_ERR;
+	}
+
+	if (!max) {
+		ERR("pipesize for pipe %lx is zero", pipe);
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (type == PIPE_ISOCHRONOUS) {
+		ERR("isochronous transfers not supported");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+	
+	/* FIFO not empty? */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+
+retry:
+	isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
+	/* Prepare the PTD data */
+	ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
+		PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
+	ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
+	ptd->len = PTD_LEN(len) | PTD_DIR(dir);
+	ptd->faddr = PTD_FA(usb_pipedevice(pipe));
+
+	
+retry_same:
+
+	/* FIFO not empty? */ /* GALVEZ: DEBUG */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+//		dev->status = USB_ST_BUF_ERR;
+//		return -1;
+	}
+
+	/* Pack data into FIFO ram */
+	pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+#ifdef EXTRA_DELAY
+	wait_ms(EXTRA_DELAY);
+#endif
+
+	/* Start the data transfer */
+
+	/* Allow more time for a BULK device to react - some are slow */
+	if (usb_pipebulk(pipe))
+		timeout = 5000; /* Galvez: default = 5000 */
+	else
+		timeout = 1000; /* Galvez : netusbee : default = 100 */
+
+	/* Wait for it to complete */
+	for (;;) {
+		/* Check whether the controller is done */
+		stat = isp116x_interrupt(isp116x);
+
+		if (stat < 0) {
+			dev->status = USB_ST_CRC_ERR;
+			break;
+		}
+		if (stat > 0)
+			break;
+
+		/* Check the timeout */
+		if (--timeout)
+			udelay(1);
+		else {
+			ERR("CTL:TIMEOUT ");
+			printf("CTL:TIMEOUT ");
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+	}
+
+	/* We got an Root Hub Status Change interrupt */
+	if (got_rhsc) {
+		isp116x_show_regs(isp116x);
+
+		got_rhsc = 0;
+
+		/* Abuse timeout */
+		timeout = rh_check_port_status(isp116x);
+		if (timeout >= 0) {
+			/*
+			 * FIXME! NOTE! AAAARGH!
+			 * This is potentially dangerous because it assumes
+			 * that only one device is ever plugged in!
+			 */
+			devgone = dev;
+		}
+	}
+
+
+	/* Ok, now we can read transfer status */
+
+	/* FIFO not ready? */
+	if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) {
+		DEBUG_HOST("****** FIFO not ready! ******");
+		printf("****** FIFO not ready! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+	
+	
+	/* Unpack data from FIFO ram */
+	cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+	i = PTD_GET_COUNT(ptd);
+	done += i;
+	buffer += i;
+	len -= i;
+	
+	
+	/* There was some kind of real problem; Prepare the PTD again
+	 * and retry from the failed transaction on
+	 */
+	if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
+	DEBUG_HOST("PROBLEM cc: %d", cc);
+		if (retries >= 100) {
+			retries -= 100;
+			/* The chip will have toggled the toggle bit for the failed
+			 * transaction too. We have to toggle it back.
+			 */
+			usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+	/* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
+	 * the transactions from the first on for the whole frame. It may be busy and we retry
+	 * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
+	 * PTD didn't make it because the function was busy or the frame ended before the PTD
+	 * finished. We prepare the rest of the data and try again.
+	 */
+	else if ( cc == TD_NOTACCESSED ||  PTD_GET_ACTIVE(ptd) ||  ( cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
+		DEBUG_HOST("NORMAL ERROR");
+		if (retries) {
+			--retries;
+			if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) {
+				goto retry_same;
+			}
+			usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+
+
+	if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
+		DEBUG_HOST("****** completition code error %x ******", cc);
+		switch (cc) {
+		case TD_CC_BITSTUFFING:
+			dev->status = USB_ST_BIT_ERR;
+			break;
+		case TD_CC_STALL:
+			dev->status = USB_ST_STALLED;
+			break;
+		case TD_BUFFEROVERRUN:
+		case TD_BUFFERUNDERRUN:
+			dev->status = USB_ST_BUF_ERR;
+			break;
+		default:
+			dev->status = USB_ST_CRC_ERR;
+		}
+		return -cc;
+	}
+	else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+
+	dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
+
+	dev->status = 0;
+	return done;
+}
+
+/* Adapted from au1x00_usb_ohci.c
+ */
+static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+				 void *buffer, int transfer_len,
+				 struct devrequest *cmd)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	u32 tmp = 0;
+
+	int leni = transfer_len;
+	int len = 0;
+	int stat = 0;
+	u32 datab[4];
+	u8 *data_buf = (u8 *) datab;
+	u16 bmRType_bReq;
+	u16 wValue;
+	u16 wIndex;
+	u16 wLength;
+
+	if (usb_pipeint(pipe)) {
+		INFO("Root-Hub submit IRQ: NOT implemented");
+		return 0;
+	}
+
+	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+
+	DEBUG_HOST("--- HUB ----------------------------------------");
+	DEBUG_HOST("submit rh urb, req=%x val=%#x index=%#x len=%d",
+	    bmRType_bReq, wValue, wIndex, wLength);
+	dump_msg(dev, pipe, buffer, transfer_len, "RH");
+	DEBUG_HOST("------------------------------------------------");
+
+	switch (bmRType_bReq) {
+	case RH_GET_STATUS:
+		DEBUG_HOST("RH_GET_STATUS");
+
+		*(__u16 *) data_buf = swap_16(1);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_INTERFACE:
+		DEBUG_HOST("RH_GET_STATUS | RH_INTERFACE");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_ENDPOINT:
+		DEBUG_HOST("RH_GET_STATUS | RH_ENDPOINT");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+		*(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE));
+		len = 4;
+		break;
+
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_OTHER | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1);
+		*(__u32 *) data_buf = swap_32(tmp);
+		isp116x_show_regs(isp116x);
+		len = 4;
+		break;
+
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_ENDPOINT");
+
+		switch (wValue) {
+		case RH_ENDPOINT_STALL:
+			DEBUG_HOST("C_HUB_ENDPOINT_STALL");
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_CLASS");
+
+		switch (wValue) {
+		case RH_C_HUB_LOCAL_POWER:
+			DEBUG_HOST("C_HUB_LOCAL_POWER");
+			len = 0;
+			break;
+
+		case RH_C_HUB_OVER_CURRENT:
+			DEBUG_HOST("C_HUB_OVER_CURRENT");
+			isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC);
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CCS);
+			len = 0;
+			break;
+
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_LSDA);
+			len = 0;
+			break;
+
+		case RH_C_PORT_CONNECTION:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PESC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_OVER_CURRENT:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_C_PORT_RESET:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRSC);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_SET_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSS);
+			len = 0;
+			break;
+
+		case RH_PORT_RESET:
+			/* Spin until any current reset finishes */
+			while (1) {
+				tmp =
+				    isp116x_read_reg32(isp116x,
+						       HCRHPORT1 + wIndex - 1);
+				if (!(tmp & RH_PS_PRS))
+					break;
+				wait_ms(1);
+			}
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRS);
+			wait_ms(10);
+
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PPS);
+			len = 0;
+			break;
+
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PES);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_ADDRESS:
+		DEBUG_HOST("RH_SET_ADDRESS");
+
+		rh_devnum = wValue;
+		len = 0;
+		break;
+
+	case RH_GET_DESCRIPTOR:
+		DEBUG_HOST("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength);
+
+		switch (wValue) {
+		case (USB_DT_DEVICE << 8):	/* device descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_dev_des),
+						wLength));
+			data_buf = root_hub_dev_des;
+			break;
+
+		case (USB_DT_CONFIG << 8):	/* configuration descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_config_des),
+						wLength));
+			data_buf = root_hub_config_des;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x00):	/* string 0 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index0),
+						wLength));
+			data_buf = root_hub_str_index0;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x01):	/* string 1 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index1),
+						wLength));
+			data_buf = root_hub_str_index1;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		DEBUG_HOST("RH_GET_DESCRIPTOR | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+		data_buf[0] = 0x09;	/* min length; */
+		data_buf[1] = 0x29;
+		data_buf[2] = tmp & RH_A_NDP;
+		data_buf[3] = 0;
+		if (tmp & RH_A_PSM)	/* per-port power switching? */
+			data_buf[3] |= 0x01;
+		if (tmp & RH_A_NOCP)	/* no overcurrent reporting? */
+			data_buf[3] |= 0x10;
+		else if (tmp & RH_A_OCPM)	/* per-port overcurrent rep? */
+			data_buf[3] |= 0x08;
+
+		/* Corresponds to data_buf[4-7] */
+		datab[1] = 0;
+		data_buf[5] = (tmp & RH_A_POTPGT) >> 24;
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+		data_buf[7] = tmp & RH_B_DR;
+		if (data_buf[2] < 7)
+			data_buf[8] = 0xff;
+		else {
+			data_buf[0] += 2;
+			data_buf[8] = (tmp & RH_B_DR) >> 8;
+			data_buf[10] = data_buf[9] = 0xff;
+		}
+
+		len = min1_t(unsigned int, leni,
+			    min2_t(unsigned int, data_buf[0], wLength));
+		break;
+
+	case RH_GET_CONFIGURATION:
+		DEBUG_HOST("RH_GET_CONFIGURATION");
+
+		*(__u8 *) data_buf = 0x01;
+		len = 1;
+		break;
+
+	case RH_SET_CONFIGURATION:
+		DEBUG_HOST("RH_SET_CONFIGURATION");
+
+		isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC);
+		len = 0;
+		break;
+
+	default:
+		ERR("*** *** *** unsupported root hub command *** *** ***");
+		stat = USB_ST_STALLED;
+	}
+
+	len = min1_t(int, len, leni);
+	if (buffer != data_buf)
+		memcpy(buffer, data_buf, len);
+
+	dev->act_len = len;
+	dev->status = stat;
+	DEBUG_HOST("dev act_len %d, status %ld", dev->act_len, dev->status);
+
+	dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)");
+
+	return stat;
+}
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	DEBUG_HOST("dev=%p pipe=%#lx buf=%p size=%d int=%d",
+	    dev, pipe, buffer, len, interval);
+
+	return -1;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	int devnum = usb_pipedevice(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int dir_in = usb_pipein(pipe);
+	int done, ret;
+	
+	
+	/* Control message is for the HUB? */
+	if (devnum == rh_devnum)
+		return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup);
+
+	/* Ok, no HUB message so send the message to the device */
+
+	/* Setup phase */
+	DEBUG_HOST("--- SETUP PHASE --------------------------------");
+	usb_settoggle(dev, epnum, 1, 0);
+	
+	
+	ret = isp116x_submit_job(dev, pipe,
+				PTD_DIR_SETUP,
+				 setup, sizeof(struct devrequest));
+	if (ret < 0) {
+		DEBUG_HOST("control setup phase error (ret = %d", ret);
+		return -1;
+	}
+
+	/* Data phase */
+	DEBUG_HOST("--- DATA PHASE ---------------------------------");
+	done = 0;
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	while (done < len) {
+		ret = isp116x_submit_job(dev, pipe,
+					 dir_in ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+		if (ret < 0) {
+			DEBUG_HOST("control data phase error (ret = %d)", ret);
+			return -1;
+		}
+		done += ret;
+
+		if (dir_in && ret < max)	/* short packet */
+			break;
+	}
+
+	/* Status phase */
+	DEBUG_HOST("--- STATUS PHASE -------------------------------");
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	ret = isp116x_submit_job(dev, pipe,
+				 !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0);
+	if (ret < 0) {
+		DEBUG_HOST("control status phase error (ret = %d", ret);
+		return -1;
+	}
+
+	dev->act_len = done;
+
+	dump_msg(dev, pipe, buffer, len, "DEV(ret)");
+
+	return done;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int dir_out = usb_pipeout(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int done, ret;
+	
+	DEBUG_HOST("--- BULK ---------------------------------------");
+	DEBUG_HOST("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d",
+	    usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out);
+
+	done = 0;
+	while (done < len) {
+
+		ret = isp116x_submit_job(dev, pipe,
+					 !dir_out ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+
+		if (ret < 0) {
+			DEBUG_HOST("error on bulk message (ret = %d)", ret);
+			return -1;
+		}
+
+		done += ret;
+
+		if (!dir_out && ret < max)	/* short packet */
+			break;
+	}
+
+	dev->act_len = done;
+
+	return 0;
+}
+
+/* --- Basic functions ----------------------------------------------------- */
+
+
+#if 0
+/* GALVEZ: Test function */
+static int GALVEZ_test_function( struct isp116x *isp116x )
+{
+	short res;
+
+	isp116x_write_reg16(isp116x, HCSCRATCH, 0x1234);
+	res = isp116x_read_reg16(isp116x, HCSCRATCH);	
+	ERR ("Scratch register read: %x\r\n",res);
+	return 0;
+
+}
+#endif
+
+static int isp116x_sw_reset(struct isp116x *isp116x)
+{
+	int retries = 15;
+	int ret = 0;
+
+	DEBUG_HOST("");
+
+	isp116x->disabled = 1;
+
+	isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC);
+	isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR);
+	
+	while (--retries) {
+		/* It usually resets within 1 ms */
+		/* GALVEZ: not enough for TOS, try 7 ms */
+		wait_ms(7);
+		if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR))
+			break;
+	}
+	
+	if (!retries) {
+		ERR("software reset timeout");
+		ret = -1;
+	}
+
+#if 0
+	/* GALVEZ: DEBUG SOFTWARE RESET */
+		
+	retries = 5000;
+	
+	while (--retries){
+		if ((isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) {
+			INFO ("HCR: 1 retries: %d\n\r",retries);
+		}
+	}
+#endif /* END DEBUG */
+
+	return ret;
+}
+
+static int isp116x_reset(struct isp116x *isp116x)
+{
+	unsigned long t;
+	u16 clkrdy = 0;
+	int ret, timeout = 1000;/* ms
+				* Galvez: 15 ms sometimes isn't enough,
+				* for NetUSBee under TOS ??????? increased to 150 ms 
+				*/ 
+
+	DEBUG_HOST("");
+
+	ret = isp116x_sw_reset(isp116x);
+
+	if (ret)
+		return ret;
+
+	for (t = 0; t < timeout; t++) {
+		clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY;
+		if (clkrdy)
+			break;
+		wait_ms(1);
+	}
+	if (!clkrdy) {
+		ERR("clock not ready after %dms", timeout);
+		/* After sw_reset the clock won't report to be ready, if
+		   H_WAKEUP pin is high. */
+		ERR("please make sure that the H_WAKEUP pin is pulled low!");
+		ret = -1;
+	}
+	return ret;
+}
+
+static void isp116x_stop(struct isp116x *isp116x)
+{
+	u32 val;
+	
+	DEBUG_HOST("");
+	
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	/* Switch off ports' power, some devices don't come up
+	   after next 'start' without this */
+	val = isp116x_read_reg32(isp116x, HCRHDESCA);
+	val &= ~(RH_A_NPS | RH_A_PSM);
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS);
+	
+	isp116x_sw_reset(isp116x);
+}
+
+/*
+ *  Configure the chip. The chip must be successfully reset by now.
+ */
+static int isp116x_start(struct isp116x *isp116x)
+{
+	struct isp116x_platform_data *board = isp116x->board;
+	u32 val;
+	
+	DEBUG_HOST("");
+
+	/* Clear interrupt status and disable all interrupt sources */
+	isp116x_write_reg16(isp116x, HCuPINT, 0xff);
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE);
+	isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE);
+
+	/* Hardware configuration */
+	val = HCHWCFG_DBWIDTH(1);
+
+	if (board->sel15Kres)
+		val |= HCHWCFG_15KRSEL;
+	/* Remote wakeup won't work without working clock */
+	if (board->remote_wakeup_enable)
+		val |= HCHWCFG_CLKNOTSTOP;
+	if (board->oc_enable)
+		val |= HCHWCFG_ANALOG_OC;
+	isp116x_write_reg16(isp116x, HCHWCFG, val);
+
+
+	/* --- Root hub configuration */
+	val = (25 << 24) & RH_A_POTPGT;
+	/* AN10003_1.pdf recommends RH_A_NPS (no power switching) to
+	   be always set. Yet, instead, we request individual port
+	   power switching. */
+	val |= RH_A_PSM;
+	/* Report overcurrent per port */
+	val |= RH_A_OCPM;
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+	val = RH_B_PPCM;
+	isp116x_write_reg32(isp116x, HCRHDESCB, val);
+	isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+	val = 0;
+	if (board->remote_wakeup_enable)
+		val |= RH_HS_DRWE;
+	isp116x_write_reg32(isp116x, HCRHSTATUS, val);
+	isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+	isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf);
+
+	/* Go operational */
+	val = HCCONTROL_USB_OPER;
+	if (board->remote_wakeup_enable)
+		val |= HCCONTROL_RWE;
+	isp116x_write_reg32(isp116x, HCCONTROL, val);
+
+	/* Disable ports to avoid race in device enumeration */
+	isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS);
+	isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS);
+
+	isp116x_show_regs(isp116x);
+
+	isp116x->disabled = 0;
+
+	return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+
+
+int isp116x_check_id(struct isp116x *isp116x)
+{
+	u16 val;
+
+	val = isp116x_read_reg16(isp116x, HCCHIPID);
+	DEBUG_HOST("chip ID: %04x", val);
+	printf ("chip ID: %04x", val);
+	
+	if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) {
+		printf("invalid chip ID %04x", val);
+		return -1;
+	}
+
+	return 0;
+}
+
+
+int usb_lowlevel_init(void)
+{
+//	u16 val;
+
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	got_rhsc = rh_devnum = 0;
+
+	/* Init device registers addr */
+	isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR_BEE;
+	isp116x->data_reg = (u16 *) ISP116X_HCD_DATA_BEE;
+
+	/* Setup specific board settings */
+#ifdef ISP116X_HCD_SEL15kRES
+	isp116x_board.sel15Kres = 1;
+#endif
+#ifdef ISP116X_HCD_OC_ENABLE
+	isp116x_board.oc_enable = 1;
+#endif
+#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+	isp116x_board.remote_wakeup_enable = 1;
+#endif
+	isp116x->board = &isp116x_board;
+
+	/* Try to get ISP116x silicon chip ID */
+	if (  isp116x_check_id(isp116x) < 0)
+		return -1;
+	
+
+//	GALVEZ_test_function ( isp116x );	/* Gálvez: Testing writing to registers */
+
+	isp116x->disabled = 1;
+	isp116x->sleeping = 0;
+
+	isp116x_reset(isp116x);
+	isp116x_start(isp116x);
+
+	return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	if (!isp116x->disabled)
+		isp116x_stop(isp116x);
+
+	return 0;
+}
diff --git a/usb/store/host/netusbee/isp116x.h b/usb/store/host/netusbee/isp116x.h
new file mode 100644
index 0000000..7d62865
--- /dev/null
+++ b/usb/store/host/netusbee/isp116x.h
@@ -0,0 +1,596 @@
+/*
+ * Modified for Atari-NetUSBee by David Gálvez 2010
+ *
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _NETUSBEE_ISP116X_H
+#define _NETUSBEE_ISP116X_H
+
+
+#define ERR(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define WARN(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define INFO(fmt, args...)	printf("isp116x: " fmt "\n\r" , ## args)
+
+/* ------------------------------------------------------------------------- */
+
+/* us of 1ms frame */
+#define  MAX_LOAD_LIMIT		850
+
+/* Full speed: max # of bytes to transfer for a single urb
+   at a time must be < 1024 && must be multiple of 64.
+   832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED	832
+
+/* Low speed: there is no reason to schedule in very big
+   chunks; often the requested long transfers are for
+   string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED	64
+
+/* Bytetime (us), a rough indication of how much time it
+   would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED	1
+#define BYTE_TIME_LOWSPEED	20
+
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE	4096
+#define ISP116x_ITL_BUFSIZE	0
+#define ISP116x_ATL_BUFSIZE	((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+
+#define ISP116x_WRITE_OFFSET	0x80
+
+
+/* --- ISP116x address registers in Netusbee --------------------------------*/
+
+#define ISP116X_HCD_ADDR_BEE	0x00FBC000
+#define ISP116X_HCD_DATA_BEE	0x00FA0000
+
+
+/* --- ISP116x registers/bits ---------------------------------------------- */
+
+#define	HCREVISION	0x00
+#define	HCCONTROL	0x01
+#define		HCCONTROL_HCFS	(3 << 6)	/* host controller
+						   functional state */
+#define		HCCONTROL_USB_RESET	(0 << 6)
+#define		HCCONTROL_USB_RESUME	(1 << 6)
+#define		HCCONTROL_USB_OPER	(2 << 6)
+#define		HCCONTROL_USB_SUSPEND	(3 << 6)
+#define		HCCONTROL_RWC	(1 << 9)	/* remote wakeup connected */
+#define		HCCONTROL_RWE	(1 << 10)	/* remote wakeup enable */
+#define	HCCMDSTAT	0x02
+#define		HCCMDSTAT_HCR	(1 << 0)	/* host controller reset */
+#define		HCCMDSTAT_SOC	(3 << 16)	/* scheduling overrun count */
+#define	HCINTSTAT	0x03
+#define		HCINT_SO	(1 << 0)	/* scheduling overrun */
+#define		HCINT_WDH	(1 << 1)	/* writeback of done_head */
+#define		HCINT_SF	(1 << 2)	/* start frame */
+#define		HCINT_RD	(1 << 3)	/* resume detect */
+#define		HCINT_UE	(1 << 4)	/* unrecoverable error */
+#define		HCINT_FNO	(1 << 5)	/* frame number overflow */
+#define		HCINT_RHSC	(1 << 6)	/* root hub status change */
+#define		HCINT_OC	(1 << 30)	/* ownership change */
+#define		HCINT_MIE	(1 << 31)	/* master interrupt enable */
+#define	HCINTENB	0x04
+#define	HCINTDIS	0x05
+#define	HCFMINTVL	0x0d
+#define	HCFMREM		0x0e
+#define	HCFMNUM		0x0f
+#define	HCLSTHRESH	0x11
+#define	HCRHDESCA	0x12
+#define		RH_A_NDP	(0x3 << 0)	/* # downstream ports */
+#define		RH_A_PSM	(1 << 8)	/* power switching mode */
+#define		RH_A_NPS	(1 << 9)	/* no power switching */
+#define		RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define		RH_A_OCPM	(1 << 11)	/* overcurrent protection
+						   mode */
+#define		RH_A_NOCP	(1 << 12)	/* no overcurrent protection */
+#define		RH_A_POTPGT	(0xff << 24)	/* power on -> power good
+						   time */
+#define	HCRHDESCB	0x13
+#define		RH_B_DR		(0xffff << 0)	/* device removable flags */
+#define		RH_B_PPCM	(0xffff << 16)	/* port power control mask */
+#define	HCRHSTATUS	0x14
+#define		RH_HS_LPS	(1 << 0)	/* local power status */
+#define		RH_HS_OCI	(1 << 1)	/* over current indicator */
+#define		RH_HS_DRWE	(1 << 15)	/* device remote wakeup
+						   enable */
+#define		RH_HS_LPSC	(1 << 16)	/* local power status change */
+#define		RH_HS_OCIC	(1 << 17)	/* over current indicator
+						   change */
+#define		RH_HS_CRWE	(1 << 31)	/* clear remote wakeup
+						   enable */
+#define	HCRHPORT1	0x15
+#define		RH_PS_CCS	(1 << 0)	/* current connect status */
+#define		RH_PS_PES	(1 << 1)	/* port enable status */
+#define		RH_PS_PSS	(1 << 2)	/* port suspend status */
+#define		RH_PS_POCI	(1 << 3)	/* port over current
+						   indicator */
+#define		RH_PS_PRS	(1 << 4)	/* port reset status */
+#define		RH_PS_PPS	(1 << 8)	/* port power status */
+#define		RH_PS_LSDA	(1 << 9)	/* low speed device attached */
+#define		RH_PS_CSC	(1 << 16)	/* connect status change */
+#define		RH_PS_PESC	(1 << 17)	/* port enable status change */
+#define		RH_PS_PSSC	(1 << 18)	/* port suspend status
+						   change */
+#define		RH_PS_OCIC	(1 << 19)	/* over current indicator
+						   change */
+#define		RH_PS_PRSC	(1 << 20)	/* port reset status change */
+#define		HCRHPORT_CLRMASK	(0x1f << 16)
+#define	HCRHPORT2	0x16
+#define	HCHWCFG		0x20
+#define		HCHWCFG_15KRSEL		(1 << 12)
+#define		HCHWCFG_CLKNOTSTOP	(1 << 11)
+#define		HCHWCFG_ANALOG_OC	(1 << 10)
+#define		HCHWCFG_DACK_MODE	(1 << 8)
+#define		HCHWCFG_EOT_POL		(1 << 7)
+#define		HCHWCFG_DACK_POL	(1 << 6)
+#define		HCHWCFG_DREQ_POL	(1 << 5)
+#define		HCHWCFG_DBWIDTH_MASK	(0x03 << 3)
+#define		HCHWCFG_DBWIDTH(n)	(((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define		HCHWCFG_INT_POL		(1 << 2)
+#define		HCHWCFG_INT_TRIGGER	(1 << 1)
+#define		HCHWCFG_INT_ENABLE	(1 << 0)
+#define	HCDMACFG	0x21
+#define		HCDMACFG_BURST_LEN_MASK	(0x03 << 5)
+#define		HCDMACFG_BURST_LEN(n)	(((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define		HCDMACFG_BURST_LEN_1	HCDMACFG_BURST_LEN(0)
+#define		HCDMACFG_BURST_LEN_4	HCDMACFG_BURST_LEN(1)
+#define		HCDMACFG_BURST_LEN_8	HCDMACFG_BURST_LEN(2)
+#define		HCDMACFG_DMA_ENABLE	(1 << 4)
+#define		HCDMACFG_BUF_TYPE_MASK	(0x07 << 1)
+#define		HCDMACFG_CTR_SEL	(1 << 2)
+#define		HCDMACFG_ITLATL_SEL	(1 << 1)
+#define		HCDMACFG_DMA_RW_SELECT	(1 << 0)
+#define	HCXFERCTR	0x22
+#define	HCuPINT		0x24
+#define		HCuPINT_SOF		(1 << 0)
+#define		HCuPINT_ATL		(1 << 1)
+#define		HCuPINT_AIIEOT		(1 << 2)
+#define		HCuPINT_OPR		(1 << 4)
+#define		HCuPINT_SUSP		(1 << 5)
+#define		HCuPINT_CLKRDY		(1 << 6)
+#define	HCuPINTENB	0x25
+#define	HCCHIPID	0x27
+#define		HCCHIPID_MASK		0xff00
+#define		HCCHIPID_MAGIC		0x6100
+#define	HCSCRATCH	0x28
+#define	HCSWRES		0x29
+#define		HCSWRES_MAGIC		0x00f6
+#define	HCITLBUFLEN	0x2a
+#define	HCATLBUFLEN	0x2b
+#define	HCBUFSTAT	0x2c
+#define		HCBUFSTAT_ITL0_FULL	(1 << 0)
+#define		HCBUFSTAT_ITL1_FULL	(1 << 1)
+#define		HCBUFSTAT_ATL_FULL	(1 << 2)
+#define		HCBUFSTAT_ITL0_DONE	(1 << 3)
+#define		HCBUFSTAT_ITL1_DONE	(1 << 4)
+#define		HCBUFSTAT_ATL_DONE	(1 << 5)
+#define	HCRDITL0LEN	0x2d
+#define	HCRDITL1LEN	0x2e
+#define	HCITLPORT	0x40
+#define	HCATLPORT	0x41
+
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p)	(((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v)		(((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p)	(((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v)		(((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p)	(((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v)		(((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p)		(((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v)		(((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p)		(((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v)		(((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p)		(((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v)		(((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p)		(((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v)		(((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p)		(((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v)		(((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p)		(((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v)		(((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p)		(((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v)		(((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p)		(((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v)		(((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p)		(((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v)		(((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p)		(((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v)		(((v) << 7) & PTD_FMT_MSK)
+
+/*  Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+    /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+    /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED     0x0F
+
+/* ------------------------------------------------------------------------- */
+
+#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
+#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
+
+/* Philips transfer descriptor */
+struct ptd {
+	u16 count;
+#define	PTD_COUNT_MSK	(0x3ff << 0)
+#define	PTD_TOGGLE_MSK	(1 << 10)
+#define	PTD_ACTIVE_MSK	(1 << 11)
+#define	PTD_CC_MSK	(0xf << 12)
+	u16 mps;
+#define	PTD_MPS_MSK	(0x3ff << 0)
+#define	PTD_SPD_MSK	(1 << 10)
+#define	PTD_LAST_MSK	(1 << 11)
+#define	PTD_EP_MSK	(0xf << 12)
+	u16 len;
+#define	PTD_LEN_MSK	(0x3ff << 0)
+#define	PTD_DIR_MSK	(3 << 10)
+#define	PTD_DIR_SETUP	(0)
+#define	PTD_DIR_OUT	(1)
+#define	PTD_DIR_IN	(2)
+#define	PTD_B5_5_MSK	(1 << 13)
+	u16 faddr;
+#define	PTD_FA_MSK	(0x7f << 0)
+#define	PTD_FMT_MSK	(1 << 7)
+} __attribute__ ((packed, aligned(2)));
+
+struct isp116x_ep {
+	struct usb_device *udev;
+	struct ptd ptd;
+
+	u8 maxpacket;
+	u8 epnum;
+	u8 nextpid;
+
+	u16 length;		/* of current packet */
+	unsigned char *data;	/* to databuf */
+
+	u16 error_count;
+};
+
+/* URB struct */
+#define N_URB_TD		48
+#define URB_DEL			1
+typedef struct {
+	struct isp116x_ep *ed;
+	void *transfer_buffer;	/* (in) associated data buffer */
+	int actual_length;	/* (return) actual transfer length */
+	unsigned long pipe;	/* (in) pipe information */
+#if 0
+	int state;
+#endif
+} urb_priv_t;
+
+struct isp116x_platform_data {
+	/* Enable internal resistors on downstream ports */
+	unsigned sel15Kres:1;
+	/* On-chip overcurrent detection */
+	unsigned oc_enable:1;
+	/* Enable wakeup by devices on usb bus (e.g. wakeup
+	   by attachment/detachment or by device activity
+	   such as moving a mouse). When chosen, this option
+	   prevents stopping internal clock, increasing
+	   thereby power consumption in suspended state. */
+	unsigned remote_wakeup_enable:1;
+};
+
+struct isp116x {
+	u16 *addr_reg;
+	u16 *data_reg;
+
+	struct isp116x_platform_data *board;
+
+	struct dentry *dentry;
+	unsigned long stat1, stat2, stat4, stat8, stat16;
+
+	/* Status flags */
+	unsigned disabled:1;
+	unsigned sleeping:1;
+
+	/* Root hub registers */
+	u32 rhdesca;
+	u32 rhdescb;
+	u32 rhstatus;
+	u32 rhport[2];
+
+	/* Schedule for the current frame */
+	struct isp116x_ep *atl_active;
+	int atl_buflen;
+	int atl_bufshrt;
+	int atl_last_dir;
+	int atl_finishing;
+};
+
+/* ------------------------------------------------- */
+
+/* Inter-io delay (ns). The chip is picky about access timings; it
+ * expects at least:
+ * 150ns delay between consecutive accesses to DATA_REG,
+ * 300ns delay between access to ADDR_REG and DATA_REG
+ * OE, WE MUST NOT be changed during these intervals
+ */
+#if defined(UDELAY)
+#define	isp116x_delay(h,d)	udelay(d)
+#else
+#define	isp116x_delay(h,d)	do {} while (0)
+#endif
+
+#include "../../super.h"	/*
+	 		 	* Functions to call supervisor mode
+		 	 	* Super() in in TOS is buggy
+			 	*/
+
+			 
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((reg & 0x00ff)<<1)); 
+	dumm = __raw_readw( isp116x->data_reg  );
+	isp116x->addr_reg = (u16*)ISP116X_HCD_ADDR_BEE;
+	dumm = __raw_readw( isp116x->addr_reg  );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0xff00)>>7) ); 
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x00ff)<<1));
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff)<<1));
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg =  (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff00)>>7)); 
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+	return val;
+}
+
+
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = __raw_readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x value: %x\n\r", isp116x->data_reg, val );
+	return val;
+}
+
+#if 0 /* We don't use it anymore */
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+#endif
+
+/*
+ * Added for NetUSBee, to write HC registers without swaping them
+ * NetUSBee already swap them by hardware (i suppose.....)
+ */
+static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg =  (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x000000ff)<<1) ); 
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x0000ff00)>>7)); 
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff0000)>>15));
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff000000)>>23) );
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+}
+/***********************************************/
+
+#if 0 /* We don't use it */
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+	p = SuperFromUser( );
+	val = (u32) readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+	SuperToUser( p );
+	return val;
+}
+#endif
+
+/*
+ * Added for NetUSBee, to read HC registers without swaping them
+ * NetUSBee already swap them by hardware (i suppose.....)
+ */
+static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = (u32) __raw_readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) __raw_readw(isp116x->data_reg )) << 16;
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+	return val;
+}
+/*******************************************************************/
+
+/* Let's keep register access functions out of line. Hint:
+   we wait at least 150 ns at every access.
+*/
+
+/* with NetUSBee use raw_read to avoid swaping bytes*/
+
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data16(isp116x);
+}
+
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data32(isp116x);
+}
+
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff));
+}
+
+/* with NetUSBee used raw_write to avoid swaping bytes by software */
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data32(isp116x, (u32) val);
+}
+
+/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
+
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+#endif /* _NETUSBEE_ISP116X_H */
diff --git a/usb/store/host/ohci-pci/ltoa.c b/usb/store/host/ohci-pci/ltoa.c
new file mode 100644
index 0000000..747ec55
--- /dev/null
+++ b/usb/store/host/ohci-pci/ltoa.c
@@ -0,0 +1,38 @@
+/*
+ * File:        ltoa.c
+ * Purpose:     Function normally found in a standard C lib.
+ *
+ * Notes:       This supports ASCII only!!!
+ */
+
+void ltoa(char *buf, long n, unsigned long base)
+{
+	unsigned long un;
+	char *tmp, ch;
+	un = n;
+	if((base == 10) && (n < 0))
+	{
+		*buf++ = '-';
+		un = -n;
+	}
+	tmp = buf;
+	do
+	{
+		ch = un % base;
+		un = un / base;
+		if(ch <= 9)
+			ch += '0';
+		else
+			ch += 'a' - 10;
+		*tmp++ = ch;
+	}
+	while(un);
+	*tmp = '\0';
+	while(tmp > buf)
+	{
+		ch = *buf;
+		*buf++ = *--tmp;
+		*tmp = ch;
+	}
+}
+
diff --git a/usb/store/host/ohci-pci/mod_devicetable.h b/usb/store/host/ohci-pci/mod_devicetable.h
new file mode 100644
index 0000000..8e480b5
--- /dev/null
+++ b/usb/store/host/ohci-pci/mod_devicetable.h
@@ -0,0 +1,165 @@
+#ifndef MOD_DEVICETABLE_H
+#define MOD_DEVICETABLE_H
+
+#define PCI_ANY_ID (~0)
+
+struct pci_device_id {
+	unsigned long vendor, device;		/* Vendor and device ID or PCI_ANY_ID*/
+	unsigned long subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
+	unsigned long class, class_mask;	/* (class,subclass,prog-if) triplet */
+	unsigned long driver_data;	/* Data private to the driver */
+};
+
+#define IEEE1394_MATCH_VENDOR_ID	0x0001
+#define IEEE1394_MATCH_MODEL_ID		0x0002
+#define IEEE1394_MATCH_SPECIFIER_ID	0x0004
+#define IEEE1394_MATCH_VERSION		0x0008
+
+struct ieee1394_device_id {
+	unsigned long match_flags;
+	unsigned long vendor_id;
+	unsigned long model_id;
+	unsigned long specifier_id;
+	unsigned long version;
+	unsigned long driver_data;
+};
+
+/*
+ * Device table entry for "new style" table-driven USB drivers.
+ * User mode code can read these tables to choose which modules to load.
+ * Declare the table as a MODULE_DEVICE_TABLE.
+ *
+ * A probe() parameter will point to a matching entry from this table.
+ * Use the driver_info field for each match to hold information tied
+ * to that match:  device quirks, etc.
+ *
+ * Terminate the driver's table with an all-zeroes entry.
+ * Use the flag values to control which fields are compared.
+ */
+
+/**
+ * struct usb_device_id - identifies USB devices for probing and hotplugging
+ * @match_flags: Bit mask controlling of the other fields are used to match
+ *	against new devices.  Any field except for driver_info may be used,
+ *	although some only make sense in conjunction with other fields.
+ *	This is usually set by a USB_DEVICE_*() macro, which sets all
+ *	other fields in this structure except for driver_info.
+ * @idVendor: USB vendor ID for a device; numbers are assigned
+ *	by the USB forum to its members.
+ * @idProduct: Vendor-assigned product ID.
+ * @bcdDevice_lo: Low end of range of vendor-assigned product version numbers.
+ *	This is also used to identify individual product versions, for
+ *	a range consisting of a single device.
+ * @bcdDevice_hi: High end of version number range.  The range of product
+ *	versions is inclusive.
+ * @bDeviceClass: Class of device; numbers are assigned
+ *	by the USB forum.  Products may choose to implement classes,
+ *	or be vendor-specific.  Device classes specify behavior of all
+ *	the interfaces on a devices.
+ * @bDeviceSubClass: Subclass of device; associated with bDeviceClass.
+ * @bDeviceProtocol: Protocol of device; associated with bDeviceClass.
+ * @bInterfaceClass: Class of interface; numbers are assigned
+ *	by the USB forum.  Products may choose to implement classes,
+ *	or be vendor-specific.  Interface classes specify behavior only
+ *	of a given interface; other interfaces may support other classes.
+ * @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass.
+ * @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass.
+ * @driver_info: Holds information used by the driver.  Usually it holds
+ *	a pointer to a descriptor understood by the driver, or perhaps
+ *	device flags.
+ *
+ * In most cases, drivers will create a table of device IDs by using
+ * USB_DEVICE(), or similar macros designed for that purpose.
+ * They will then export it to userspace using MODULE_DEVICE_TABLE(),
+ * and provide it to the USB core through their usb_driver structure.
+ *
+ * See the usb_match_id() function for information about how matches are
+ * performed.  Briefly, you will normally use one of several macros to help
+ * construct these entries.  Each entry you provide will either identify
+ * one or more specific products, or will identify a class of products
+ * which have agreed to behave the same.  You should put the more specific
+ * matches towards the beginning of your table, so that driver_info can
+ * record quirks of specific products.
+ */
+struct usb_device_id {
+	/* which fields to match against? */
+	unsigned short		match_flags;
+
+	/* Used for product specific matches; range is inclusive */
+	unsigned short		idVendor;
+	unsigned short		idProduct;
+	unsigned short		bcdDevice_lo;
+	unsigned short		bcdDevice_hi;
+
+	/* Used for device class matches */
+	unsigned char		bDeviceClass;
+	unsigned char		bDeviceSubClass;
+	unsigned char		bDeviceProtocol;
+
+	/* Used for interface class matches */
+	unsigned char		bInterfaceClass;
+	unsigned char		bInterfaceSubClass;
+	unsigned char		bInterfaceProtocol;
+
+	/* not matched against */
+	unsigned long	driver_info;
+};
+
+/* Some useful macros to use to create struct usb_device_id */
+#define USB_DEVICE_ID_MATCH_VENDOR		0x0001
+#define USB_DEVICE_ID_MATCH_PRODUCT		0x0002
+#define USB_DEVICE_ID_MATCH_DEV_LO		0x0004
+#define USB_DEVICE_ID_MATCH_DEV_HI		0x0008
+#define USB_DEVICE_ID_MATCH_DEV_CLASS		0x0010
+#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS	0x0020
+#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL	0x0040
+#define USB_DEVICE_ID_MATCH_INT_CLASS		0x0080
+#define USB_DEVICE_ID_MATCH_INT_SUBCLASS	0x0100
+#define USB_DEVICE_ID_MATCH_INT_PROTOCOL	0x0200
+
+/* s390 CCW devices */
+struct ccw_device_id {
+	unsigned short	match_flags;	/* which fields to match against */
+
+	unsigned short	cu_type;	/* control unit type     */
+	unsigned short	dev_type;	/* device type           */
+	unsigned char	cu_model;	/* control unit model    */
+	unsigned char	dev_model;	/* device model          */
+
+	unsigned long driver_info;
+};
+
+#define CCW_DEVICE_ID_MATCH_CU_TYPE		0x01
+#define CCW_DEVICE_ID_MATCH_CU_MODEL		0x02
+#define CCW_DEVICE_ID_MATCH_DEVICE_TYPE		0x04
+#define CCW_DEVICE_ID_MATCH_DEVICE_MODEL	0x08
+
+
+#define PNP_ID_LEN	8
+#define PNP_MAX_DEVICES	8
+
+struct pnp_device_id {
+	unsigned char id[PNP_ID_LEN];
+	unsigned long driver_data;
+};
+
+struct pnp_card_device_id {
+	unsigned char id[PNP_ID_LEN];
+	unsigned long driver_data;
+	struct {
+		unsigned char id[PNP_ID_LEN];
+	} devs[PNP_MAX_DEVICES];
+};
+
+
+#define SERIO_ANY	0xff
+
+struct serio_device_id {
+	unsigned char type;
+	unsigned char extra;
+	unsigned char id;
+	unsigned char proto;
+};
+
+
+#endif /* MOD_DEVICETABLE_H */
diff --git a/usb/store/host/ohci-pci/ohci-hcd.c b/usb/store/host/ohci-pci/ohci-hcd.c
new file mode 100644
index 0000000..8dcab45
--- /dev/null
+++ b/usb/store/host/ohci-pci/ohci-hcd.c
@@ -0,0 +1,1953 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB and PCI bus.
+ *
+ * Interrupt support is added. Now, it has been tested
+ * on ULI1575 chip and works well with USB keyboard.
+ *
+ * (C) Copyright 2007
+ * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ * Note: Much of this code has been derived from Linux 2.4
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com - based on s3c24x0's driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/*
+ * IMPORTANT NOTE
+ * this driver is intended for use with USB Mass Storage Devices
+ * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
+ */
+
+#include "../../config.h"
+#include "../../usb.h"
+#include "ohci.h"
+#include "pci_ids.h"
+#include "pcixbios.h"
+
+#include "../../debug.h"
+/* Extra debug information, aside from config.h */
+#undef OHCI_VERBOSE_DEBUG	/* not always helpful */
+#undef SHOW_INFO
+#undef OHCI_FILL_TRACE
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+/*
+ * e.g. PCI controllers need this
+ */
+#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+# define readl(a) __swap_32(*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
+#else
+# define readl(a) (*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
+#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
+
+#define min_t(type, x, y) \
+		    ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+/* Galvez: added to avoid shadow warnings */
+#define min2_t(type,x,y)	\
+	({ type __a = (x); type __b = (y); __a < __b ? __a : __b; })
+
+struct pci_device_id usb_pci_table[] = {
+	{ PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ULI1575 PCI OHCI module ids */
+	{ PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NEC PCI OHCI module ids */
+//	{ PCI_VENDOR_ID_PHILIPS, PCI_VENDOR_ID_PHILIPS_ISP1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* Philips 1561 PCI OHCI module ids */
+	/* Please add supported PCI OHCI controller ids here */
+	{ 0, 0, 0, 0, 0, 0, 0 }
+};
+
+
+#define err(format, arg...) printf("ERROR: " format "\r\n", ## arg)
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\r\n", ## arg)
+#else
+#define info(format, arg...) do {} while (0)
+#endif
+
+#define m16_swap(x) cpu_to_le16(x)
+#define m32_swap(x) cpu_to_le32(x)
+
+typedef struct
+{
+	long ident;
+	union
+	{
+		long l;
+		short i[2];
+		char c[4];
+	} v;
+} COOKIE;
+
+extern COOKIE *get_cookie(long id);
+extern void udelay(long usec);
+extern void ltoa(char *buf, long n, unsigned long base);
+
+/* global ohci_t */
+static ohci_t gohci;
+/* device which was disconnected */
+struct usb_device *devgone;
+char ohci_inited;
+
+static inline u32 roothub_a(struct ohci *hc)
+	{ return readl(&hc->regs->roothub.a); }
+static inline u32 roothub_b(struct ohci *hc)
+	{ return readl(&hc->regs->roothub.b); }
+static inline u32 roothub_status(struct ohci *hc)
+	{ return readl(&hc->regs->roothub.status); }
+static inline u32 roothub_portstatus(struct ohci *hc, int i)
+	{ return readl(&hc->regs->roothub.portstatus[i]); }
+
+/* forward declaration */
+static int hc_interrupt(void);
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval);
+
+#if 0
+unsigned short cpu_to_le16(unsigned short val)
+{
+	extern unsigned short swap_short(unsigned short val);
+	if(gohci.big_endian)
+		return(swap_short(val));
+	return(val);
+}
+
+unsigned long cpu_to_le32(unsigned long val)
+{
+	extern unsigned long swap_long(unsigned long val);
+	if(gohci.big_endian)
+		return(swap_long(val));
+	return(val);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv(urb_priv_t *urb)
+{
+	int i;
+	struct td	*td;
+	int last = urb->length - 1;
+	if(last >= 0)
+	{
+		for(i = 0; i <= last; i++)
+		{
+			td = urb->td[i];
+			if(td)
+			{
+				td->usb_dev = NULL;
+				urb->td[i] = NULL;
+			}
+		}
+	}
+	usb_free(urb);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#if DEBUG_HOST_LAYER
+static int sohci_get_current_frame_number(struct usb_device *dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print(urb_priv_t *purb, struct usb_device *dev,
+		      unsigned long pipe, void *buffer, int transfer_len,
+		      struct devrequest *setup, char *str, int small)
+{
+	DEBUG_HOST("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
+			str,
+			sohci_get_current_frame_number(dev),
+			usb_pipedevice(pipe),
+			usb_pipeendpoint(pipe),
+			usb_pipeout(pipe)? 'O': 'I',
+			usb_pipetype(pipe) < 2 ? \
+				(usb_pipeint(pipe)? "INTR": "ISOC"): \
+				(usb_pipecontrol(pipe)? "CTRL": "BULK"),
+			(purb ? purb->actual_length : 0),
+			transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+	if(!small)
+	{
+		int i, len;
+		if(usb_pipecontrol(pipe))
+		{
+			DEBUG_HOST(__FILE__ ": cmd(8):");
+			for(i = 0; i < 8 ; i++)
+				DEBUG_HOST(" %02x", ((__u8 *)setup)[i]);
+			DEBUG_HOST("\r\n");
+		}
+		if(transfer_len > 0 && buffer)
+		{
+			DEBUG_HOST(__FILE__ ": data(%d/%d):", (purb ? purb->actual_length : 0), transfer_len);
+			len = usb_pipeout(pipe)? transfer_len : (purb ? purb->actual_length : 0);
+			for(i = 0; i < 16 && i < len; i++)
+				DEBUG_HOST(" %02x", ((__u8 *)buffer)[i]);
+			DEBUG_HOST("%s\r\n", i < len? "...": "");
+		}
+	}
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree
+ * inclusive iso eds */
+void ep_print_int_eds(ohci_t *ohci, char *str)
+{
+	int i, j;
+	__u32 *ed_p;
+	for(i = 0; i < 32; i++)
+	{
+		j = 5;
+		ed_p = &(ohci->hcca->int_table[i]);
+		if(*ed_p == 0)
+			continue;
+		DEBUG_HOST(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+		while(*ed_p != 0 && j--)
+		{
+			ed_t *ed = (ed_t *)m32_swap((unsigned long)ed_p);
+			DEBUG_HOST(" ed: %4x;", ed->hwINFO);
+			ed_p = &ed->hwNextED;
+		}
+		DEBUG_HOST("\r\n");
+	}
+}
+
+static void ohci_dump_intr_mask(char *label, __u32 mask)
+{
+	DEBUG_HOST("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+		label,
+		mask,
+		(mask & OHCI_INTR_MIE) ? " MIE" : "",
+		(mask & OHCI_INTR_OC) ? " OC" : "",
+		(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+		(mask & OHCI_INTR_FNO) ? " FNO" : "",
+		(mask & OHCI_INTR_UE) ? " UE" : "",
+		(mask & OHCI_INTR_RD) ? " RD" : "",
+		(mask & OHCI_INTR_SF) ? " SF" : "",
+		(mask & OHCI_INTR_WDH) ? " WDH" : "",
+		(mask & OHCI_INTR_SO) ? " SO" : ""
+		);
+}
+
+static void maybe_print_eds(char *label, __u32 value)
+{
+	ed_t *edp; 
+	value += gohci.dma_offset;
+	edp = (ed_t *)value;
+	if(value && (value < 0xDFFFF0))  /* STRAM */
+	{
+		DEBUG_HOST("%s %08x", label, value);
+		DEBUG_HOST("%08x", edp->hwINFO);
+		DEBUG_HOST("%08x", edp->hwTailP);
+		DEBUG_HOST("%08x", edp->hwHeadP);
+		DEBUG_HOST("%08x", edp->hwNextED);
+	}
+}
+
+static char *hcfs2string(int state)
+{
+	switch(state)
+	{
+		case OHCI_USB_RESET:	return "reset";
+		case OHCI_USB_RESUME:	return "resume";
+		case OHCI_USB_OPER:	return "operational";
+		case OHCI_USB_SUSPEND:	return "suspend";
+	}
+	return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status(ohci_t *controller)
+{
+	struct ohci_regs	*regs = controller->regs;
+	__u32	temp = readl(&regs->revision) & 0xff;
+	if(temp != 0x10)
+		DEBUG_HOST("spec %d.%d", (temp >> 4), (temp & 0x0f));
+	temp = readl(&regs->control);
+	DEBUG_HOST("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+		(temp & OHCI_CTRL_RWE) ? " RWE" : "",
+		(temp & OHCI_CTRL_RWC) ? " RWC" : "",
+		(temp & OHCI_CTRL_IR) ? " IR" : "",
+		hcfs2string(temp & OHCI_CTRL_HCFS),
+		(temp & OHCI_CTRL_BLE) ? " BLE" : "",
+		(temp & OHCI_CTRL_CLE) ? " CLE" : "",
+		(temp & OHCI_CTRL_IE) ? " IE" : "",
+		(temp & OHCI_CTRL_PLE) ? " PLE" : "",
+		temp & OHCI_CTRL_CBSR
+		);
+	temp = readl(&regs->cmdstatus);
+	DEBUG_HOST("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+		(temp & OHCI_SOC) >> 16,
+		(temp & OHCI_OCR) ? " OCR" : "",
+		(temp & OHCI_BLF) ? " BLF" : "",
+		(temp & OHCI_CLF) ? " CLF" : "",
+		(temp & OHCI_HCR) ? " HCR" : ""
+		);
+	ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
+	ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
+	maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
+	maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
+	maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
+	maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
+	maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
+	maybe_print_eds("donehead", readl(&regs->donehead));
+}
+
+static void ohci_dump_roothub(ohci_t *controller, int verbose)
+{
+	__u32	temp, ndp, i;
+	temp = roothub_a(controller);
+	ndp = (temp & RH_A_NDP);
+	if(verbose)
+	{
+		DEBUG_HOST("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+			((temp & RH_A_POTPGT) >> 24) & 0xff,
+			(temp & RH_A_NOCP) ? " NOCP" : "",
+			(temp & RH_A_OCPM) ? " OCPM" : "",
+			(temp & RH_A_DT) ? " DT" : "",
+			(temp & RH_A_NPS) ? " NPS" : "",
+			(temp & RH_A_PSM) ? " PSM" : "",
+			ndp
+			);
+		temp = roothub_b(controller);
+		DEBUG_HOST("roothub.b: %08x PPCM=%04x DR=%04x",
+			temp,
+			(temp & RH_B_PPCM) >> 16,
+			(temp & RH_B_DR)
+			);
+		temp = roothub_status(controller);
+		DEBUG_HOST("roothub.status: %08x%s%s%s%s%s%s",
+			temp,
+			(temp & RH_HS_CRWE) ? " CRWE" : "",
+			(temp & RH_HS_OCIC) ? " OCIC" : "",
+			(temp & RH_HS_LPSC) ? " LPSC" : "",
+			(temp & RH_HS_DRWE) ? " DRWE" : "",
+			(temp & RH_HS_OCI) ? " OCI" : "",
+			(temp & RH_HS_LPS) ? " LPS" : ""
+			);
+	}
+	for(i = 0; i < ndp; i++)
+	{
+		temp = roothub_portstatus(controller, i);
+		DEBUG_HOST("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+			i,
+			temp,
+			(temp & RH_PS_PRSC) ? " PRSC" : "",
+			(temp & RH_PS_OCIC) ? " OCIC" : "",
+			(temp & RH_PS_PSSC) ? " PSSC" : "",
+			(temp & RH_PS_PESC) ? " PESC" : "",
+			(temp & RH_PS_CSC) ? " CSC" : "",
+
+			(temp & RH_PS_LSDA) ? " LSDA" : "",
+			(temp & RH_PS_PPS) ? " PPS" : "",
+			(temp & RH_PS_PRS) ? " PRS" : "",
+			(temp & RH_PS_POCI) ? " POCI" : "",
+			(temp & RH_PS_PSS) ? " PSS" : "",
+
+			(temp & RH_PS_PES) ? " PES" : "",
+			(temp & RH_PS_CCS) ? " CCS" : ""
+			);
+	}
+}
+
+static void ohci_dump(ohci_t *controller, int verbose)
+{
+	DEBUG_HOST("OHCI controller usb-%s state", controller->slot_name);
+	/* dumps some of the state we know about */
+	ohci_dump_status(controller);
+	if(verbose)
+		ep_print_int_eds(controller, "hcca");
+	DEBUG_HOST("hcca frame #%04x", controller->hcca->frame_no);
+	ohci_dump_roothub(controller, 1);
+}
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
+{
+	ohci_t *ohci;
+	ed_t *ed;
+	urb_priv_t *purb_priv = urb;
+	int i, size = 0;
+	struct usb_device *dev = urb->dev;
+	unsigned long pipe = urb->pipe;
+	void *buffer = urb->transfer_buffer;
+	int transfer_len = urb->transfer_buffer_length;
+	int interval = urb->interval;
+	ohci = &gohci;
+	/* when controller's hung, permit only roothub cleanup attempts
+	 * such as powering down ports */
+	if(ohci->disabled)
+	{
+		err("sohci_submit_job: EPIPE");
+		return -1;
+	}
+	/* we're about to begin a new transaction here so mark the
+	 * URB unfinished */
+	urb->finished = 0;
+	/* every endpoint has a ed, locate and fill it */
+	ed = ep_add_ed(dev, pipe, interval, 1);
+	if(!ed)
+	{
+		err("sohci_submit_job: ENOMEM");
+		return -1;
+	}
+	/* for the private part of the URB we need the number of TDs (size) */
+	switch(usb_pipetype(pipe))
+	{
+		case PIPE_BULK: /* one TD for every 4096 Byte */
+			size = (transfer_len - 1) / 4096 + 1;
+			break;
+		case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+			size = (transfer_len == 0) ? 2: (transfer_len - 1) / 4096 + 3;
+			break;
+		case PIPE_INTERRUPT: /* 1 TD */
+			size = 1;
+			break;
+	}
+	ed->purb = urb;
+	if(size >= (N_URB_TD - 1))
+	{
+		err("need %d TDs, only have %d", size, N_URB_TD);
+		return -1;
+	}
+	purb_priv->pipe = pipe;
+	/* fill the private part of the URB */
+	purb_priv->length = size;
+	purb_priv->ed = ed;
+	purb_priv->actual_length = 0;
+	/* allocate the TDs */
+	/* note that td[0] was allocated in ep_add_ed */
+	for(i = 0; i < size; i++)
+	{
+		purb_priv->td[i] = td_alloc(dev);
+		if(!purb_priv->td[i])
+		{
+			purb_priv->length = i;
+			urb_free_priv(purb_priv);
+			err("sohci_submit_job: ENOMEM");
+			return -1;
+		}
+	}
+	if(ed->state == ED_NEW || (ed->state & ED_DEL))
+	{
+		urb_free_priv(purb_priv);
+		err("sohci_submit_job: EINVAL");
+		return -1;
+	}
+	/* link the ed into a chain if is not already */
+	if(ed->state != ED_OPER)
+		ep_link(ohci, ed);
+	/* fill the TDs and link it to the ed */
+	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+	return 0;
+}
+
+static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
+{
+	struct ohci_regs *regs = hc->regs;
+	switch(usb_pipetype(urb->pipe))
+	{
+		case PIPE_INTERRUPT:
+			/* implicitly requeued */
+			if(urb->dev->irq_handle && (urb->dev->irq_act_len = urb->actual_length))
+			{
+				writel(OHCI_INTR_WDH, &regs->intrenable);
+				readl(&regs->intrenable); /* PCI posting flush */
+ 				/* call interrupt device routine */
+ 				DEBUG_HOST("irq_handle device %d", urb->dev->devnum);
+				urb->dev->irq_handle(urb->dev);
+				writel(OHCI_INTR_WDH, &regs->intrdisable);
+				readl(&regs->intrdisable); /* PCI posting flush */
+			}
+			urb->actual_length = 0;
+			td_submit_job(urb->dev,	urb->pipe, urb->transfer_buffer, urb->transfer_buffer_length, NULL, urb, urb->interval);
+			break;
+		case PIPE_CONTROL:
+		case PIPE_BULK:
+			break;
+		default:
+			return 0;
+	}
+	return 1;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#if DEBUG_HOST_LAYER
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number(struct usb_device *usb_dev)
+{
+	ohci_t *ohci = &gohci;
+	return m16_swap(ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* search for the right branch to insert an interrupt ed into the int tree
+ * do some load ballancing;
+ * returns the branch and
+ * sets the interval to interval = 2^integer (ld (interval)) */
+
+static int ep_int_ballance(ohci_t *ohci, int interval, int load)
+{
+	int i, branch = 0;
+	/* search for the least loaded interrupt endpoint
+	 * branch of all 32 branches
+	 */
+	for (i = 0; i < 32; i++)
+		if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
+			branch = i;
+
+	branch = branch % interval;
+	for (i = branch; i < 32; i += interval)
+		ohci->ohci_int_load [i] += load;
+
+	return branch;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*  2^int( ld (inter)) */
+
+static int ep_2_n_interval(int inter)
+{
+	int i;
+	for(i = 0; ((inter >> i) > 1) && (i < 5); i++);
+	return 1 << i;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* the int tree is a binary tree
+ * in order to process it sequentially the indexes of the branches have to
+ * be mapped the mapping reverses the bits of a word of num_bits length */
+static int ep_rev(int num_bits, int word)
+{
+	int i, wout = 0;
+	for(i = 0; i < num_bits; i++)
+		wout |= (((word >> i) & 1) << (num_bits - i - 1));
+	return wout;
+}
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link(ohci_t *ohci, ed_t *edi)
+{
+	volatile ed_t *ed = edi;
+	int int_branch;
+	int i;
+	int inter;
+	int interval;
+	int load;
+	__u32 *ed_p;
+	ed->state = ED_OPER;
+	ed->int_interval = 0;
+	switch(ed->type)
+	{     
+		case PIPE_CONTROL:
+			ed->hwNextED = 0;
+			if(ohci->ed_controltail == NULL)
+				writel(ed - ohci->dma_offset, &ohci->regs->ed_controlhead);
+			else
+				ohci->ed_controltail->hwNextED = m32_swap((unsigned long)ed - ohci->dma_offset); 	
+			ed->ed_prev = ohci->ed_controltail;
+			if(!ohci->ed_controltail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping)
+			{
+				ohci->hc_control |= OHCI_CTRL_CLE;
+				writel(ohci->hc_control, &ohci->regs->control);
+			}
+			ohci->ed_controltail = edi;
+			break;
+		case PIPE_BULK:
+			ed->hwNextED = 0;
+			if(ohci->ed_bulktail == NULL)
+				writel(ed - ohci->dma_offset, &ohci->regs->ed_bulkhead);
+			else
+				ohci->ed_bulktail->hwNextED = m32_swap((unsigned long)ed - ohci->dma_offset);	
+			ed->ed_prev = ohci->ed_bulktail;
+			if(!ohci->ed_bulktail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping)
+			{
+				ohci->hc_control |= OHCI_CTRL_BLE;
+				writel(ohci->hc_control, &ohci->regs->control);
+			}
+			ohci->ed_bulktail = edi;
+			break; 	
+		case PIPE_INTERRUPT:
+			load = ed->int_load;
+			interval = ep_2_n_interval(ed->int_period);
+			ed->int_interval = interval;
+			int_branch = ep_int_ballance(ohci, interval, load);
+			ed->int_branch = int_branch;
+			for(i = 0; i < ep_rev(6, interval); i += inter)
+			{
+				inter = 1;
+				for(ed_p = &(ohci->hcca->int_table[ep_rev(5, i) + int_branch]);
+				 (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
+				 ed_p = &(((ed_t *)ed_p)->hwNextED))
+					inter = ep_rev(6, ((ed_t *)ed_p)->int_interval);
+				ed->hwNextED = *ed_p;
+				*ed_p = m32_swap((unsigned long)ed - ohci->dma_offset);
+			}
+			break;
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* scan the periodic table to find and unlink this ED */
+static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
+			    unsigned idx, unsigned period)
+{
+	for( ;idx < NUM_INTS; idx += period)
+	{
+		__u32	*ed_p = &ohci->hcca->int_table[idx];
+		/* ED might have been unlinked through another path */
+		while(*ed_p != 0)
+		{
+			if(((struct ed *)m32_swap((unsigned long)ed_p)) == ed)
+			{
+				*ed_p = ed->hwNextED;
+				break;
+			}
+			ed_p = &(((struct ed *)m32_swap((unsigned long)ed_p))->hwNextED);
+		}
+	}
+}
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink(ohci_t *ohci, ed_t *edi)
+{
+	volatile ed_t *ed = edi;
+	int i;
+	ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
+	switch(ed->type)
+	{
+		case PIPE_CONTROL:
+			if(ed->ed_prev == NULL)
+			{
+				if(!ed->hwNextED)
+				{
+					ohci->hc_control &= ~OHCI_CTRL_CLE;
+					writel(ohci->hc_control, &ohci->regs->control);
+				}
+				writel(m32_swap(*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+			}
+			else
+				ed->ed_prev->hwNextED = ed->hwNextED;
+			if(ohci->ed_controltail == ed)
+				ohci->ed_controltail = ed->ed_prev;
+			else
+				((ed_t *)(m32_swap(*((__u32 *)&ed->hwNextED))) + ohci->dma_offset)->ed_prev = ed->ed_prev;
+			break;
+		case PIPE_BULK:
+			if(ed->ed_prev == NULL)
+			{
+				if(!ed->hwNextED)
+				{
+					ohci->hc_control &= ~OHCI_CTRL_BLE;
+					writel(ohci->hc_control, &ohci->regs->control);
+				}
+				writel(m32_swap(*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+			}
+			else
+				ed->ed_prev->hwNextED = ed->hwNextED;
+			if(ohci->ed_bulktail == ed)
+				ohci->ed_bulktail = ed->ed_prev;
+			else
+				((ed_t *)(m32_swap(*((__u32 *)&ed->hwNextED))) + ohci->dma_offset)->ed_prev = ed->ed_prev;
+			break;
+		case PIPE_INTERRUPT:
+			periodic_unlink(ohci, ed, 0, 1);
+			for(i = ed->int_branch; i < 32; i += ed->int_interval)
+				ohci->ohci_int_load[i] -= ed->int_load;
+			break;
+	}
+	ed->state = ED_UNLINK;
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the
+ * usb_set_configuration command, but the USB stack is a little bit
+ * stateless so we do it at every transaction if the state of the ed
+ * is ED_NEW then a dummy td is added and the state is changed to
+ * ED_UNLINK in all other cases the state is left unchanged the ed
+ * info fields are setted anyway even though most of them should not
+ * change
+ */
+static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, int interval, int load)
+{
+	td_t *td;
+	ed_t *ed_ret;
+	volatile ed_t *ed;
+	struct ohci_device *ohci_dev = gohci.ohci_dev;
+	ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
+	if((ed->state & ED_DEL) || (ed->state & ED_URB_DEL))
+	{
+		err("ep_add_ed: pending delete");
+		/* pending delete request */
+		return NULL;
+	}
+	if(ed->state == ED_NEW)
+	{
+		/* dummy td; end of td list for ed */
+		td = td_alloc(usb_dev);
+		ed->hwTailP = m32_swap((unsigned long)td - gohci.dma_offset);
+		ed->hwHeadP = ed->hwTailP;
+		ed->state = ED_UNLINK;
+		ed->type = usb_pipetype(pipe);
+		ohci_dev->ed_cnt++;
+	}
+	ed->hwINFO = m32_swap(usb_pipedevice(pipe)
+			| usb_pipeendpoint(pipe) << 7
+			| (usb_pipeisoc(pipe)? 0x8000: 0)
+			| (usb_pipecontrol(pipe)? 0: \
+					   (usb_pipeout(pipe)? 0x800: 0x1000))
+			| usb_pipeslow(pipe) << 13
+			| usb_maxpacket(usb_dev, pipe) << 16);
+	if(ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK)
+	{
+		ed->int_period = interval;
+		ed->int_load = load;
+	}
+	return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill(ohci_t *ohci, unsigned int info, void *data, int len,
+ struct usb_device *dev, int idx, urb_priv_t *urb_priv)
+{
+	volatile td_t *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+	int i;
+#endif
+	if(idx > urb_priv->length)
+	{
+		err("index > length");
+		return;
+	}
+	/* use this td as the next dummy */
+	td_pt = urb_priv->td[idx];
+	td_pt->hwNextTD = 0;
+	/* fill the old dummy TD */
+	td = urb_priv->td[idx] = (td_t *)((m32_swap(urb_priv->ed->hwTailP) & ~0xf) + ohci->dma_offset);
+	td->ed = urb_priv->ed;
+	td->next_dl_td = NULL;
+	td->index = idx;
+	td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+	if(usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe))
+	{
+		for(i = 0; i < len; i++)
+			printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
+		printf("\r\n");
+	}
+#endif
+	if(!len)
+		data = NULL;
+	td->hwINFO = m32_swap(info);
+	if(data != NULL)
+	{
+		td->hwCBP = m32_swap((unsigned long)data - ohci->dma_offset);
+		td->hwBE = m32_swap((unsigned long)(data + len - 1 - ohci->dma_offset));
+	}
+	else
+	{
+		td->hwCBP = 0;
+		td->hwBE = 0;
+	}
+	td->hwNextTD = m32_swap((unsigned long)td_pt - ohci->dma_offset);
+	/* append to queue */
+	td->ed->hwTailP = td->hwNextTD;
+#if 0
+	if(data)
+	{
+		int i;
+		static char buf[4096];
+		char buf2[16];
+		*buf = '\0';
+		for(i = 0; i < len; i++)
+		{
+			ltoa(buf2, (long)*(unsigned char *)(data + i), 16);
+			strcat(buf, buf2);
+			strcat(buf, " ");
+		}	 
+		err(">>>>>>td_fill: %08x %08x %08X %08X at 0x%08x", 
+		 m32_swap(td->hwINFO), m32_swap(td->hwCBP), m32_swap(td->hwNextTD), m32_swap(td->hwBE), td);
+		err(" ... %s", buf);
+	}
+	else
+		err(">>>>>>td_fill: %08x %08x %08X %08X at 0x%08x", 
+		 m32_swap(td->hwINFO), m32_swap(td->hwCBP), m32_swap(td->hwNextTD), m32_swap(td->hwBE), td);
+#endif
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+	ohci_t *ohci = &gohci;
+	int data_len = transfer_len;
+	void *data;
+	int cnt = 0;
+	__u32 info = 0;
+	unsigned int toggle = 0;
+	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle
+	 * bits for reseting */
+	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)))
+		toggle = TD_T_TOGGLE;
+	else
+	{
+		toggle = TD_T_DATA0;
+		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+	}
+	urb->td_cnt = 0;
+	if(data_len)
+		data = buffer;
+	else
+		data = NULL;
+	switch(usb_pipetype(pipe))
+	{
+		case PIPE_BULK:
+			info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+			while(data_len > 4096)
+			{
+				td_fill(ohci, info | (cnt? TD_T_TOGGLE : toggle), data, 4096, dev, cnt, urb);
+				data += 4096; data_len -= 4096; cnt++;
+			}
+			info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+			td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+			cnt++;
+			if(!ohci->sleeping)	/* start bulk list */
+				writel(OHCI_BLF, &ohci->regs->cmdstatus);
+			break;
+		case PIPE_CONTROL:
+			/* Setup phase */
+			info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+			td_fill(ohci, info, setup, 8, dev, cnt++, urb);
+			/* Optional Data phase */
+			if(data_len > 0)
+			{
+				info = usb_pipeout(pipe) ? TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+				/* NOTE:  mishandles transfers >8K, some >4K */
+				td_fill(ohci, info, data, data_len, dev, cnt++, urb);
+			}
+			/* Status phase */
+ 			info = usb_pipeout(pipe) ? TD_CC | TD_DP_IN | TD_T_DATA1 : TD_CC | TD_DP_OUT | TD_T_DATA1;
+			td_fill(ohci, info, data, 0, dev, cnt++, urb);
+			if(!ohci->sleeping) /* start Control list */
+				writel(OHCI_CLF, &ohci->regs->cmdstatus);
+			break;
+		case PIPE_INTERRUPT:
+			info = usb_pipeout(urb->pipe) ? TD_CC | TD_DP_OUT | toggle : TD_CC | TD_R | TD_DP_IN | toggle;
+			td_fill(ohci, info, data, data_len, dev, cnt++, urb);
+			break;
+	}
+	if(urb->length != cnt)
+		DEBUG_HOST("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t *td)
+{
+	__u32 tdINFO, tdBE, tdCBP;
+	urb_priv_t *lurb_priv = td->ed->purb;
+	tdINFO = m32_swap(td->hwINFO);
+	tdBE   = m32_swap(td->hwBE);
+	tdCBP  = m32_swap(td->hwCBP);
+	if(tdBE)
+		tdBE += gohci.dma_offset;
+	if(tdCBP)
+		tdCBP += gohci.dma_offset;
+	if(!(usb_pipecontrol(lurb_priv->pipe) && ((td->index == 0) || (td->index == lurb_priv->length - 1))))
+	{
+		if(tdBE != 0)
+		{
+			if(td->hwCBP == 0)
+				lurb_priv->actual_length += tdBE - td->data + 1;
+			else
+				lurb_priv->actual_length += tdCBP - td->data;
+		}
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+void check_status(td_t *td_list)
+{
+	urb_priv_t *lurb_priv = td_list->ed->purb;
+	int urb_len = lurb_priv->length;
+	__u32 *phwHeadP = &td_list->ed->hwHeadP;
+	int cc = TD_CC_GET(m32_swap(td_list->hwINFO));
+	if(cc)
+	{
+		err(" USB-error: %s (%x)", cc_to_string[cc], cc);
+		if(*phwHeadP & m32_swap(0x1))
+		{
+			if(lurb_priv && ((td_list->index + 1) < urb_len))
+			{
+				*phwHeadP = (lurb_priv->td[urb_len - 1]->hwNextTD &	m32_swap(0xfffffff0)) | (*phwHeadP & m32_swap(0x2));
+				lurb_priv->td_cnt += urb_len - td_list->index - 1;
+			}
+			else
+				*phwHeadP &= m32_swap(0xfffffff2);
+		}
+#ifdef CONFIG_MPC5200
+		td_list->hwNextTD = 0;
+#endif
+	}
+}
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+td_t *dl_reverse_done_list(ohci_t *ohci)
+{
+	__u32 td_list_hc;
+	td_t *td_rev = NULL;
+	td_t *td_list = NULL;
+	td_list_hc = m32_swap(ohci->hcca->done_head) & ~0xf;
+	if(td_list_hc)
+		td_list_hc += ohci->dma_offset;
+	ohci->hcca->done_head = 0;
+	while(td_list_hc)
+	{
+		td_list = (td_t *)td_list_hc;
+		check_status(td_list);
+		td_list->next_dl_td = td_rev;
+		td_rev = td_list;
+		td_list_hc = m32_swap(td_list->hwNextTD) & ~0xf;
+		if(td_list_hc)
+			td_list_hc += ohci->dma_offset;
+	}
+	return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+/*-------------------------------------------------------------------------*/
+
+static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
+{
+	if((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
+		urb->finished = sohci_return_job(ohci, urb);
+	else
+		DEBUG_HOST("finish_urb: strange.., ED state %x, \r\n", status);
+}
+
+/*
+ * Used to take back a TD from the host controller. This would normally be
+ * called from within dl_done_list, however it may be called directly if the
+ * HC no longer sees the TD and it has not appeared on the donelist (after
+ * two frames).  This bug has been observed on ZF Micro systems.
+ */
+int takeback_td(ohci_t *ohci, td_t *td_list)
+{
+	ed_t *ed;
+	int cc;
+	int stat = 0;
+	/* urb_t *urb; */
+	urb_priv_t *lurb_priv;
+	__u32 tdINFO, edHeadP, edTailP;
+	tdINFO = m32_swap(td_list->hwINFO);
+	ed = td_list->ed;
+	lurb_priv = ed->purb;
+	dl_transfer_length(td_list);
+	lurb_priv->td_cnt++;
+	/* error code of transfer */
+	cc = TD_CC_GET(tdINFO);
+	if(cc)
+	{
+		err("USB-error: %s (%x)", cc_to_string[cc], cc);
+		stat = cc_to_error[cc];
+	}
+	/* see if this done list makes for all TD's of current URB,
+	* and mark the URB finished if so */
+	if(lurb_priv->td_cnt == lurb_priv->length)
+		finish_urb(ohci, lurb_priv, ed->state);
+	DEBUG_HOST("dl_done_list: processing TD %x, len %x\r\n",
+		lurb_priv->td_cnt, lurb_priv->length);
+	if(ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe)))
+	{
+		edHeadP = m32_swap(ed->hwHeadP) & ~0xf;
+		edTailP = m32_swap(ed->hwTailP);
+		/* unlink eds if they are not busy */
+		if((edHeadP == edTailP) && (ed->state == ED_OPER))
+			ep_unlink(ohci, ed);
+	}
+	return stat;
+}
+
+int dl_done_list(ohci_t *ohci)
+{
+	int stat = 0;
+	td_t *td_list = dl_reverse_done_list(ohci);
+	while(td_list)
+	{
+		td_t *td_next = td_list->next_dl_td;
+		stat = takeback_td(ohci, td_list);
+		td_list = td_next;
+	}
+	return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+	0x12,	    /*	__u8  bLength; */
+	0x01,	    /*	__u8  bDescriptorType; Device */
+	0x10,	    /*	__u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,	    /*	__u8  bDeviceSubClass; */
+	0x00,	    /*	__u8  bDeviceProtocol; */
+	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
+	0x00,	    /*	__u16 idVendor; */
+	0x00,
+	0x00,	    /*	__u16 idProduct; */
+	0x00,
+	0x00,	    /*	__u16 bcdDevice; */
+	0x00,
+	0x00,	    /*	__u8  iManufacturer; */
+	0x01,	    /*	__u8  iProduct; */
+	0x00,	    /*	__u8  iSerialNumber; */
+	0x01	    /*	__u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+	0x09,	    /*	__u8  bLength; */
+	0x02,	    /*	__u8  bDescriptorType; Configuration */
+	0x19,	    /*	__u16 wTotalLength; */
+	0x00,
+	0x01,	    /*	__u8  bNumInterfaces; */
+	0x01,	    /*	__u8  bConfigurationValue; */
+	0x00,	    /*	__u8  iConfiguration; */
+	0x40,	    /*	__u8  bmAttributes;
+	 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,	    /*	__u8  MaxPower; */
+
+	/* interface */
+	0x09,	    /*	__u8  if_bLength; */
+	0x04,	    /*	__u8  if_bDescriptorType; Interface */
+	0x00,	    /*	__u8  if_bInterfaceNumber; */
+	0x00,	    /*	__u8  if_bAlternateSetting; */
+	0x01,	    /*	__u8  if_bNumEndpoints; */
+	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,	    /*	__u8  if_bInterfaceSubClass; */
+	0x00,	    /*	__u8  if_bInterfaceProtocol; */
+	0x00,	    /*	__u8  if_iInterface; */
+
+	/* endpoint */
+	0x07,	    /*	__u8  ep_bLength; */
+	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
+	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
+	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
+	0xff	    /*	__u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+	28,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'O',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'C',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'I',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x)			len = (x); break
+#if DEBUG_HOST_LAYER
+#define WR_RH_STAT(x)		{info("WR:status %#8x", (x)); writel((x), \
+						&gohci.regs->roothub.status); }
+#define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, \
+		(x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
+#else
+#define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)	writel((x), \
+				    &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT		roothub_status(&gohci)
+#define RD_RH_PORTSTAT		roothub_portstatus(&gohci, wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+	__u32 temp, ndp, i;
+	int res = -1;
+	temp = roothub_a(controller);
+	ndp = (temp & RH_A_NDP);
+	for (i = 0; i < ndp; i++) {
+		temp = roothub_portstatus(controller, i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+			(RH_PS_PESC | RH_PS_CSC)) &&
+			((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+		void *buffer, int transfer_len, struct devrequest *cmd)
+{
+	void *data = buffer;
+	int leni = transfer_len;
+	int len = 0;
+	int stat = 0;
+	__u32 datab[4];
+	__u8 *data_buf = (__u8 *)datab;
+	__u16 bmRType_bReq;
+	__u16 wValue;
+	__u16 wIndex;
+	__u16 wLength;
+#if DEBUG_HOST_LAYER
+	pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	if(usb_pipeint(pipe))
+	{
+		info("Root-Hub submit IRQ: NOT implemented");
+		return 0;
+	}
+	bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
+	wValue	      = le16_to_cpu(cmd->value);
+	wIndex	      = le16_to_cpu(cmd->index);
+	wLength	      = le16_to_cpu(cmd->length);
+	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+		dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+	switch(bmRType_bReq)
+	{
+		/* Request Destination:
+		   without flags: Device,
+		   RH_INTERFACE: interface,
+		   RH_ENDPOINT: endpoint,
+		   RH_CLASS means HUB here,
+		   RH_OTHER | RH_CLASS	almost ever means HUB_PORT here
+		*/
+		case RH_GET_STATUS:
+			*(__u16 *)data_buf = cpu_to_le16(1);
+			OK(2);
+		case RH_GET_STATUS | RH_INTERFACE:
+			*(__u16 *)data_buf = cpu_to_le16(0);
+			OK(2);
+		case RH_GET_STATUS | RH_ENDPOINT:
+			*(__u16 *)data_buf = cpu_to_le16(0);
+			OK(2);
+		case RH_GET_STATUS | RH_CLASS:
+			*(__u32 *)data_buf = cpu_to_le32(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+			OK(4);
+		case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+			*(__u32 *)data_buf = cpu_to_le32(RD_RH_PORTSTAT);
+			OK(4);
+		case RH_CLEAR_FEATURE | RH_ENDPOINT:
+			switch(wValue)
+			{
+				case (RH_ENDPOINT_STALL): OK(0);
+			}
+			break;
+		case RH_CLEAR_FEATURE | RH_CLASS:
+			switch(wValue)
+			{
+				case RH_C_HUB_LOCAL_POWER: OK(0);
+				case (RH_C_HUB_OVER_CURRENT): WR_RH_STAT(RH_HS_OCIC); OK(0);
+			}
+			break;
+		case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+			switch(wValue)
+			{
+				case (RH_PORT_ENABLE):        WR_RH_PORTSTAT(RH_PS_CCS);  OK(0);
+				case (RH_PORT_SUSPEND):       WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
+				case (RH_PORT_POWER):         WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
+				case (RH_C_PORT_CONNECTION):  WR_RH_PORTSTAT(RH_PS_CSC);  OK(0);
+				case (RH_C_PORT_ENABLE):      WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
+				case (RH_C_PORT_SUSPEND):     WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
+				case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
+				case (RH_C_PORT_RESET):       WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
+			}
+			break;
+		case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+			switch(wValue)
+			{
+				case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSS);  OK(0);
+				case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+					if(RD_RH_PORTSTAT & RH_PS_CCS)
+						WR_RH_PORTSTAT(RH_PS_PRS);
+					OK(0);
+				case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_PPS); wait_ms(100); OK(0);
+				case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+					if(RD_RH_PORTSTAT & RH_PS_CCS)
+						WR_RH_PORTSTAT(RH_PS_PES);
+					OK(0);
+			}
+			break;
+		case RH_SET_ADDRESS:
+			gohci.rh.devnum = wValue;
+			OK(0);
+		case RH_GET_DESCRIPTOR:
+			switch((wValue & 0xff00) >> 8)
+			{
+				case(0x01): /* device descriptor */
+					len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_dev_des), wLength));
+					data_buf = root_hub_dev_des;
+					OK(len);
+				case(0x02): /* configuration descriptor */
+					len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_config_des), wLength));
+					data_buf = root_hub_config_des;
+					OK(len);
+				case(0x03): /* string descriptors */
+					if(wValue == 0x0300)
+					{
+						len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_str_index0), wLength));
+						data_buf = root_hub_str_index0;
+						OK(len);
+					}
+					if(wValue == 0x0301)
+					{
+						len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_str_index1), wLength));
+						data_buf = root_hub_str_index1;
+						OK(len);
+					}
+				default:
+					stat = USB_ST_STALLED;
+			}
+			break;
+		case RH_GET_DESCRIPTOR | RH_CLASS:
+		{
+			__u32 temp = roothub_a(&gohci);
+			data_buf[0] = 9;		/* min length; */
+			data_buf[1] = 0x29;
+			data_buf[2] = temp & RH_A_NDP;
+			data_buf[3] = 0;
+			if(temp & RH_A_PSM)	/* per-port power switching? */
+				data_buf[3] |= 0x1;
+			if(temp & RH_A_NOCP)	/* no overcurrent reporting? */
+				data_buf[3] |= 0x10;
+			else if(temp & RH_A_OCPM) /* per-port overcurrent reporting? */
+				data_buf[3] |= 0x8;
+			/* corresponds to data_buf[4-7] */
+			datab[1] = 0;
+			data_buf[5] = (temp & RH_A_POTPGT) >> 24;
+			temp = roothub_b(&gohci);
+			data_buf[7] = temp & RH_B_DR;
+			if(data_buf[2] < 7)
+				data_buf[8] = 0xff;
+			else
+			{
+				data_buf[0] += 2;
+				data_buf[8] = (temp & RH_B_DR) >> 8;
+				data_buf[10] = data_buf[9] = 0xff;
+			}
+			len = min_t(unsigned int, leni, min2_t(unsigned int, data_buf [0], wLength));
+			OK(len);
+		}
+		case RH_GET_CONFIGURATION:	*(__u8 *) data_buf = 0x01; OK(1);
+		case RH_SET_CONFIGURATION:	WR_RH_STAT(0x10000); OK(0);
+		default:
+			DEBUG_HOST("unsupported root hub command");
+			stat = USB_ST_STALLED;
+	}
+#if DEBUG_HOST_LAYER
+	ohci_dump_roothub(&gohci, 1);
+#else
+//	wait_ms(1);
+#endif
+	len = min_t(int, len, leni);
+	if(data != data_buf)
+		memcpy(data, data_buf, len);
+	dev->act_len = len;
+	dev->status = stat;
+#if DEBUG_HOST_LAYER
+	pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+//	wait_ms(1);
+#endif
+	return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub accesses. */
+
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int transfer_len, struct devrequest *setup, int interval)
+{
+	int stat = 0;
+	int maxsize = usb_maxpacket(dev, pipe);
+	int timeout;
+	urb_priv_t *urb;
+	urb = (urb_priv_t *)usb_malloc(sizeof(urb_priv_t));
+	if(urb == NULL)
+	{
+		err("submit_common_msg malloc failed");
+		return -1;
+	}
+	memset(urb, 0, sizeof(urb_priv_t));
+	urb->dev = dev;
+	urb->pipe = pipe;
+	urb->transfer_buffer = buffer;
+	urb->transfer_buffer_length = transfer_len;
+	urb->interval = interval;
+	/* device pulled? Shortcut the action. */
+	if(devgone == dev)
+	{
+		dev->status = USB_ST_CRC_ERR;
+		return 0;
+	}
+#if DEBUG_HOST_LAYER
+	urb->actual_length = 0;
+	pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	if(!maxsize)
+	{
+		err("submit_common_message: pipesize for pipe %lx is zero", pipe);
+		return -1;
+	}
+	if(sohci_submit_job(urb, setup) < 0)
+	{
+		err("sohci_submit_job failed");
+		return -1;
+	}
+#if 0
+	wait_ms(10);
+	/* ohci_dump_status(&gohci); */
+#endif
+	/* allow more time for a BULK device to react - some are slow */
+#define BULK_TO	 5000	/* timeout in milliseconds */
+	if(usb_pipebulk(pipe))
+		timeout = BULK_TO;
+	else
+		timeout = 100;
+	/* wait for it to complete */
+	while(1)
+	{
+		/* check whether the controller is done */
+#ifdef COLDFIRE /* no bus snooping on Coldfire */
+#ifdef NETWORK
+#ifdef LWIP
+		extern unsigned long pxCurrentTCB, tid_TOS;
+		extern void flush_caches(void);
+		if(pxCurrentTCB != tid_TOS)
+			flush_caches();
+		else
+#endif /* LWIP */
+#endif /* NETWORK */
+			asm(" .chip 68060\n cpusha DC\n .chip 5200\n");
+#endif /* COLDFIRE */
+		stat = hc_interrupt();
+		if(stat < 0)
+		{
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+		/* NOTE: since we are not interrupt driven in U-Boot and always
+		 * handle only one URB at a time, we cannot assume the
+		 * transaction finished on the first successful return from
+		 * hc_interrupt().. unless the flag for current URB is set,
+		 * meaning that all TD's to/from device got actually
+		 * transferred and processed. If the current URB is not
+		 * finished we need to re-iterate this loop so as
+		 * hc_interrupt() gets called again as there needs to be some
+		 * more TD's to process still */
+		if((stat >= 0) && (stat != 0xff) && (urb->finished))
+		{
+			/* 0xff is returned for an SF-interrupt */
+			break;
+		}
+		if(--timeout)
+		{
+			wait_ms(1);
+			if(!urb->finished)
+				DEBUG_HOST("*");
+		}
+		else
+		{
+			err("CTL:TIMEOUT ");
+			DEBUG_HOST("submit_common_msg: TO status %x\r\n", stat);
+			urb->finished = 1;
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+	}
+	dev->status = stat;
+	dev->act_len = transfer_len;
+#if DEBUG_HOST_LAYER
+	pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	/* free TDs in urb_priv */
+	if(!usb_pipeint(pipe))
+		urb_free_priv(urb);
+	return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len)
+{
+	info("submit_bulk_msg");
+	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, struct devrequest *setup)
+{
+	int maxsize = usb_maxpacket(dev, pipe);
+	info("submit_control_msg");
+#if DEBUG_HOST_LAYER
+	pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	if(!maxsize)
+	{
+		err("submit_control_message: pipesize for pipe %lx is zero", pipe);
+		return -1;
+	}
+	if(((pipe >> 8) & 0x7f) == gohci.rh.devnum)
+	{
+		gohci.rh.dev = dev;
+		/* root hub - redirect */
+		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, setup);
+	}
+	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval)
+{
+	info("submit_int_msg");
+	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, interval);
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset(ohci_t *ohci)
+{
+	int timeout = 30;
+	int smm_timeout = 50; /* 0,5 sec */
+	DEBUG_HOST("%s\r\n", __FUNCTION__);
+	if(readl(&ohci->regs->control) & OHCI_CTRL_IR)
+	{
+		/* SMM owns the HC */
+		writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */
+		info("USB HC TakeOver from SMM");
+		while(readl(&ohci->regs->control) & OHCI_CTRL_IR)
+		{
+			wait_ms(10);
+			if(--smm_timeout == 0)
+			{
+				err("USB HC TakeOver failed!");
+				return -1;
+			}
+		}
+	}
+	/* Disable HC interrupts */
+	writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
+	DEBUG_HOST("USB HC reset_hc usb-%s: ctrl = 0x%X ;\r\n", ohci->slot_name, readl(&ohci->regs->control));
+	/* Reset USB (needed by some controllers) */
+	ohci->hc_control = 0;
+	writel(ohci->hc_control, &ohci->regs->control);
+	/* HC Reset requires max 10 us delay */
+	writel(OHCI_HCR,  &ohci->regs->cmdstatus);
+	while((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0)
+	{
+		if(--timeout == 0)
+		{
+			err("USB HC reset timed out!");
+			return -1;
+		}
+		udelay(1);
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start(ohci_t *ohci)
+{
+	__u32 mask;
+	unsigned int fminterval;
+	ohci->disabled = 1;
+	/* Tell the controller where the control and bulk lists are
+	 * The lists are empty now. */
+	writel(0, &ohci->regs->ed_controlhead);
+	writel(0, &ohci->regs->ed_bulkhead);
+	writel((__u32)ohci->hcca - ohci->dma_offset, &ohci->regs->hcca); /* a reset clears this */
+	fminterval = 0x2edf;
+	writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
+	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+	writel(fminterval, &ohci->regs->fminterval);
+	writel(0x628, &ohci->regs->lsthresh);
+	/* start controller operations */
+	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+	ohci->disabled = 0;
+	writel(ohci->hc_control, &ohci->regs->control);
+	/* disable all interrupts */
+	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | OHCI_INTR_OC | OHCI_INTR_MIE);
+	writel(mask, &ohci->regs->intrdisable);
+	/* clear all interrupts */
+	mask &= ~OHCI_INTR_MIE;
+	writel(mask, &ohci->regs->intrstatus);
+	/* Choose the interrupts we care about now  - but w/o MIE */
+	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+	writel(mask, &ohci->regs->intrenable);
+#ifdef OHCI_USE_NPS
+	/* required for AMD-756 and some Mac platforms */
+	writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, &ohci->regs->roothub.a);
+	writel(RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+	/* POTPGT delay is bits 24-31, in 2 ms units. */
+	mdelay((roothub_a(ohci) >> 23) & 0x1fe);
+	/* connect the virtual root hub */
+	ohci->rh.devnum = 0;
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USB_INTERRUPT_POLLING
+
+/* Poll USB interrupt. */
+void usb_event_poll(void)
+{
+	if(ohci_inited)
+	{
+#ifdef COLDFIRE /* no bus snooping on Coldfire */
+#ifdef NETWORK
+#ifdef LWIP
+		extern unsigned long pxCurrentTCB, tid_TOS;
+		extern void flush_caches(void);
+		if(pxCurrentTCB != tid_TOS)
+			flush_caches();
+		else
+#endif /* LWIP */
+#endif /* NETWORK */
+		asm(" .chip 68060\n cpusha DC\n .chip 5200\n");
+#endif /* COLDFIRE */
+		hc_interrupt();
+	}
+}
+
+#endif /* CONFIG_USB_INTERRUPT_POLLING */
+
+/* an interrupt happens */
+static int hc_interrupt(void)
+{
+	ohci_t *ohci = &gohci;
+	struct ohci_regs *regs = ohci->regs;
+	int ints, stat = -1;
+	if((ohci->hcca->done_head != 0) && !(m32_swap(ohci->hcca->done_head) & 0x01))
+		ints =  OHCI_INTR_WDH;
+	else
+	{
+		ints = readl(&regs->intrstatus);
+		if(ints == ~(u32)0)
+		{
+			ohci->disabled++;
+			err("%s device removed!", ohci->slot_name);
+			return -1;
+		}
+		else
+		{
+			ints &= readl(&regs->intrenable);
+			if(ints == 0)
+			{
+//				DEBUG_HOST("hc_interrupt: returning..\r\n");
+				return 0xff;
+			}
+		}
+	}
+  DEBUG_HOST("Interrupt: 0x%x frame: 0x%x", ints, le16_to_cpu(ohci->hcca->frame_no));
+	if(ints & OHCI_INTR_RHSC)
+	{
+		stat = 0xff;
+	}
+	if(ints & OHCI_INTR_UE)
+	{
+		ohci->disabled++;
+		err("OHCI Unrecoverable Error, controller usb-%s disabled", ohci->slot_name);
+		/* e.g. due to PCI Master/Target Abort */
+#if DEBUG_HOST_LAYER
+		ohci_dump(ohci, 1);
+#else
+//		wait_ms(1);
+#endif
+		/* FIXME: be optimistic, hope that bug won't repeat often. */
+		/* Make some non-interrupt context restart the controller. */
+		/* Count and limit the retries though; either hardware or */
+		/* software errors can go forever... */
+		hc_reset(ohci);
+		return -1;
+	}
+	if(ints & OHCI_INTR_WDH)
+	{
+//		wait_ms(1);
+		writel(OHCI_INTR_WDH, &regs->intrdisable);
+		(void)readl(&regs->intrdisable); /* flush */
+		stat = dl_done_list(&gohci);
+		writel(OHCI_INTR_WDH, &regs->intrenable);
+		(void)readl(&regs->intrdisable); /* flush */
+	}
+	if(ints & OHCI_INTR_SO)
+	{
+		DEBUG_HOST("USB Schedule overrun\r\n");
+		writel(OHCI_INTR_SO, &regs->intrenable);
+		stat = -1;
+	}
+	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
+	if(ints & OHCI_INTR_SF)
+	{
+		unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
+//		wait_ms(1);
+		writel(OHCI_INTR_SF, &regs->intrdisable);
+		if(ohci->ed_rm_list[frame] != NULL)
+			writel(OHCI_INTR_SF, &regs->intrenable);
+		stat = 0xff;
+	}
+	writel(ints, &regs->intrstatus);
+	return stat;
+}
+
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+
+static int handle_usb_interrupt(void)
+{
+#ifdef COLDFIRE /* no bus snooping on Coldfire */
+	extern void flush_caches(void);
+	conout_debug('.');
+	flush_caches(); /* native interrupt */
+#endif /* COLDFIRE */
+	gohci.irq = 0;
+	hc_interrupt();
+	gohci.irq = -1;
+	return 1; /* clear interrupt, 0: disable interrupt */
+}
+
+void usb_enable_interrupt(int enable)
+{
+	ohci_t *ohci = &gohci;
+	if(enable)
+		writel(OHCI_INTR_MIE, &ohci->regs->intrenable);
+	else
+		writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
+}
+
+#endif /* !CONFIG_USB_INTERRUPT_POLLING */
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci(ohci_t *ohci)
+{
+	DEBUG_HOST("USB HC release ohci usb-%s", ohci->slot_name);
+	if(!ohci->disabled)
+		hc_reset(ohci);
+}
+
+static void hc_free_buffers(ohci_t *ohci)
+{
+	if(ohci->td_unaligned != NULL)
+	{
+		usb_free(ohci->td_unaligned);
+		ohci->td_unaligned = NULL;
+	}
+	if(ohci->ohci_dev_unaligned != NULL)
+	{
+		usb_free(ohci->ohci_dev_unaligned);
+		ohci->ohci_dev_unaligned = NULL;
+	}
+	if(ohci->hcca_unaligned  != NULL)
+	{
+		usb_free(ohci->hcca_unaligned);
+		ohci->hcca_unaligned = NULL;
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+int usb_lowlevel_init(long handle, const struct pci_device_id *ent)
+{
+	char buf[16];
+	unsigned long usb_base_addr = 0xFFFFFFFF;
+	PCI_RSC_DESC *pci_rsc_desc;
+#ifdef PCI_XBIOS
+	pci_rsc_desc = (PCI_RSC_DESC *)get_resource(handle); /* USB OHCI */
+#else
+	COOKIE *p = get_cookie('_PCI'); 
+  	PCI_COOKIE *bios_cookie = (PCI_COOKIE *)p->v.l;
+	if(bios_cookie == NULL)   /* faster than XBIOS calls */
+		return(-1);	
+	tab_funcs_pci = &bios_cookie->routine[0];
+	pci_rsc_desc = (PCI_RSC_DESC *)Get_resource(handle); /* USB OHCI */
+#endif
+	if(handle && (ent != NULL))
+	{
+		memset(&gohci, 0, sizeof(ohci_t));
+		gohci.handle = handle;
+	}
+	else if(!gohci.handle) /* for restart USB cmd */
+		return(-1);	
+	/* this must be aligned to a 256 byte boundary */
+	gohci.hcca_unaligned = (struct ohci_hcca *)usb_malloc(sizeof(struct ohci_hcca) + 256);
+	if(gohci.hcca_unaligned == NULL)
+	{
+		err("HCCA malloc failed");
+		return -1;
+	}
+	/* align the storage */
+	gohci.hcca = (struct ohci_hcca *)(((unsigned long)gohci.hcca_unaligned + 255) & ~255);
+	memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
+	info("aligned ghcca 0x%p", gohci.hcca);
+	gohci.ohci_dev_unaligned = (struct ohci_device *)usb_malloc(sizeof(struct ohci_device) + 8);
+	if(gohci.ohci_dev_unaligned == NULL)
+	{
+		err("EDs malloc failed");
+		hc_free_buffers(&gohci);
+		return -1;
+	}
+	gohci.ohci_dev = (struct ohci_device *)(((unsigned long)gohci.ohci_dev_unaligned + 7) & ~7);
+	memset(gohci.ohci_dev, 0, sizeof(struct ohci_device));
+	info("aligned EDs 0x%p", gohci.ohci_dev);
+	gohci.td_unaligned = (td_t *)usb_malloc(sizeof(td_t) * (NUM_TD + 1));
+	if(gohci.td_unaligned == NULL)
+	{
+		err("TDs malloc failed");
+		hc_free_buffers(&gohci);
+		return -1;
+	}
+	ptd = (td_t *)(((unsigned long)gohci.td_unaligned + 7) & ~7);
+	memset(ptd, 0, sizeof(td_t) * NUM_TD);
+	info("aligned TDs 0x%p", ptd);
+	gohci.disabled = 1;
+	gohci.sleeping = 0;
+	gohci.irq = -1;
+	if((long)pci_rsc_desc >= 0)
+	{
+		unsigned short flags;
+		do
+		{
+			DEBUG_HOST("PCI USB descriptors: flags 0x%08x start 0x%08x \r\n offset 0x%08x dmaoffset 0x%08x length 0x%08x",
+				 pci_rsc_desc->flags, pci_rsc_desc->start, pci_rsc_desc->offset, pci_rsc_desc->dmaoffset, pci_rsc_desc->length);
+			if(!(pci_rsc_desc->flags & FLG_IO))
+			{
+				if(usb_base_addr == 0xFFFFFFFF)
+				{
+					usb_base_addr = pci_rsc_desc->start;
+					gohci.regs = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start);
+					gohci.dma_offset = pci_rsc_desc->dmaoffset;
+					if((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA)
+						gohci.big_endian = 0; /* host bridge make swapping intel -> motorola */
+					else
+						gohci.big_endian = 1; /* driver must swapping intel -> motorola */
+				}
+			}
+			flags = pci_rsc_desc->flags;
+			pci_rsc_desc += (unsigned long)pci_rsc_desc->next;
+		}
+		while(!(flags & FLG_LAST));
+	}
+	else
+	{
+		hc_free_buffers(&gohci);
+		return(-1); /* get_resource error */
+	}
+	if(usb_base_addr == 0xFFFFFFFF)
+	{
+		hc_free_buffers(&gohci);
+		return(-1);
+	}
+	if(handle && (ent != NULL))
+	{
+		switch(ent->vendor)
+		{
+			case PCI_VENDOR_ID_AL: gohci.slot_name = "uli1575"; break;
+			case PCI_VENDOR_ID_NEC: gohci.slot_name = "uPD720101"; break;
+			case PCI_VENDOR_ID_PHILIPS: gohci.slot_name = "isp1561"; break;
+			default: gohci.slot_name = "generic"; break;
+		}
+	}
+	(void) Cconws("OHCI usb-");
+	(void) Cconws(gohci.slot_name);
+	(void) Cconws(", regs address 0x");
+	ltoa(buf, (long)gohci.regs, 16);
+	(void) Cconws(buf);
+	(void) Cconws(", PCI handle 0x");
+	ltoa(buf, handle, 16);
+	(void) Cconws(buf);
+	(void) Cconws("\r\n");
+	gohci.flags = 0;
+	if(hc_reset(&gohci) < 0)
+	{
+		err("Can't reset usb-%s", gohci.slot_name);
+		hc_release_ohci(&gohci);
+		hc_free_buffers(&gohci);
+		return -1;
+	}
+	if(hc_start(&gohci) < 0)
+	{
+		err("Can't start usb-%s", gohci.slot_name);
+		hc_release_ohci(&gohci);
+		hc_free_buffers(&gohci);
+		/* Initialization failed */
+		return -1;
+	}
+#if DEBUG_HOST_LAYER
+	ohci_dump(&gohci, 1);
+#else
+//	wait_ms(1);
+#endif
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+#ifdef PCI_XBIOS
+	hook_interrupt(handle, handle_usb_interrupt, NULL);
+#else
+	Hook_interrupt(handle, (void *)handle_usb_interrupt, NULL);
+#endif /* PCI_BIOS */
+#endif /* CONFIG_USB_INTERRUPT_POLLING */
+	ohci_inited = 1;
+	return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+	/* this gets called really early - before the controller has */
+	/* even been initialized! */
+	if(!ohci_inited)
+		return 0;
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+#ifdef PCI_XBIOS
+	unhook_interrupt(gohci.handle);
+#else
+	Unhook_interrupt(gohci.handle);
+#endif /* PCI_BIOS */
+#endif /* CONFIG_USB_INTERRUPT_POLLING */
+	/* call hc_release_ohci() here ? */
+	hc_reset(&gohci);
+	hc_free_buffers(&gohci);
+	/* This driver is no longer initialised. It needs a new low-level
+	 * init (board/cpu) before it can be used again. */
+	ohci_inited = 0;
+	return 0;
+}
diff --git a/usb/store/host/ohci-pci/ohci.h b/usb/store/host/ohci-pci/ohci.h
new file mode 100644
index 0000000..b07e3b2
--- /dev/null
+++ b/usb/store/host/ohci-pci/ohci.h
@@ -0,0 +1,457 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+	/* No  Error  */	       0,
+	/* CRC Error  */	       USB_ST_CRC_ERR,
+	/* Bit Stuff  */	       USB_ST_BIT_ERR,
+	/* Data Togg  */	       USB_ST_CRC_ERR,
+	/* Stall      */	       USB_ST_STALLED,
+	/* DevNotResp */	       -1,
+	/* PIDCheck   */	       USB_ST_BIT_ERR,
+	/* UnExpPID   */	       USB_ST_BIT_ERR,
+	/* DataOver   */	       USB_ST_BUF_ERR,
+	/* DataUnder  */	       USB_ST_BUF_ERR,
+	/* reservd    */	       -1,
+	/* reservd    */	       -1,
+	/* BufferOver */	       USB_ST_BUF_ERR,
+	/* BuffUnder  */	       USB_ST_BUF_ERR,
+	/* Not Access */	       -1,
+	/* Not Access */	       -1
+};
+
+static const char *cc_to_string[16] = {
+	"No Error",
+	"CRC: Last data packet from endpoint contained a CRC error.",
+	"BITSTUFFING: Last data packet from endpoint contained a bit stuffing violation",
+	"DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID that did not match the expected value.",
+	"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
+	"DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT)",
+	"PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID (IN) or handshake (OUT)",
+	"UNEXPECTEDPID: Receive PID was not valid when encountered or PID value is not defined.",
+	"DATAOVERRUN: The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in MaximumPacketSize field of ED) or the remaining buffer size.",
+	"DATAUNDERRUN: The endpoint returned less than MaximumPacketSize and that amount was not sufficient to fill the specified buffer",
+	"reserved1",
+	"reserved2",
+	"BUFFEROVERRUN: During an IN, HC received data from endpoint faster than it could be written to system memory",
+	"BUFFERUNDERRUN: During an OUT, HC could not retrieve data from system memory fast enough to keep up with data USB data rate.",
+	"NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(1)",
+	"NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(2)",
+};
+
+/* ED States */
+
+#define ED_NEW		0x00
+#define ED_UNLINK	0x01
+#define ED_OPER		0x02
+#define ED_DEL		0x04
+#define ED_URB_DEL	0x08
+
+/* usb_ohci_ed */
+struct ed {
+	__u32 hwINFO;
+	__u32 hwTailP;
+	__u32 hwHeadP;
+	__u32 hwNextED;
+
+	struct ed *ed_prev;
+	__u8 int_period;
+	__u8 int_branch;
+	__u8 int_load;
+	__u8 int_interval;
+	__u8 state;
+	__u8 type;
+	__u16 last_iso;
+	struct ed *ed_rm_list;
+
+	struct usb_device *usb_dev;
+	void *purb;
+	__u32 unused[2];
+} __attribute__((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC	    0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC	    0x0C000000
+#define TD_T	    0x03000000
+#define TD_T_DATA0  0x02000000
+#define TD_T_DATA1  0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R	    0x00040000
+#define TD_DI	    0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP	    0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN    0x00100000
+#define TD_DP_OUT   0x00080000
+
+#define TD_ISO	    0x00010000
+#define TD_DEL	    0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR	   0x00
+#define TD_CC_CRC	   0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL	   0x04
+#define TD_DEVNOTRESP	   0x05
+#define TD_PIDCHECKFAIL	   0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN	   0x08
+#define TD_DATAUNDERRUN	   0x09
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+#define TD_NOTACCESSED	   0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+	__u32 hwINFO;
+	__u32 hwCBP;		/* Current Buffer Pointer */
+	__u32 hwNextTD;		/* Next TD Pointer */
+	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+	__u16 hwPSW[MAXPSW];
+	__u8 unused;
+	__u8 index;
+	struct ed *ed;
+	struct td *next_dl_td;
+	struct usb_device *usb_dev;
+	int transfer_len;
+	__u32 data;
+
+	__u32 unused2[2];
+} __attribute__((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP	(1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32	/* part of the OHCI standard */
+struct ohci_hcca {
+	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+#if defined(CONFIG_MPC5200)
+	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u16	frame_no;		/* current frame number */
+#else
+	__u16	frame_no;		/* current frame number */
+	__u16	pad1;			/* set to 0 on each frame_no change */
+#endif
+	__u32	done_head;		/* info returned for an interrupt */
+	u8		reserved_for_hc[116];
+} __attribute__((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
+# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#endif
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+	/* control and status registers */
+	__u32	revision;
+	__u32	control;
+	__u32	cmdstatus;
+	__u32	intrstatus;
+	__u32	intrenable;
+	__u32	intrdisable;
+	/* memory pointers */
+	__u32	hcca;
+	__u32	ed_periodcurrent;
+	__u32	ed_controlhead;
+	__u32	ed_controlcurrent;
+	__u32	ed_bulkhead;
+	__u32	ed_bulkcurrent;
+	__u32	donehead;
+	/* frame counters */
+	__u32	fminterval;
+	__u32	fmremaining;
+	__u32	fmnumber;
+	__u32	periodicstart;
+	__u32	lsthresh;
+	/* Root hub ports */
+	struct	ohci_roothub_regs {
+		__u32	a;
+		__u32	b;
+		__u32	status;
+		__u32	portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
+	} roothub;
+} __attribute__((aligned(32)));
+
+/* Some EHCI controls */
+#define EHCI_USBCMD_OFF		0x20
+#define EHCI_USBCMD_HCRESET	(1 << 1)
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
+#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
+#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
+#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
+#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
+#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
+#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
+#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
+#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+#	define OHCI_USB_RESET	(0 << 6)
+#	define OHCI_USB_RESUME	(1 << 6)
+#	define OHCI_USB_OPER	(2 << 6)
+#	define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR	(1 << 0)	/* host controller reset */
+#define OHCI_CLF	(1 << 1)	/* control list filled */
+#define OHCI_BLF	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR	(1 << 3)	/* ownership change request */
+#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
+#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
+#define OHCI_INTR_SF	(1 << 2)	/* start frame */
+#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
+#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
+#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
+#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
+#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
+#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+	int devnum; /* Address of Root Hub endpoint */
+	void *dev;  /* was urb */
+	void *int_addr;
+	int send;
+	int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE		   0x01
+#define RH_ENDPOINT		   0x02
+#define RH_OTHER		   0x03
+
+#define RH_CLASS		   0x20
+#define RH_VENDOR		   0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS		0x0080
+#define RH_CLEAR_FEATURE	0x0100
+#define RH_SET_FEATURE		0x0300
+#define RH_SET_ADDRESS		0x0500
+#define RH_GET_DESCRIPTOR	0x0680
+#define RH_SET_DESCRIPTOR	0x0700
+#define RH_GET_CONFIGURATION	0x0880
+#define RH_SET_CONFIGURATION	0x0900
+#define RH_GET_STATE		0x0280
+#define RH_GET_INTERFACE	0x0A80
+#define RH_SET_INTERFACE	0x0B00
+#define RH_SYNC_FRAME		0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP		0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION	   0x00
+#define RH_PORT_ENABLE		   0x01
+#define RH_PORT_SUSPEND		   0x02
+#define RH_PORT_OVER_CURRENT	   0x03
+#define RH_PORT_RESET		   0x04
+#define RH_PORT_POWER		   0x08
+#define RH_PORT_LOW_SPEED	   0x09
+
+#define RH_C_PORT_CONNECTION	   0x10
+#define RH_C_PORT_ENABLE	   0x11
+#define RH_C_PORT_SUSPEND	   0x12
+#define RH_C_PORT_OVER_CURRENT	   0x13
+#define RH_C_PORT_RESET		   0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER	   0x00
+#define RH_C_HUB_OVER_CURRENT	   0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP	   0x00
+#define RH_ENDPOINT_STALL	   0x01
+
+#define RH_ACK			   0x01
+#define RH_REQ_ERR		   -1
+#define RH_NACK			   0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS	     0x00000001		/* current connect status */
+#define RH_PS_PES	     0x00000002		/* port enable status*/
+#define RH_PS_PSS	     0x00000004		/* port suspend status */
+#define RH_PS_POCI	     0x00000008		/* port over current indicator */
+#define RH_PS_PRS	     0x00000010		/* port reset status */
+#define RH_PS_PPS	     0x00000100		/* port power status */
+#define RH_PS_LSDA	     0x00000200		/* low speed device attached */
+#define RH_PS_CSC	     0x00010000		/* connect status change */
+#define RH_PS_PESC	     0x00020000		/* port enable status change */
+#define RH_PS_PSSC	     0x00040000		/* port suspend status change */
+#define RH_PS_OCIC	     0x00080000		/* over current indicator change */
+#define RH_PS_PRSC	     0x00100000		/* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS	     0x00000001		/* local power status */
+#define RH_HS_OCI	     0x00000002		/* over current indicator */
+#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
+#define RH_HS_LPSC	     0x00010000		/* local power status change */
+#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
+#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR		0x0000ffff		/* device removable flags */
+#define RH_B_PPCM	0xffff0000		/* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP	(0xff << 0)		/* number of downstream ports */
+#define RH_A_PSM	(1 << 8)		/* power switching mode */
+#define RH_A_NPS	(1 << 9)		/* no power switching */
+#define RH_A_DT		(1 << 10)		/* device type (mbz) */
+#define RH_A_OCPM	(1 << 11)		/* over current protection mode */
+#define RH_A_NOCP	(1 << 12)		/* no over current protection */
+#define RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+	ed_t *ed;
+	__u16 length;	/* number of tds associated with this request */
+	__u16 td_cnt;	/* number of tds already serviced */
+	struct usb_device *dev;
+	int   state;
+	unsigned long pipe;
+	void *transfer_buffer;
+	int transfer_buffer_length;
+	int interval;
+	int actual_length;
+	int finished;
+	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+	ed_t	ed[NUM_EDS];
+	int ed_cnt;
+};
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+typedef struct ohci {
+	long handle;              /* PCI BIOS */
+	int big_endian;           /* PCI BIOS */
+	struct ohci_hcca *hcca_unaligned;
+	struct ohci_hcca *hcca;		/* hcca */
+	td_t *td_unaligned;
+	struct ohci_device *ohci_dev_unaligned;
+	/* this allocates EDs for all possible endpoints */
+	struct ohci_device *ohci_dev;
+	/*dma_addr_t hcca_dma;*/
+
+	int irq;
+	int disabled;			/* e.g. got a UE, we're hung */
+	int sleeping;
+	unsigned long flags;		/* for HC bugs */
+
+	unsigned long dma_offset;
+	struct ohci_regs *regs; /* OHCI controller's memory */
+
+	int ohci_int_load[32];	 /* load of the 32 Interrupt Chains (for load balancing)*/
+	ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
+	ed_t *ed_controltail;	 /* last endpoint of control list */
+	int intrstatus;
+	__u32 hc_control;		/* copy of the hc control reg */
+	struct usb_device *dev[32];
+	struct virt_root_hub rh;
+
+	const char	*slot_name;
+} ohci_t;
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
+		int interval, int load);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *td_alloc(struct usb_device *usb_dev)
+{
+	int i;
+	struct td	*td;
+	td = NULL;
+	for(i = 0; i < NUM_TD; i++)
+	{
+		if(ptd[i].usb_dev == NULL)
+		{
+			td = &ptd[i];
+			td->usb_dev = usb_dev;
+			break;
+		}
+	}
+	return td;
+}
+
+static inline void ed_free(struct ed *ed)
+{
+	ed->usb_dev = NULL;
+}
+
diff --git a/usb/store/host/ohci-pci/pci_ids.h b/usb/store/host/ohci-pci/pci_ids.h
new file mode 100644
index 0000000..29ea2de
--- /dev/null
+++ b/usb/store/host/ohci-pci/pci_ids.h
@@ -0,0 +1,2613 @@
+/*
+ *	PCI Class, Vendor and Device IDs
+ *
+ *	Please keep sorted.
+ */
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED		0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
+
+#define PCI_BASE_CLASS_STORAGE		0x01
+#define PCI_CLASS_STORAGE_SCSI		0x0100
+#define PCI_CLASS_STORAGE_IDE		0x0101
+#define PCI_CLASS_STORAGE_FLOPPY	0x0102
+#define PCI_CLASS_STORAGE_IPI		0x0103
+#define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_OTHER		0x0180
+
+#define PCI_BASE_CLASS_NETWORK		0x02
+#define PCI_CLASS_NETWORK_ETHERNET	0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
+#define PCI_CLASS_NETWORK_FDDI		0x0202
+#define PCI_CLASS_NETWORK_ATM		0x0203
+#define PCI_CLASS_NETWORK_OTHER		0x0280
+
+#define PCI_BASE_CLASS_DISPLAY		0x03
+#define PCI_CLASS_DISPLAY_VGA		0x0300
+#define PCI_CLASS_DISPLAY_XGA		0x0301
+#define PCI_CLASS_DISPLAY_3D		0x0302
+#define PCI_CLASS_DISPLAY_OTHER		0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA	0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
+
+#define PCI_BASE_CLASS_MEMORY		0x05
+#define PCI_CLASS_MEMORY_RAM		0x0500
+#define PCI_CLASS_MEMORY_FLASH		0x0501
+#define PCI_CLASS_MEMORY_OTHER		0x0580
+
+#define PCI_BASE_CLASS_BRIDGE		0x06
+#define PCI_CLASS_BRIDGE_HOST		0x0600
+#define PCI_CLASS_BRIDGE_ISA		0x0601
+#define PCI_CLASS_BRIDGE_EISA		0x0602
+#define PCI_CLASS_BRIDGE_MC		0x0603
+#define PCI_CLASS_BRIDGE_PCI		0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
+#define PCI_CLASS_BRIDGE_NUBUS		0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
+#define PCI_CLASS_BRIDGE_OTHER		0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION	0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
+
+#define PCI_BASE_CLASS_SYSTEM		0x08
+#define PCI_CLASS_SYSTEM_PIC		0x0800
+#define PCI_CLASS_SYSTEM_DMA		0x0801
+#define PCI_CLASS_SYSTEM_TIMER		0x0802
+#define PCI_CLASS_SYSTEM_RTC		0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
+#define PCI_CLASS_SYSTEM_OTHER		0x0880
+
+#define PCI_BASE_CLASS_INPUT		0x09
+#define PCI_CLASS_INPUT_KEYBOARD	0x0900
+#define PCI_CLASS_INPUT_PEN		0x0901
+#define PCI_CLASS_INPUT_MOUSE		0x0902
+#define PCI_CLASS_INPUT_SCANNER		0x0903
+#define PCI_CLASS_INPUT_GAMEPORT	0x0904
+#define PCI_CLASS_INPUT_OTHER		0x0980
+
+#define PCI_BASE_CLASS_DOCKING		0x0a
+#define PCI_CLASS_DOCKING_GENERIC	0x0a00
+#define PCI_CLASS_DOCKING_OTHER		0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR	0x0b
+#define PCI_CLASS_PROCESSOR_386		0x0b00
+#define PCI_CLASS_PROCESSOR_486		0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
+#define PCI_CLASS_PROCESSOR_CO		0x0b40
+
+#define PCI_BASE_CLASS_SERIAL		0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
+#define PCI_CLASS_SERIAL_ACCESS		0x0c01
+#define PCI_CLASS_SERIAL_SSA		0x0c02
+#define PCI_CLASS_SERIAL_USB		0x0c03
+/* added code to find different types of USB controllers */
+#define PCI_CLASS_SERIAL_USB_UHCI   0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI   0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI   0x0c0320
+#define PCI_CLASS_SERIAL_FIBER		0x0c04
+#define PCI_CLASS_SERIAL_SMBUS		0x0c05
+
+#define PCI_BASE_CLASS_INTELLIGENT	0x0e
+#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
+
+#define PCI_BASE_CLASS_SATELLITE	0x0f
+#define PCI_CLASS_SATELLITE_TV		0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
+#define PCI_CLASS_SATELLITE_VOICE	0x0f03
+#define PCI_CLASS_SATELLITE_DATA	0x0f04
+
+#define PCI_BASE_CLASS_CRYPT		0x10
+#define PCI_CLASS_CRYPT_NETWORK		0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
+#define PCI_CLASS_CRYPT_OTHER		0x1080
+
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define PCI_CLASS_SP_DPIO		0x1100
+#define PCI_CLASS_SP_OTHER		0x1180
+
+#define PCI_CLASS_OTHERS		0xff
+
+/* Vendors and devices.  Sort key: vendor first, device next. */
+
+#define PCI_VENDOR_ID_DYNALINK		0x0675
+#define PCI_DEVICE_ID_DYNALINK_IS64PH	0x1702
+
+#define PCI_VENDOR_ID_BERKOM			0x0871
+#define PCI_DEVICE_ID_BERKOM_A1T		0xffa1
+#define PCI_DEVICE_ID_BERKOM_T_CONCEPT		0xffa2
+#define PCI_DEVICE_ID_BERKOM_A4T		0xffa4
+#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO	0xffa8
+
+#define PCI_VENDOR_ID_COMPAQ		0x0e11
+#define PCI_DEVICE_ID_COMPAQ_TOKENRING	0x0508
+#define PCI_DEVICE_ID_COMPAQ_1280	0x3033
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX	0x4000
+#define PCI_DEVICE_ID_COMPAQ_6010	0x6010
+#define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
+#define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
+#define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
+#define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
+#define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
+#define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
+#define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
+#define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
+#define PCI_DEVICE_ID_COMPAQ_CISSC	0x46
+#define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
+
+#define PCI_VENDOR_ID_NCR		0x1000
+#define PCI_VENDOR_ID_LSI_LOGIC		0x1000
+#define PCI_DEVICE_ID_NCR_53C810	0x0001
+#define PCI_DEVICE_ID_NCR_53C820	0x0002
+#define PCI_DEVICE_ID_NCR_53C825	0x0003
+#define PCI_DEVICE_ID_NCR_53C815	0x0004
+#define PCI_DEVICE_ID_LSI_53C810AP	0x0005
+#define PCI_DEVICE_ID_NCR_53C860	0x0006
+#define PCI_DEVICE_ID_LSI_53C1510	0x000a
+#define PCI_DEVICE_ID_NCR_53C896	0x000b
+#define PCI_DEVICE_ID_NCR_53C895	0x000c
+#define PCI_DEVICE_ID_NCR_53C885	0x000d
+#define PCI_DEVICE_ID_NCR_53C875	0x000f
+#define PCI_DEVICE_ID_NCR_53C1510	0x0010
+#define PCI_DEVICE_ID_LSI_53C895A	0x0012
+#define PCI_DEVICE_ID_LSI_53C875A	0x0013
+#define PCI_DEVICE_ID_LSI_53C1010_33	0x0020
+#define PCI_DEVICE_ID_LSI_53C1010_66	0x0021
+#define PCI_DEVICE_ID_LSI_53C1030	0x0030
+#define PCI_DEVICE_ID_LSI_1030_53C1035	0x0032
+#define PCI_DEVICE_ID_LSI_53C1035	0x0040
+#define PCI_DEVICE_ID_NCR_53C875J	0x008f
+#define PCI_DEVICE_ID_LSI_FC909		0x0621
+#define PCI_DEVICE_ID_LSI_FC929		0x0622
+#define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
+#define PCI_DEVICE_ID_LSI_FC919		0x0624
+#define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
+#define PCI_DEVICE_ID_LSI_FC929X	0x0626
+#define PCI_DEVICE_ID_LSI_FC939X	0x0642
+#define PCI_DEVICE_ID_LSI_FC949X	0x0640
+#define PCI_DEVICE_ID_LSI_FC919X	0x0628
+#define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
+#define PCI_DEVICE_ID_LSI_61C102	0x0901
+#define PCI_DEVICE_ID_LSI_63C815	0x1000
+#define PCI_DEVICE_ID_LSI_SAS1064	0x0050
+#define PCI_DEVICE_ID_LSI_SAS1066	0x005E
+#define PCI_DEVICE_ID_LSI_SAS1068	0x0054
+#define PCI_DEVICE_ID_LSI_SAS1064A	0x005C
+#define PCI_DEVICE_ID_LSI_SAS1064E	0x0056
+#define PCI_DEVICE_ID_LSI_SAS1066E	0x005A
+#define PCI_DEVICE_ID_LSI_SAS1068E	0x0058
+#define PCI_DEVICE_ID_LSI_SAS1078	0x0060
+
+#define PCI_VENDOR_ID_ATI		0x1002
+/* Mach64 */
+#define PCI_DEVICE_ID_ATI_68800		0x4158
+#define PCI_DEVICE_ID_ATI_215CT222	0x4354
+#define PCI_DEVICE_ID_ATI_210888CX	0x4358
+#define PCI_DEVICE_ID_ATI_215ET222	0x4554
+/* Mach64 / Rage */
+#define PCI_DEVICE_ID_ATI_215GB		0x4742
+#define PCI_DEVICE_ID_ATI_215GD		0x4744
+#define PCI_DEVICE_ID_ATI_215GI		0x4749
+#define PCI_DEVICE_ID_ATI_215GP		0x4750
+#define PCI_DEVICE_ID_ATI_215GQ		0x4751
+#define PCI_DEVICE_ID_ATI_215XL		0x4752
+#define PCI_DEVICE_ID_ATI_215GT		0x4754
+#define PCI_DEVICE_ID_ATI_215GTB	0x4755
+#define PCI_DEVICE_ID_ATI_215_IV	0x4756
+#define PCI_DEVICE_ID_ATI_215_IW	0x4757
+#define PCI_DEVICE_ID_ATI_215_IZ	0x475A
+#define PCI_DEVICE_ID_ATI_210888GX	0x4758
+#define PCI_DEVICE_ID_ATI_215_LB	0x4c42
+#define PCI_DEVICE_ID_ATI_215_LD	0x4c44
+#define PCI_DEVICE_ID_ATI_215_LG	0x4c47
+#define PCI_DEVICE_ID_ATI_215_LI	0x4c49
+#define PCI_DEVICE_ID_ATI_215_LM	0x4c4D
+#define PCI_DEVICE_ID_ATI_215_LN	0x4c4E
+#define PCI_DEVICE_ID_ATI_215_LR	0x4c52
+#define PCI_DEVICE_ID_ATI_215_LS	0x4c53
+#define PCI_DEVICE_ID_ATI_264_LT	0x4c54
+/* Mach64 VT */
+#define PCI_DEVICE_ID_ATI_264VT		0x5654
+#define PCI_DEVICE_ID_ATI_264VU		0x5655
+#define PCI_DEVICE_ID_ATI_264VV		0x5656
+/* Rage128 GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_RE	0x5245
+#define PCI_DEVICE_ID_ATI_RAGE128_RF	0x5246
+#define PCI_DEVICE_ID_ATI_RAGE128_RG	0x5247
+/* Rage128 VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_RK	0x524b
+#define PCI_DEVICE_ID_ATI_RAGE128_RL	0x524c
+#define PCI_DEVICE_ID_ATI_RAGE128_SE	0x5345
+#define PCI_DEVICE_ID_ATI_RAGE128_SF	0x5346
+#define PCI_DEVICE_ID_ATI_RAGE128_SG	0x5347
+#define PCI_DEVICE_ID_ATI_RAGE128_SH	0x5348
+#define PCI_DEVICE_ID_ATI_RAGE128_SK	0x534b
+#define PCI_DEVICE_ID_ATI_RAGE128_SL	0x534c
+#define PCI_DEVICE_ID_ATI_RAGE128_SM	0x534d
+#define PCI_DEVICE_ID_ATI_RAGE128_SN	0x534e
+/* Rage128 Ultra */
+#define PCI_DEVICE_ID_ATI_RAGE128_TF	0x5446
+#define PCI_DEVICE_ID_ATI_RAGE128_TL	0x544c
+#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
+#define PCI_DEVICE_ID_ATI_RAGE128_TS	0x5453
+#define PCI_DEVICE_ID_ATI_RAGE128_TT	0x5454
+#define PCI_DEVICE_ID_ATI_RAGE128_TU	0x5455
+/* Rage128 M3 */
+#define PCI_DEVICE_ID_ATI_RAGE128_LE	0x4c45
+#define PCI_DEVICE_ID_ATI_RAGE128_LF	0x4c46
+/* Rage128 M4 */
+#define PCI_DEVICE_ID_ATI_RAGE128_MF    0x4d46
+#define PCI_DEVICE_ID_ATI_RAGE128_ML    0x4d4c
+/* Rage128 Pro GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_PA	0x5041
+#define PCI_DEVICE_ID_ATI_RAGE128_PB	0x5042
+#define PCI_DEVICE_ID_ATI_RAGE128_PC	0x5043
+#define PCI_DEVICE_ID_ATI_RAGE128_PD	0x5044
+#define PCI_DEVICE_ID_ATI_RAGE128_PE	0x5045
+#define PCI_DEVICE_ID_ATI_RAGE128_PF	0x5046
+/* Rage128 Pro VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_PG	0x5047
+#define PCI_DEVICE_ID_ATI_RAGE128_PH	0x5048
+#define PCI_DEVICE_ID_ATI_RAGE128_PI	0x5049
+#define PCI_DEVICE_ID_ATI_RAGE128_PJ	0x504A
+#define PCI_DEVICE_ID_ATI_RAGE128_PK	0x504B
+#define PCI_DEVICE_ID_ATI_RAGE128_PL	0x504C
+#define PCI_DEVICE_ID_ATI_RAGE128_PM	0x504D
+#define PCI_DEVICE_ID_ATI_RAGE128_PN	0x504E
+#define PCI_DEVICE_ID_ATI_RAGE128_PO	0x504F
+#define PCI_DEVICE_ID_ATI_RAGE128_PP	0x5050
+#define PCI_DEVICE_ID_ATI_RAGE128_PQ	0x5051
+#define PCI_DEVICE_ID_ATI_RAGE128_PR	0x5052
+#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
+#define PCI_DEVICE_ID_ATI_RAGE128_PS	0x5053
+#define PCI_DEVICE_ID_ATI_RAGE128_PT	0x5054
+#define PCI_DEVICE_ID_ATI_RAGE128_PU	0x5055
+#define PCI_DEVICE_ID_ATI_RAGE128_PV	0x5056
+#define PCI_DEVICE_ID_ATI_RAGE128_PW	0x5057
+#define PCI_DEVICE_ID_ATI_RAGE128_PX	0x5058
+/* Rage128 M4 */
+#define PCI_DEVICE_ID_ATI_RADEON_LE	0x4d45
+#define PCI_DEVICE_ID_ATI_RADEON_LF	0x4d46
+/* Radeon R100 */
+#define PCI_DEVICE_ID_ATI_RADEON_QD	0x5144
+#define PCI_DEVICE_ID_ATI_RADEON_QE	0x5145
+#define PCI_DEVICE_ID_ATI_RADEON_QF	0x5146
+#define PCI_DEVICE_ID_ATI_RADEON_QG	0x5147
+/* Radeon RV100 (VE) */
+#define PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
+#define PCI_DEVICE_ID_ATI_RADEON_QZ	0x515a
+/* Radeon R200 (8500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QL	0x514c
+#define PCI_DEVICE_ID_ATI_RADEON_QN	0x514e
+#define PCI_DEVICE_ID_ATI_RADEON_QO	0x514f
+#define PCI_DEVICE_ID_ATI_RADEON_Ql	0x516c
+#define PCI_DEVICE_ID_ATI_RADEON_BB	0x4242
+/* Radeon R200 (9100) */
+#define PCI_DEVICE_ID_ATI_RADEON_QM	0x514d
+/* Radeon RV200 (7500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QW	0x5157
+#define PCI_DEVICE_ID_ATI_RADEON_QX	0x5158
+/* Radeon NV-100 */
+#define PCI_DEVICE_ID_ATI_RADEON_N1	0x5159
+#define PCI_DEVICE_ID_ATI_RADEON_N2	0x515a
+/* Radeon RV250 (9000) */
+#define PCI_DEVICE_ID_ATI_RADEON_Id	0x4964
+#define PCI_DEVICE_ID_ATI_RADEON_Ie	0x4965
+#define PCI_DEVICE_ID_ATI_RADEON_If	0x4966
+#define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
+/* Radeon RV280 (9200) */
+#define PCI_DEVICE_ID_ATI_RADEON_Y_	0x5960
+#define PCI_DEVICE_ID_ATI_RADEON_Ya	0x5961
+#define PCI_DEVICE_ID_ATI_RADEON_Yd	0x5964
+/* Radeon R300 (9500) */
+#define PCI_DEVICE_ID_ATI_RADEON_AD	0x4144
+/* Radeon R300 (9700) */
+#define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
+#define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
+#define PCI_DEVICE_ID_ATI_RADEON_NF	0x4e46
+#define PCI_DEVICE_ID_ATI_RADEON_NG	0x4e47
+#define PCI_DEVICE_ID_ATI_RADEON_AE	0x4145
+#define PCI_DEVICE_ID_ATI_RADEON_AF	0x4146
+/* Radeon R350 (9800) */
+#define PCI_DEVICE_ID_ATI_RADEON_NH	0x4e48
+#define PCI_DEVICE_ID_ATI_RADEON_NI	0x4e49
+/* Radeon RV350 (9600) */
+#define PCI_DEVICE_ID_ATI_RADEON_AP	0x4150
+#define PCI_DEVICE_ID_ATI_RADEON_AR	0x4152
+/* Radeon M6 */
+#define PCI_DEVICE_ID_ATI_RADEON_LY	0x4c59
+#define PCI_DEVICE_ID_ATI_RADEON_LZ	0x4c5a
+/* Radeon M7 */
+#define PCI_DEVICE_ID_ATI_RADEON_LW	0x4c57
+#define PCI_DEVICE_ID_ATI_RADEON_LX	0x4c58
+/* Radeon M9 */
+#define PCI_DEVICE_ID_ATI_RADEON_Ld	0x4c64
+#define PCI_DEVICE_ID_ATI_RADEON_Le	0x4c65
+#define PCI_DEVICE_ID_ATI_RADEON_Lf	0x4c66
+#define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
+/* Radeon */
+#define PCI_DEVICE_ID_ATI_RADEON_RA	0x5144
+#define PCI_DEVICE_ID_ATI_RADEON_RB	0x5145
+#define PCI_DEVICE_ID_ATI_RADEON_RC	0x5146
+#define PCI_DEVICE_ID_ATI_RADEON_RD	0x5147
+/* RadeonIGP */
+#define PCI_DEVICE_ID_ATI_RS100		0xcab0
+#define PCI_DEVICE_ID_ATI_RS200		0xcab2
+#define PCI_DEVICE_ID_ATI_RS200_B	0xcbb2
+#define PCI_DEVICE_ID_ATI_RS250		0xcab3
+#define PCI_DEVICE_ID_ATI_RS300_100	0x5830
+#define PCI_DEVICE_ID_ATI_RS300_133	0x5831
+#define PCI_DEVICE_ID_ATI_RS300_166	0x5832
+#define PCI_DEVICE_ID_ATI_RS300_200	0x5833
+#define PCI_DEVICE_ID_ATI_RS350_100     0x7830
+#define PCI_DEVICE_ID_ATI_RS350_133     0x7831
+#define PCI_DEVICE_ID_ATI_RS350_166     0x7832
+#define PCI_DEVICE_ID_ATI_RS350_200     0x7833
+#define PCI_DEVICE_ID_ATI_RS400_100     0x5a30
+#define PCI_DEVICE_ID_ATI_RS400_133     0x5a31
+#define PCI_DEVICE_ID_ATI_RS400_166     0x5a32
+#define PCI_DEVICE_ID_ATI_RS400_200     0x5a33
+#define PCI_DEVICE_ID_ATI_RS480         0x5950
+/* ATI IXP Chipset */
+#define PCI_DEVICE_ID_ATI_IXP200_IDE	0x4349
+#define PCI_DEVICE_ID_ATI_IXP300_IDE	0x4369
+#define PCI_DEVICE_ID_ATI_IXP300_SATA   0x436e
+#define PCI_DEVICE_ID_ATI_IXP400_IDE	0x4376
+#define PCI_DEVICE_ID_ATI_IXP400_SATA   0x4379
+
+#define PCI_VENDOR_ID_VLSI		0x1004
+#define PCI_DEVICE_ID_VLSI_82C592	0x0005
+#define PCI_DEVICE_ID_VLSI_82C593	0x0006
+#define PCI_DEVICE_ID_VLSI_82C594	0x0007
+#define PCI_DEVICE_ID_VLSI_82C597	0x0009
+#define PCI_DEVICE_ID_VLSI_82C541	0x000c
+#define PCI_DEVICE_ID_VLSI_82C543	0x000d
+#define PCI_DEVICE_ID_VLSI_82C532	0x0101
+#define PCI_DEVICE_ID_VLSI_82C534	0x0102
+#define PCI_DEVICE_ID_VLSI_82C535	0x0104
+#define PCI_DEVICE_ID_VLSI_82C147	0x0105
+#define PCI_DEVICE_ID_VLSI_VAS96011	0x0702
+
+#define PCI_VENDOR_ID_ADL		0x1005
+#define PCI_DEVICE_ID_ADL_2301		0x2301
+
+#define PCI_VENDOR_ID_NS		0x100b
+#define PCI_DEVICE_ID_NS_87415		0x0002
+#define PCI_DEVICE_ID_NS_87560_LIO	0x000e
+#define PCI_DEVICE_ID_NS_87560_USB	0x0012
+#define PCI_DEVICE_ID_NS_83815		0x0020
+#define PCI_DEVICE_ID_NS_83820		0x0022
+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE	0x0500
+#define PCI_DEVICE_ID_NS_SCx200_SMI	0x0501
+#define PCI_DEVICE_ID_NS_SCx200_IDE	0x0502
+#define PCI_DEVICE_ID_NS_SCx200_AUDIO	0x0503
+#define PCI_DEVICE_ID_NS_SCx200_VIDEO	0x0504
+#define PCI_DEVICE_ID_NS_SCx200_XBUS	0x0505
+#define PCI_DEVICE_ID_NS_SC1100_BRIDGE	0x0510
+#define PCI_DEVICE_ID_NS_SC1100_SMI	0x0511
+#define PCI_DEVICE_ID_NS_SC1100_XBUS	0x0515
+#define PCI_DEVICE_ID_NS_87410		0xd001
+
+#define PCI_VENDOR_ID_TSENG		0x100c
+#define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
+#define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
+#define PCI_DEVICE_ID_TSENG_W32P_c	0x3206
+#define PCI_DEVICE_ID_TSENG_W32P_d	0x3207
+#define PCI_DEVICE_ID_TSENG_ET6000	0x3208
+
+#define PCI_VENDOR_ID_WEITEK		0x100e
+#define PCI_DEVICE_ID_WEITEK_P9000	0x9001
+#define PCI_DEVICE_ID_WEITEK_P9100	0x9100
+
+#define PCI_VENDOR_ID_DEC		0x1011
+#define PCI_DEVICE_ID_DEC_BRD		0x0001
+#define PCI_DEVICE_ID_DEC_TULIP		0x0002
+#define PCI_DEVICE_ID_DEC_TGA		0x0004
+#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
+#define PCI_DEVICE_ID_DEC_TGA2		0x000D
+#define PCI_DEVICE_ID_DEC_FDDI		0x000F
+#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
+#define PCI_DEVICE_ID_DEC_21142		0x0019
+#define PCI_DEVICE_ID_DEC_21052		0x0021
+#define PCI_DEVICE_ID_DEC_21150		0x0022
+#define PCI_DEVICE_ID_DEC_21152		0x0024
+#define PCI_DEVICE_ID_DEC_21153		0x0025
+#define PCI_DEVICE_ID_DEC_21154		0x0026
+#define PCI_DEVICE_ID_DEC_21285		0x1065
+#define PCI_DEVICE_ID_COMPAQ_42XX	0x0046
+
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#define PCI_DEVICE_ID_CIRRUS_7548	0x0038
+#define PCI_DEVICE_ID_CIRRUS_5430	0x00a0
+#define PCI_DEVICE_ID_CIRRUS_5434_4	0x00a4
+#define PCI_DEVICE_ID_CIRRUS_5434_8	0x00a8
+#define PCI_DEVICE_ID_CIRRUS_5436	0x00ac
+#define PCI_DEVICE_ID_CIRRUS_5446	0x00b8
+#define PCI_DEVICE_ID_CIRRUS_5480	0x00bc
+#define PCI_DEVICE_ID_CIRRUS_5462	0x00d0
+#define PCI_DEVICE_ID_CIRRUS_5464	0x00d4
+#define PCI_DEVICE_ID_CIRRUS_5465	0x00d6
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#define PCI_DEVICE_ID_CIRRUS_7542	0x1200
+#define PCI_DEVICE_ID_CIRRUS_7543	0x1202
+#define PCI_DEVICE_ID_CIRRUS_7541	0x1204
+
+#define PCI_VENDOR_ID_IBM		0x1014
+#define PCI_DEVICE_ID_IBM_FIRE_CORAL	0x000a
+#define PCI_DEVICE_ID_IBM_TR		0x0018
+#define PCI_DEVICE_ID_IBM_82G2675	0x001d
+#define PCI_DEVICE_ID_IBM_MCA		0x0020
+#define PCI_DEVICE_ID_IBM_82351		0x0022
+#define PCI_DEVICE_ID_IBM_PYTHON	0x002d
+#define PCI_DEVICE_ID_IBM_SERVERAID	0x002e
+#define PCI_DEVICE_ID_IBM_TR_WAKE	0x003e
+#define PCI_DEVICE_ID_IBM_MPIC		0x0046
+#define PCI_DEVICE_ID_IBM_3780IDSP	0x007d
+#define PCI_DEVICE_ID_IBM_CHUKAR	0x0096
+#define PCI_DEVICE_ID_IBM_CPC710_PCI64	0x00fc
+#define PCI_DEVICE_ID_IBM_CPC710_PCI32	0x0105
+#define	PCI_DEVICE_ID_IBM_405GP		0x0156
+#define PCI_DEVICE_ID_IBM_SNIPE		0x0180
+#define PCI_DEVICE_ID_IBM_SERVERAIDI960	0x01bd
+#define PCI_DEVICE_ID_IBM_CITRINE		0x028C
+#define PCI_DEVICE_ID_IBM_GEMSTONE		0xB166
+#define PCI_DEVICE_ID_IBM_MPIC_2	0xffff
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1	0x0031
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2	0x0219
+#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX		0x021A
+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM	0x0251
+#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL	0x252
+
+#define PCI_VENDOR_ID_COMPEX2		0x101a // pci.ids says "AT&T GIS (NCR)"
+#define PCI_DEVICE_ID_COMPEX2_100VG	0x0005
+
+#define PCI_VENDOR_ID_WD		0x101c
+#define PCI_DEVICE_ID_WD_7197		0x3296
+#define PCI_DEVICE_ID_WD_90C		0xc24a
+
+#define PCI_VENDOR_ID_AMI		0x101e
+#define PCI_DEVICE_ID_AMI_MEGARAID3	0x1960
+#define PCI_DEVICE_ID_AMI_MEGARAID	0x9010
+#define PCI_DEVICE_ID_AMI_MEGARAID2	0x9060
+
+#define PCI_VENDOR_ID_AMD		0x1022
+#define PCI_DEVICE_ID_AMD_LANCE		0x2000
+#define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
+#define PCI_DEVICE_ID_AMD_SCSI		0x2020
+#define PCI_DEVICE_ID_AMD_SERENADE	0x36c0
+#define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
+#define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
+#define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
+#define PCI_DEVICE_ID_AMD_FE_GATE_700D	0x700D
+#define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
+#define PCI_DEVICE_ID_AMD_FE_GATE_700F	0x700F
+#define PCI_DEVICE_ID_AMD_COBRA_7400	0x7400
+#define PCI_DEVICE_ID_AMD_COBRA_7401	0x7401
+#define PCI_DEVICE_ID_AMD_COBRA_7403	0x7403
+#define PCI_DEVICE_ID_AMD_COBRA_7404	0x7404
+#define PCI_DEVICE_ID_AMD_VIPER_7408	0x7408
+#define PCI_DEVICE_ID_AMD_VIPER_7409	0x7409
+#define PCI_DEVICE_ID_AMD_VIPER_740B	0x740B
+#define PCI_DEVICE_ID_AMD_VIPER_740C	0x740C
+#define PCI_DEVICE_ID_AMD_VIPER_7410	0x7410
+#define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
+#define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
+#define PCI_DEVICE_ID_AMD_VIPER_7414	0x7414
+#define PCI_DEVICE_ID_AMD_OPUS_7440	0x7440
+#	define PCI_DEVICE_ID_AMD_VIPER_7440	PCI_DEVICE_ID_AMD_OPUS_7440
+#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
+#	define PCI_DEVICE_ID_AMD_VIPER_7441	PCI_DEVICE_ID_AMD_OPUS_7441
+#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
+#	define PCI_DEVICE_ID_AMD_VIPER_7443	PCI_DEVICE_ID_AMD_OPUS_7443
+#define PCI_DEVICE_ID_AMD_OPUS_7445	0x7445
+#define PCI_DEVICE_ID_AMD_OPUS_7448	0x7448
+# define	PCI_DEVICE_ID_AMD_VIPER_7448	PCI_DEVICE_ID_AMD_OPUS_7448
+#define PCI_DEVICE_ID_AMD_OPUS_7449	0x7449
+#	define PCI_DEVICE_ID_AMD_VIPER_7449	PCI_DEVICE_ID_AMD_OPUS_7449
+#define PCI_DEVICE_ID_AMD_8111_LAN	0x7462
+#define PCI_DEVICE_ID_AMD_8111_LPC	0x7468
+#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
+#define PCI_DEVICE_ID_AMD_8111_SMBUS2	0x746a
+#define PCI_DEVICE_ID_AMD_8111_SMBUS	0x746b
+#define PCI_DEVICE_ID_AMD_8111_AUDIO	0x746d
+#define PCI_DEVICE_ID_AMD_8151_0	0x7454
+#define PCI_DEVICE_ID_AMD_8131_APIC     0x7450
+
+#define PCI_VENDOR_ID_TRIDENT		0x1023
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
+#define PCI_DEVICE_ID_TRIDENT_9320	0x9320
+#define PCI_DEVICE_ID_TRIDENT_9388	0x9388
+#define PCI_DEVICE_ID_TRIDENT_9397	0x9397
+#define PCI_DEVICE_ID_TRIDENT_939A	0x939A
+#define PCI_DEVICE_ID_TRIDENT_9520	0x9520
+#define PCI_DEVICE_ID_TRIDENT_9525	0x9525
+#define PCI_DEVICE_ID_TRIDENT_9420	0x9420
+#define PCI_DEVICE_ID_TRIDENT_9440	0x9440
+#define PCI_DEVICE_ID_TRIDENT_9660	0x9660
+#define PCI_DEVICE_ID_TRIDENT_9750	0x9750
+#define PCI_DEVICE_ID_TRIDENT_9850	0x9850
+#define PCI_DEVICE_ID_TRIDENT_9880	0x9880
+#define PCI_DEVICE_ID_TRIDENT_8400	0x8400
+#define PCI_DEVICE_ID_TRIDENT_8420	0x8420
+#define PCI_DEVICE_ID_TRIDENT_8500	0x8500
+
+#define PCI_VENDOR_ID_AI		0x1025
+#define PCI_DEVICE_ID_AI_M1435		0x1435
+
+#define PCI_VENDOR_ID_DELL		0x1028
+#define PCI_DEVICE_ID_DELL_RACIII	0x0008
+#define PCI_DEVICE_ID_DELL_RAC4		0x0012
+
+#define PCI_VENDOR_ID_MATROX		0x102B
+#define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
+#define PCI_DEVICE_ID_MATROX_MIL	0x0519
+#define PCI_DEVICE_ID_MATROX_MYS	0x051A
+#define PCI_DEVICE_ID_MATROX_MIL_2	0x051b
+#define PCI_DEVICE_ID_MATROX_MIL_2_AGP	0x051f
+#define PCI_DEVICE_ID_MATROX_MGA_IMP	0x0d10
+#define PCI_DEVICE_ID_MATROX_G100_MM	0x1000
+#define PCI_DEVICE_ID_MATROX_G100_AGP	0x1001
+#define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
+#define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
+#define	PCI_DEVICE_ID_MATROX_G400	0x0525
+#define PCI_DEVICE_ID_MATROX_G550	0x2527
+#define PCI_DEVICE_ID_MATROX_VIA	0x4536
+
+#define PCI_VENDOR_ID_CT		0x102c
+#define PCI_DEVICE_ID_CT_69000		0x00c0
+#define PCI_DEVICE_ID_CT_65545		0x00d8
+#define PCI_DEVICE_ID_CT_65548		0x00dc
+#define PCI_DEVICE_ID_CT_65550		0x00e0
+#define PCI_DEVICE_ID_CT_65554		0x00e4
+#define PCI_DEVICE_ID_CT_65555		0x00e5
+
+#define PCI_VENDOR_ID_MIRO		0x1031
+#define PCI_DEVICE_ID_MIRO_36050	0x5601
+#define PCI_DEVICE_ID_MIRO_DC10PLUS	0x7efe
+#define PCI_DEVICE_ID_MIRO_DC30PLUS	0xd801
+
+#define PCI_VENDOR_ID_NEC		0x1033
+#define PCI_DEVICE_ID_NEC_CBUS_1	0x0001 /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_LOCAL		0x0002 /* Local Bridge */
+#define PCI_DEVICE_ID_NEC_ATM		0x0003 /* ATM LAN Controller */
+#define PCI_DEVICE_ID_NEC_R4000		0x0004 /* R4000 Bridge */
+#define PCI_DEVICE_ID_NEC_486		0x0005 /* 486 Like Peripheral Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_1	0x0006 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_UXBUS		0x0007 /* UX-Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_2	0x0008 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_GRAPH		0x0009 /* PCI-CoreGraph Bridge */
+#define PCI_DEVICE_ID_NEC_VL		0x0016 /* PCI-VL Bridge */
+#define PCI_DEVICE_ID_NEC_STARALPHA2	0x002c /* STAR ALPHA2 */
+#define PCI_DEVICE_ID_NEC_CBUS_2	0x002d /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_USB		0x0035 /* PCI-USB Host */
+#define PCI_DEVICE_ID_NEC_CBUS_3	0x003b
+#define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
+#define PCI_DEVICE_ID_NEC_PCX2		0x0046 /* PowerVR */
+#define PCI_DEVICE_ID_NEC_NILE4		0x005a
+#define PCI_DEVICE_ID_NEC_VRC5476       0x009b
+#define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
+#define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
+#define PCI_DEVICE_ID_NEC_PC9821CS01    0x800c /* PC-9821-CS01 */
+#define PCI_DEVICE_ID_NEC_PC9821NRB06   0x800d /* PC-9821NR-B06 */
+
+#define PCI_VENDOR_ID_FD		0x1036
+#define PCI_DEVICE_ID_FD_36C70		0x0000
+
+#define PCI_VENDOR_ID_SI		0x1039
+#define PCI_DEVICE_ID_SI_5591_AGP	0x0001
+#define PCI_DEVICE_ID_SI_6202		0x0002
+#define PCI_DEVICE_ID_SI_503		0x0008
+#define PCI_DEVICE_ID_SI_ACPI		0x0009
+#define PCI_DEVICE_ID_SI_SMBUS		0x0016
+#define PCI_DEVICE_ID_SI_LPC		0x0018
+#define PCI_DEVICE_ID_SI_5597_VGA	0x0200
+#define PCI_DEVICE_ID_SI_6205		0x0205
+#define PCI_DEVICE_ID_SI_501		0x0406
+#define PCI_DEVICE_ID_SI_496		0x0496
+#define PCI_DEVICE_ID_SI_300		0x0300
+#define PCI_DEVICE_ID_SI_315H		0x0310
+#define PCI_DEVICE_ID_SI_315		0x0315
+#define PCI_DEVICE_ID_SI_315PRO		0x0325
+#define PCI_DEVICE_ID_SI_530		0x0530
+#define PCI_DEVICE_ID_SI_540		0x0540
+#define PCI_DEVICE_ID_SI_550		0x0550
+#define PCI_DEVICE_ID_SI_540_VGA	0x5300
+#define PCI_DEVICE_ID_SI_550_VGA	0x5315
+#define PCI_DEVICE_ID_SI_601		0x0601
+#define PCI_DEVICE_ID_SI_620		0x0620
+#define PCI_DEVICE_ID_SI_630		0x0630
+#define PCI_DEVICE_ID_SI_633		0x0633
+#define PCI_DEVICE_ID_SI_635		0x0635
+#define PCI_DEVICE_ID_SI_640		0x0640
+#define PCI_DEVICE_ID_SI_645		0x0645
+#define PCI_DEVICE_ID_SI_646		0x0646
+#define PCI_DEVICE_ID_SI_648		0x0648
+#define PCI_DEVICE_ID_SI_650		0x0650
+#define PCI_DEVICE_ID_SI_651		0x0651
+#define PCI_DEVICE_ID_SI_652		0x0652
+#define PCI_DEVICE_ID_SI_655		0x0655
+#define PCI_DEVICE_ID_SI_661		0x0661
+#define PCI_DEVICE_ID_SI_730		0x0730
+#define PCI_DEVICE_ID_SI_733		0x0733
+#define PCI_DEVICE_ID_SI_630_VGA	0x6300
+#define PCI_DEVICE_ID_SI_730_VGA	0x7300
+#define PCI_DEVICE_ID_SI_735		0x0735
+#define PCI_DEVICE_ID_SI_740		0x0740
+#define PCI_DEVICE_ID_SI_741		0x0741
+#define PCI_DEVICE_ID_SI_745		0x0745
+#define PCI_DEVICE_ID_SI_746		0x0746
+#define PCI_DEVICE_ID_SI_748		0x0748
+#define PCI_DEVICE_ID_SI_750		0x0750
+#define PCI_DEVICE_ID_SI_751		0x0751
+#define PCI_DEVICE_ID_SI_752		0x0752
+#define PCI_DEVICE_ID_SI_755		0x0755
+#define PCI_DEVICE_ID_SI_760		0x0760
+#define PCI_DEVICE_ID_SI_900		0x0900
+#define PCI_DEVICE_ID_SI_961		0x0961
+#define PCI_DEVICE_ID_SI_962		0x0962
+#define PCI_DEVICE_ID_SI_963		0x0963
+#define PCI_DEVICE_ID_SI_5107		0x5107
+#define PCI_DEVICE_ID_SI_5300		0x5300
+#define PCI_DEVICE_ID_SI_5511		0x5511
+#define PCI_DEVICE_ID_SI_5513		0x5513
+#define PCI_DEVICE_ID_SI_5518		0x5518
+#define PCI_DEVICE_ID_SI_5571		0x5571
+#define PCI_DEVICE_ID_SI_5581		0x5581
+#define PCI_DEVICE_ID_SI_5582		0x5582
+#define PCI_DEVICE_ID_SI_5591		0x5591
+#define PCI_DEVICE_ID_SI_5596		0x5596
+#define PCI_DEVICE_ID_SI_5597		0x5597
+#define PCI_DEVICE_ID_SI_5598		0x5598
+#define PCI_DEVICE_ID_SI_5600		0x5600
+#define PCI_DEVICE_ID_SI_6300		0x6300
+#define PCI_DEVICE_ID_SI_6306		0x6306
+#define PCI_DEVICE_ID_SI_6326		0x6326
+#define PCI_DEVICE_ID_SI_7001		0x7001
+#define PCI_DEVICE_ID_SI_7012		0x7012
+#define PCI_DEVICE_ID_SI_7016		0x7016
+
+#define PCI_VENDOR_ID_HP		0x103c
+#define PCI_DEVICE_ID_HP_VISUALIZE_EG	0x1005
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX6	0x1006
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX4	0x1008
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX2	0x100a
+#define PCI_DEVICE_ID_HP_TACHYON	0x1028
+#define PCI_DEVICE_ID_HP_TACHLITE	0x1029
+#define PCI_DEVICE_ID_HP_J2585A		0x1030
+#define PCI_DEVICE_ID_HP_J2585B		0x1031
+#define PCI_DEVICE_ID_HP_J2973A		0x1040
+#define PCI_DEVICE_ID_HP_J2970A		0x1042
+#define PCI_DEVICE_ID_HP_DIVA		0x1048
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA1	0x1049
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA2	0x104A
+#define PCI_DEVICE_ID_HP_DIVA_MAESTRO	0x104B
+#define PCI_DEVICE_ID_HP_PCI_LBA	0x1054
+#define PCI_DEVICE_ID_HP_REO_SBA	0x10f0
+#define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
+#define PCI_DEVICE_ID_HP_VISUALIZE_FXE	0x108b
+#define PCI_DEVICE_ID_HP_DIVA_HALFDOME	0x1223
+#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE	0x1226
+#define PCI_DEVICE_ID_HP_DIVA_POWERBAR	0x1227
+#define PCI_DEVICE_ID_HP_ZX1_SBA	0x1229
+#define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
+#define PCI_DEVICE_ID_HP_PCIX_LBA	0x122e
+#define PCI_DEVICE_ID_HP_SX1000_IOC	0x127c
+#define PCI_DEVICE_ID_HP_DIVA_EVEREST	0x1282
+#define PCI_DEVICE_ID_HP_DIVA_AUX	0x1290
+#define PCI_DEVICE_ID_HP_DIVA_RMP3	0x1301
+#define PCI_DEVICE_ID_HP_CISSA		0x3220
+#define PCI_DEVICE_ID_HP_CISSB		0x3230
+#define PCI_DEVICE_ID_HP_ZX2_IOC	0x4031
+
+#define PCI_VENDOR_ID_PCTECH		0x1042
+#define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
+#define PCI_DEVICE_ID_PCTECH_RZ1001	0x1001
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_0	0x3000
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_1	0x3010
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
+
+#define PCI_VENDOR_ID_ASUSTEK		0x1043
+#define PCI_DEVICE_ID_ASUSTEK_0675	0x0675
+
+#define PCI_VENDOR_ID_DPT		0x1044
+#define PCI_DEVICE_ID_DPT		0xa400
+
+#define PCI_VENDOR_ID_OPTI		0x1045
+#define PCI_DEVICE_ID_OPTI_92C178	0xc178
+#define PCI_DEVICE_ID_OPTI_82C557	0xc557
+#define PCI_DEVICE_ID_OPTI_82C558	0xc558
+#define PCI_DEVICE_ID_OPTI_82C621	0xc621
+#define PCI_DEVICE_ID_OPTI_82C700	0xc700
+#define PCI_DEVICE_ID_OPTI_82C701	0xc701
+#define PCI_DEVICE_ID_OPTI_82C814	0xc814
+#define PCI_DEVICE_ID_OPTI_82C822	0xc822
+#define PCI_DEVICE_ID_OPTI_82C861	0xc861
+#define PCI_DEVICE_ID_OPTI_82C825	0xd568
+
+#define PCI_VENDOR_ID_ELSA		0x1048
+#define PCI_DEVICE_ID_ELSA_MICROLINK	0x1000
+#define PCI_DEVICE_ID_ELSA_QS3000	0x3000
+
+#define PCI_VENDOR_ID_SGS		0x104a
+#define PCI_DEVICE_ID_SGS_2000		0x0008
+#define PCI_DEVICE_ID_SGS_1764		0x0009
+
+#define PCI_VENDOR_ID_BUSLOGIC		      0x104B
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
+
+#define PCI_VENDOR_ID_TI		0x104c
+#define PCI_DEVICE_ID_TI_TVP4010	0x3d04
+#define PCI_DEVICE_ID_TI_TVP4020	0x3d07
+#define PCI_DEVICE_ID_TI_4450		0x8011
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#define PCI_DEVICE_ID_TI_1250		0xac16
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#define PCI_DEVICE_ID_TI_4510		0xac44
+#define PCI_DEVICE_ID_TI_4520		0xac46
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#define PCI_DEVICE_ID_TI_1451A		0xac52
+#define PCI_DEVICE_ID_TI_1620		0xac54
+#define PCI_DEVICE_ID_TI_1520		0xac55
+#define PCI_DEVICE_ID_TI_1510		0xac56
+
+#define PCI_VENDOR_ID_SONY		0x104d
+#define PCI_DEVICE_ID_SONY_CXD3222	0x8039
+
+#define PCI_VENDOR_ID_OAK		0x104e
+#define PCI_DEVICE_ID_OAK_OTI107	0x0107
+
+/* Winbond have two vendor IDs! See 0x10ad as well */
+#define PCI_VENDOR_ID_WINBOND2		0x1050
+#define PCI_DEVICE_ID_WINBOND2_89C940	0x0940
+#define PCI_DEVICE_ID_WINBOND2_89C940F	0x5a5a
+#define PCI_DEVICE_ID_WINBOND2_6692	0x6692
+
+#define PCI_VENDOR_ID_ANIGMA		0x1051
+#define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
+  
+#define PCI_VENDOR_ID_EFAR		0x1055
+#define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
+#define PCI_DEVICE_ID_EFAR_SLC90E66_0	0x9460
+#define PCI_DEVICE_ID_EFAR_SLC90E66_2	0x9462
+#define PCI_DEVICE_ID_EFAR_SLC90E66_3	0x9463
+
+#define PCI_VENDOR_ID_MOTOROLA		0x1057
+#define PCI_VENDOR_ID_MOTOROLA_OOPS	0x1507
+#define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
+#define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
+#define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
+#define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
+#define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
+#define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
+#define PCI_DEVICE_ID_MOTOROLA_CPX8216	0x4806
+#define PCI_DEVICE_ID_MOTOROLA_HARRIER	0x480b
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200	0x5803
+
+#define PCI_VENDOR_ID_PROMISE		0x105a
+#define PCI_DEVICE_ID_PROMISE_20265	0x0d30
+#define PCI_DEVICE_ID_PROMISE_20267	0x4d30
+#define PCI_DEVICE_ID_PROMISE_20246	0x4d33
+#define PCI_DEVICE_ID_PROMISE_20262	0x4d38
+#define PCI_DEVICE_ID_PROMISE_20263	0x0D38
+#define PCI_DEVICE_ID_PROMISE_20268	0x4d68
+#define PCI_DEVICE_ID_PROMISE_20268R	0x6268
+#define PCI_DEVICE_ID_PROMISE_20269	0x4d69
+#define PCI_DEVICE_ID_PROMISE_20270	0x6268
+#define PCI_DEVICE_ID_PROMISE_20271	0x6269
+#define PCI_DEVICE_ID_PROMISE_20275	0x1275
+#define PCI_DEVICE_ID_PROMISE_20276	0x5275
+#define PCI_DEVICE_ID_PROMISE_20277	0x7275
+#define PCI_DEVICE_ID_PROMISE_5300	0x5300
+
+#define PCI_VENDOR_ID_N9		0x105d
+#define PCI_DEVICE_ID_N9_I128		0x2309
+#define PCI_DEVICE_ID_N9_I128_2		0x2339
+#define PCI_DEVICE_ID_N9_I128_T2R	0x493d
+
+#define PCI_VENDOR_ID_UMC		0x1060
+#define PCI_DEVICE_ID_UMC_UM8673F	0x0101
+#define PCI_DEVICE_ID_UMC_UM8891A	0x0891
+#define PCI_DEVICE_ID_UMC_UM8886BF	0x673a
+#define PCI_DEVICE_ID_UMC_UM8886A	0x886a
+#define PCI_DEVICE_ID_UMC_UM8881F	0x8881
+#define PCI_DEVICE_ID_UMC_UM8886F	0x8886
+#define PCI_DEVICE_ID_UMC_UM9017F	0x9017
+#define PCI_DEVICE_ID_UMC_UM8886N	0xe886
+#define PCI_DEVICE_ID_UMC_UM8891N	0xe891
+
+#define PCI_VENDOR_ID_X			0x1061
+#define PCI_DEVICE_ID_X_AGX016		0x0001
+
+#define PCI_VENDOR_ID_MYLEX		0x1069
+#define PCI_DEVICE_ID_MYLEX_DAC960_P	0x0001
+#define PCI_DEVICE_ID_MYLEX_DAC960_PD	0x0002
+#define PCI_DEVICE_ID_MYLEX_DAC960_PG	0x0010
+#define PCI_DEVICE_ID_MYLEX_DAC960_LA	0x0020
+#define PCI_DEVICE_ID_MYLEX_DAC960_LP	0x0050
+#define PCI_DEVICE_ID_MYLEX_DAC960_BA	0xBA56
+#define PCI_DEVICE_ID_MYLEX_DAC960_GEM	0xB166
+
+#define PCI_VENDOR_ID_PICOP		0x1066
+#define PCI_DEVICE_ID_PICOP_PT86C52X	0x0001
+#define PCI_DEVICE_ID_PICOP_PT80C524	0x8002
+
+#define PCI_VENDOR_ID_APPLE		0x106b
+#define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
+#define PCI_DEVICE_ID_APPLE_GC		0x0002
+#define PCI_DEVICE_ID_APPLE_HYDRA	0x000e
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW	0x0018
+#define PCI_DEVICE_ID_APPLE_KL_USB	0x0019
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP	0x0020
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC	0x0021
+#define PCI_DEVICE_ID_APPLE_KEYLARGO	0x0022
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP	0x0024
+#define PCI_DEVICE_ID_APPLE_KEYLARGO_P	0x0025
+#define PCI_DEVICE_ID_APPLE_KL_USB_P	0x0026
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P	0x0027
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15	0x002d
+#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15	0x002e
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW2	0x0030
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2	0x0032
+#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA	0x0033
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2	0x0034
+#define PCI_DEVICE_ID_APPLE_IPID_ATA100	0x003b
+#define PCI_DEVICE_ID_APPLE_KEYLARGO_I	0x003e
+#define PCI_DEVICE_ID_APPLE_K2_ATA100	0x0043
+#define PCI_DEVICE_ID_APPLE_U3_AGP	0x004b
+#define PCI_DEVICE_ID_APPLE_K2_GMAC	0x004c
+#define PCI_DEVICE_ID_APPLE_SH_ATA      0x0050
+#define PCI_DEVICE_ID_APPLE_SH_SUNGEM   0x0051
+#define PCI_DEVICE_ID_APPLE_SH_FW       0x0052
+#define PCI_DEVICE_ID_APPLE_U3L_AGP	0x0058
+#define PCI_DEVICE_ID_APPLE_U3H_AGP	0x0059
+#define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
+
+#define PCI_VENDOR_ID_YAMAHA		0x1073
+#define PCI_DEVICE_ID_YAMAHA_724	0x0004
+#define PCI_DEVICE_ID_YAMAHA_724F	0x000d
+#define PCI_DEVICE_ID_YAMAHA_740	0x000a
+#define PCI_DEVICE_ID_YAMAHA_740C	0x000c
+#define PCI_DEVICE_ID_YAMAHA_744	0x0010
+#define PCI_DEVICE_ID_YAMAHA_754	0x0012
+
+#define PCI_VENDOR_ID_NEXGEN		0x1074
+#define PCI_DEVICE_ID_NEXGEN_82C501	0x4e78
+
+#define PCI_VENDOR_ID_QLOGIC		0x1077
+#define PCI_DEVICE_ID_QLOGIC_ISP1020	0x1020
+#define PCI_DEVICE_ID_QLOGIC_ISP1022	0x1022
+#define PCI_DEVICE_ID_QLOGIC_ISP2100	0x2100
+#define PCI_DEVICE_ID_QLOGIC_ISP2200	0x2200
+
+#define PCI_VENDOR_ID_CYRIX		0x1078
+#define PCI_DEVICE_ID_CYRIX_5510	0x0000
+#define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
+#define PCI_DEVICE_ID_CYRIX_5520	0x0002
+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY	0x0100
+#define PCI_DEVICE_ID_CYRIX_5530_SMI	0x0101
+#define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
+#define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
+#define PCI_DEVICE_ID_CYRIX_5530_VIDEO	0x0104
+
+#define PCI_VENDOR_ID_LEADTEK		0x107d
+#define PCI_DEVICE_ID_LEADTEK_805	0x0000
+
+#define PCI_VENDOR_ID_INTERPHASE	0x107e
+#define PCI_DEVICE_ID_INTERPHASE_5526	0x0004
+#define PCI_DEVICE_ID_INTERPHASE_55x6	0x0005
+#define PCI_DEVICE_ID_INTERPHASE_5575	0x0008
+
+#define PCI_VENDOR_ID_CONTAQ		0x1080
+#define PCI_DEVICE_ID_CONTAQ_82C599	0x0600
+#define PCI_DEVICE_ID_CONTAQ_82C693	0xc693
+
+#define PCI_VENDOR_ID_FOREX		0x1083
+
+#define PCI_VENDOR_ID_OLICOM		0x108d
+#define PCI_DEVICE_ID_OLICOM_OC3136	0x0001
+#define PCI_DEVICE_ID_OLICOM_OC2315	0x0011
+#define PCI_DEVICE_ID_OLICOM_OC2325	0x0012
+#define PCI_DEVICE_ID_OLICOM_OC2183	0x0013
+#define PCI_DEVICE_ID_OLICOM_OC2326	0x0014
+#define PCI_DEVICE_ID_OLICOM_OC6151	0x0021
+
+#define PCI_VENDOR_ID_SUN		0x108e
+#define PCI_DEVICE_ID_SUN_EBUS		0x1000
+#define PCI_DEVICE_ID_SUN_HAPPYMEAL	0x1001
+#define PCI_DEVICE_ID_SUN_RIO_EBUS	0x1100
+#define PCI_DEVICE_ID_SUN_RIO_GEM	0x1101
+#define PCI_DEVICE_ID_SUN_RIO_1394	0x1102
+#define PCI_DEVICE_ID_SUN_RIO_USB	0x1103
+#define PCI_DEVICE_ID_SUN_GEM		0x2bad
+#define PCI_DEVICE_ID_SUN_SIMBA		0x5000
+#define PCI_DEVICE_ID_SUN_PBM		0x8000
+#define PCI_DEVICE_ID_SUN_SCHIZO	0x8001
+#define PCI_DEVICE_ID_SUN_SABRE		0xa000
+#define PCI_DEVICE_ID_SUN_HUMMINGBIRD	0xa001
+#define PCI_DEVICE_ID_SUN_TOMATILLO	0xa801
+
+#define PCI_VENDOR_ID_CMD		0x1095
+#define PCI_DEVICE_ID_CMD_640		0x0640
+#define PCI_DEVICE_ID_CMD_643		0x0643
+#define PCI_DEVICE_ID_CMD_646		0x0646
+#define PCI_DEVICE_ID_CMD_647		0x0647
+#define PCI_DEVICE_ID_CMD_648		0x0648
+#define PCI_DEVICE_ID_CMD_649		0x0649
+#define PCI_DEVICE_ID_CMD_670		0x0670
+#define PCI_DEVICE_ID_CMD_680		0x0680
+
+#define PCI_DEVICE_ID_SII_680		0x0680
+#define PCI_DEVICE_ID_SII_3112		0x3112
+#define PCI_DEVICE_ID_SII_1210SA	0x0240
+
+#define PCI_VENDOR_ID_VISION		0x1098
+#define PCI_DEVICE_ID_VISION_QD8500	0x0001
+#define PCI_DEVICE_ID_VISION_QD8580	0x0002
+
+#define PCI_VENDOR_ID_BROOKTREE		0x109e
+#define PCI_DEVICE_ID_BROOKTREE_848	0x0350
+#define PCI_DEVICE_ID_BROOKTREE_849A	0x0351
+#define PCI_DEVICE_ID_BROOKTREE_878_1	0x036e
+#define PCI_DEVICE_ID_BROOKTREE_878	0x0878
+#define PCI_DEVICE_ID_BROOKTREE_8474	0x8474
+
+#define PCI_VENDOR_ID_SIERRA		0x10a8
+#define PCI_DEVICE_ID_SIERRA_STB	0x0000
+
+#define PCI_VENDOR_ID_SGI		0x10a9
+#define PCI_DEVICE_ID_SGI_IOC3		0x0003
+#define PCI_DEVICE_ID_SGI_IOC4		0x100a
+#define PCI_VENDOR_ID_SGI_LITHIUM	0x1002
+
+#define PCI_VENDOR_ID_ACC		0x10aa
+#define PCI_DEVICE_ID_ACC_2056		0x0000
+
+#define PCI_VENDOR_ID_WINBOND		0x10ad
+#define PCI_DEVICE_ID_WINBOND_83769	0x0001
+#define PCI_DEVICE_ID_WINBOND_82C105	0x0105
+#define PCI_DEVICE_ID_WINBOND_83C553	0x0565
+
+#define PCI_VENDOR_ID_DATABOOK		0x10b3
+#define PCI_DEVICE_ID_DATABOOK_87144	0xb106
+
+#define PCI_VENDOR_ID_PLX		0x10b5
+#define PCI_DEVICE_ID_PLX_R685		0x1030
+#define PCI_DEVICE_ID_PLX_ROMULUS	0x106a
+#define PCI_DEVICE_ID_PLX_SPCOM800	0x1076
+#define PCI_DEVICE_ID_PLX_1077		0x1077
+#define PCI_DEVICE_ID_PLX_SPCOM200	0x1103
+#define PCI_DEVICE_ID_PLX_DJINN_ITOO	0x1151
+#define PCI_DEVICE_ID_PLX_R753		0x1152
+#define PCI_DEVICE_ID_PLX_9030		0x9030
+#define PCI_DEVICE_ID_PLX_9050		0x9050
+#define PCI_DEVICE_ID_PLX_9060		0x9060
+#define PCI_DEVICE_ID_PLX_9060ES	0x906E
+#define PCI_DEVICE_ID_PLX_9060SD	0x906D
+#define PCI_DEVICE_ID_PLX_9080		0x9080
+#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2	0xa001
+
+#define PCI_VENDOR_ID_MADGE		0x10b6
+#define PCI_DEVICE_ID_MADGE_MK2		0x0002
+#define PCI_DEVICE_ID_MADGE_C155S	0x1001
+
+#define PCI_VENDOR_ID_3COM		0x10b7
+#define PCI_DEVICE_ID_3COM_3C985	0x0001
+#define PCI_DEVICE_ID_3COM_3C940	0x1700
+#define PCI_DEVICE_ID_3COM_3C339	0x3390
+#define PCI_DEVICE_ID_3COM_3C359	0x3590
+#define PCI_DEVICE_ID_3COM_3C590	0x5900
+#define PCI_DEVICE_ID_3COM_3C595TX	0x5950
+#define PCI_DEVICE_ID_3COM_3C595T4	0x5951
+#define PCI_DEVICE_ID_3COM_3C595MII	0x5952
+#define PCI_DEVICE_ID_3COM_3C940B	0x80eb
+#define PCI_DEVICE_ID_3COM_3C900TPO	0x9000
+#define PCI_DEVICE_ID_3COM_3C900COMBO	0x9001
+#define PCI_DEVICE_ID_3COM_3C905TX	0x9050
+#define PCI_DEVICE_ID_3COM_3C905T4	0x9051
+#define PCI_DEVICE_ID_3COM_3C905B_TX	0x9055
+#define PCI_DEVICE_ID_3COM_3CR990	0x9900
+#define PCI_DEVICE_ID_3COM_3CR990_TX_95	0x9902
+#define PCI_DEVICE_ID_3COM_3CR990_TX_97	0x9903
+#define PCI_DEVICE_ID_3COM_3CR990B	0x9904
+#define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
+#define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
+#define PCI_DEVICE_ID_3COM_3CR990SVR97	0x9909
+#define PCI_DEVICE_ID_3COM_3CR990SVR	0x990a
+
+#define PCI_VENDOR_ID_SMC		0x10b8
+#define PCI_DEVICE_ID_SMC_EPIC100	0x0005
+
+#define PCI_VENDOR_ID_AL		0x10b9
+#define PCI_DEVICE_ID_AL_M1445		0x1445
+#define PCI_DEVICE_ID_AL_M1449		0x1449
+#define PCI_DEVICE_ID_AL_M1451		0x1451
+#define PCI_DEVICE_ID_AL_M1461		0x1461
+#define PCI_DEVICE_ID_AL_M1489		0x1489
+#define PCI_DEVICE_ID_AL_M1511		0x1511
+#define PCI_DEVICE_ID_AL_M1513		0x1513
+#define PCI_DEVICE_ID_AL_M1521		0x1521
+#define PCI_DEVICE_ID_AL_M1523		0x1523
+#define PCI_DEVICE_ID_AL_M1531		0x1531
+#define PCI_DEVICE_ID_AL_M1533		0x1533
+#define PCI_DEVICE_ID_AL_M1535 		0x1535
+#define PCI_DEVICE_ID_AL_M1541		0x1541
+#define PCI_DEVICE_ID_AL_M1543		0x1543
+#define PCI_DEVICE_ID_AL_M1563		0x1563
+#define PCI_DEVICE_ID_AL_M1621		0x1621
+#define PCI_DEVICE_ID_AL_M1631		0x1631
+#define PCI_DEVICE_ID_AL_M1632		0x1632
+#define PCI_DEVICE_ID_AL_M1641		0x1641
+#define PCI_DEVICE_ID_AL_M1644		0x1644
+#define PCI_DEVICE_ID_AL_M1647		0x1647
+#define PCI_DEVICE_ID_AL_M1651		0x1651
+#define PCI_DEVICE_ID_AL_M1671		0x1671
+#define PCI_DEVICE_ID_AL_M1681		0x1681
+#define PCI_DEVICE_ID_AL_M1683		0x1683
+#define PCI_DEVICE_ID_AL_M1689		0x1689
+#define PCI_DEVICE_ID_AL_M3307		0x3307
+#define PCI_DEVICE_ID_AL_M4803		0x5215
+#define PCI_DEVICE_ID_AL_M5219		0x5219
+#define PCI_DEVICE_ID_AL_M5228		0x5228
+#define PCI_DEVICE_ID_AL_M5229		0x5229
+#define PCI_DEVICE_ID_AL_M5237		0x5237
+#define PCI_DEVICE_ID_AL_M5243		0x5243
+#define PCI_DEVICE_ID_AL_M5451		0x5451
+#define PCI_DEVICE_ID_AL_M7101		0x7101
+
+#define PCI_VENDOR_ID_MITSUBISHI	0x10ba
+
+#define PCI_VENDOR_ID_SURECOM		0x10bd
+#define PCI_DEVICE_ID_SURECOM_NE34	0x0e34
+
+#define PCI_VENDOR_ID_NEOMAGIC		0x10c8
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV       0x0005
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS   0x0083
+
+#define PCI_VENDOR_ID_ASP		0x10cd
+#define PCI_DEVICE_ID_ASP_ABP940	0x1200
+#define PCI_DEVICE_ID_ASP_ABP940U	0x1300
+#define PCI_DEVICE_ID_ASP_ABP940UW	0x2300
+
+#define PCI_VENDOR_ID_MACRONIX		0x10d9
+#define PCI_DEVICE_ID_MACRONIX_MX98713	0x0512
+#define PCI_DEVICE_ID_MACRONIX_MX987x5	0x0531
+
+#define PCI_VENDOR_ID_TCONRAD		0x10da
+#define PCI_DEVICE_ID_TCONRAD_TOKENRING	0x0508
+
+#define PCI_VENDOR_ID_CERN		0x10dc
+#define PCI_DEVICE_ID_CERN_SPSB_PMC	0x0001
+#define PCI_DEVICE_ID_CERN_SPSB_PCI	0x0002
+#define PCI_DEVICE_ID_CERN_HIPPI_DST	0x0021
+#define PCI_DEVICE_ID_CERN_HIPPI_SRC	0x0022
+
+#define PCI_VENDOR_ID_NVIDIA			0x10de
+#define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
+#define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028
+#define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
+#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN        0x002a
+#define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
+#define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE	0x0035
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA	0x0036
+#define PCI_DEVICE_ID_NVIDIA_NVENET_10		0x0037
+#define PCI_DEVICE_ID_NVIDIA_NVENET_11		0x0038
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2	0x003e
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800       0x0041
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE    0x0042
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT    0x0045
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000     0x004E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS	0x0052
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE	0x0053
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA	0x0054
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2	0x0055
+#define PCI_DEVICE_ID_NVIDIA_NVENET_8		0x0056
+#define PCI_DEVICE_ID_NVIDIA_NVENET_9		0x0057
+#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO	0x0059
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS	0x0064
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
+#define PCI_DEVICE_ID_NVIDIA_NVENET_2		0x0066
+#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO		0x006a
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS	0x0084
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
+#define PCI_DEVICE_ID_NVIDIA_NVENET_4		0x0086
+#define PCI_DEVICE_ID_NVIDIA_NVENET_5		0x008c
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA	0x008e
+#define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
+#define PCI_DEVICE_ID_GEFORCE_6800A             0x00c1
+#define PCI_DEVICE_ID_GEFORCE_6800A_LE          0x00c2
+#define PCI_DEVICE_ID_GEFORCE_GO_6800           0x00c8
+#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA     0x00c9
+#define PCI_DEVICE_ID_QUADRO_FX_GO1400          0x00cc
+#define PCI_DEVICE_ID_QUADRO_FX_1400            0x00ce
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO		0x00da
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS	0x00d4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE	0x00d5
+#define PCI_DEVICE_ID_NVIDIA_NVENET_3		0x00d6
+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO		0x00da
+#define PCI_DEVICE_ID_NVIDIA_NVENET_7		0x00df
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA	0x00e3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS	0x00e4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE	0x00e5
+#define PCI_DEVICE_ID_NVIDIA_NVENET_6		0x00e6
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2	0x00ee
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
+#define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX	0x0110
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2	0x0111
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO	0x0112
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR	0x0113
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT	0x0140
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600	0x0141
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL	0x0145
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540	0x014E
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200	0x014F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS	0x0150
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2	0x0151
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200    0x0164
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250    0x0166
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1  0x0167
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1  0x0168
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460	0x0170
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440	0x0171
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420	0x0172
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE	0x0173
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO	0x0174
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO	0x0175
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO    0x0177
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL	0x0178
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200	0x017A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL	0x017B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL	0x017C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO    0x0186
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO    0x0187
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL    0x0188
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC    0x0189
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS    0x018A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL    0x018B
+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
+#define PCI_DEVICE_ID_NVIDIA_NFORCE		0x01a4
+#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO		0x01b1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS	0x01b4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
+#define PCI_DEVICE_ID_NVIDIA_NVENET_1		0x01c3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2		0x01e0
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC		0x0203
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B      0x0211
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE   0x0212
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT   0x0215
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600	0x0250
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400	0x0251
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200	0x0253
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL	0x0258
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL	0x0259
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL	0x025B
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE	0x0265
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA	0x0266
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2	0x0267
+#define PCI_DEVICE_ID_NVIDIA_NVENET_12		0x0268
+#define PCI_DEVICE_ID_NVIDIA_NVENET_13		0x0269
+#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO	0x026B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800	0x0280
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO       0x0286
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL        0x0288
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL        0x0289
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL       0x028C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA  0x0301
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800        0x0302
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000         0x0308
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000         0x0309
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA  0x0311
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600        0x0312
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE      0x0314
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600      0x031A
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650      0x031B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700        0x031C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200        0x0320
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA  0x0321
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1      0x0322
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE      0x0323
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200      0x0324
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250      0x0325
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500        0x0326
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100        0x0327
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32   0x0328
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200	    0x0329
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI     0x032A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500          0x032B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300      0x032C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100      0x032D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA  0x0330
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900        0x0331
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT      0x0332
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA  0x0333
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT      0x0334
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000         0x0338
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700          0x033F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA  0x0341
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700        0x0342
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE      0x0343
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE      0x0344
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1    0x0347
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
+
+#define PCI_VENDOR_ID_IMS		0x10e0
+#define PCI_DEVICE_ID_IMS_8849		0x8849
+#define PCI_DEVICE_ID_IMS_TT128		0x9128
+#define PCI_DEVICE_ID_IMS_TT3D		0x9135
+
+#define PCI_VENDOR_ID_TEKRAM2		0x10e1
+#define PCI_DEVICE_ID_TEKRAM2_690c	0x690c
+
+#define PCI_VENDOR_ID_TUNDRA		0x10e3
+#define PCI_DEVICE_ID_TUNDRA_CA91C042	0x0000
+
+#define PCI_VENDOR_ID_AMCC		0x10e8
+#define PCI_DEVICE_ID_AMCC_MYRINET	0x8043
+#define PCI_DEVICE_ID_AMCC_PARASTATION	0x8062
+#define PCI_DEVICE_ID_AMCC_S5933	0x807d
+#define PCI_DEVICE_ID_AMCC_S5933_HEPC3	0x809c
+
+#define PCI_VENDOR_ID_INTERG		0x10ea
+#define PCI_DEVICE_ID_INTERG_1680	0x1680
+#define PCI_DEVICE_ID_INTERG_1682	0x1682
+#define PCI_DEVICE_ID_INTERG_2000	0x2000
+#define PCI_DEVICE_ID_INTERG_2010	0x2010
+#define PCI_DEVICE_ID_INTERG_5000	0x5000
+#define PCI_DEVICE_ID_INTERG_5050	0x5050
+
+#define PCI_VENDOR_ID_REALTEK		0x10ec
+#define PCI_DEVICE_ID_REALTEK_8029	0x8029
+#define PCI_DEVICE_ID_REALTEK_8129	0x8129
+#define PCI_DEVICE_ID_REALTEK_8139	0x8139
+#define PCI_DEVICE_ID_REALTEK_8169	0x8169
+
+#define PCI_VENDOR_ID_XILINX		0x10ee
+#define PCI_DEVICE_ID_TURBOPAM		0x4020
+
+#define PCI_VENDOR_ID_TRUEVISION	0x10fa
+#define PCI_DEVICE_ID_TRUEVISION_T1000	0x000c
+
+#define PCI_VENDOR_ID_INIT		0x1101
+#define PCI_DEVICE_ID_INIT_320P		0x9100
+#define PCI_DEVICE_ID_INIT_360P		0x9500
+
+#define PCI_VENDOR_ID_CREATIVE		0x1102 // duplicate: ECTIVA
+#define PCI_DEVICE_ID_CREATIVE_EMU10K1	0x0002
+
+#define PCI_VENDOR_ID_ECTIVA		0x1102 // duplicate: CREATIVE
+#define PCI_DEVICE_ID_ECTIVA_EV1938	0x8938
+
+#define PCI_VENDOR_ID_TTI		0x1103
+#define PCI_DEVICE_ID_TTI_HPT343	0x0003
+#define PCI_DEVICE_ID_TTI_HPT366	0x0004
+#define PCI_DEVICE_ID_TTI_HPT372	0x0005
+#define PCI_DEVICE_ID_TTI_HPT302	0x0006
+#define PCI_DEVICE_ID_TTI_HPT371	0x0007
+#define PCI_DEVICE_ID_TTI_HPT374	0x0008
+#define PCI_DEVICE_ID_TTI_HPT372N	0x0009	// apparently a 372N variant?
+
+#define PCI_VENDOR_ID_VIA		0x1106
+#define PCI_DEVICE_ID_VIA_8763_0	0x0198
+#define PCI_DEVICE_ID_VIA_8380_0	0x0204
+#define PCI_DEVICE_ID_VIA_3238_0	0x0238
+#define PCI_DEVICE_ID_VIA_PT880		0x0258
+#define PCI_DEVICE_ID_VIA_PX8X0_0	0x0259
+#define PCI_DEVICE_ID_VIA_3269_0	0x0269
+#define PCI_DEVICE_ID_VIA_K8T800PRO_0	0x0282
+#define PCI_DEVICE_ID_VIA_8363_0	0x0305
+#define PCI_DEVICE_ID_VIA_8371_0	0x0391
+#define PCI_DEVICE_ID_VIA_8501_0	0x0501
+#define PCI_DEVICE_ID_VIA_82C505	0x0505
+#define PCI_DEVICE_ID_VIA_82C561	0x0561
+#define PCI_DEVICE_ID_VIA_82C586_1	0x0571
+#define PCI_DEVICE_ID_VIA_82C576	0x0576
+#define PCI_DEVICE_ID_VIA_82C585	0x0585
+#define PCI_DEVICE_ID_VIA_82C586_0	0x0586
+#define PCI_DEVICE_ID_VIA_82C595	0x0595
+#define PCI_DEVICE_ID_VIA_82C596	0x0596
+#define PCI_DEVICE_ID_VIA_82C597_0	0x0597
+#define PCI_DEVICE_ID_VIA_82C598_0	0x0598
+#define PCI_DEVICE_ID_VIA_8601_0	0x0601
+#define PCI_DEVICE_ID_VIA_8605_0	0x0605
+#define PCI_DEVICE_ID_VIA_82C680	0x0680
+#define PCI_DEVICE_ID_VIA_82C686	0x0686
+#define PCI_DEVICE_ID_VIA_82C691_0	0x0691
+#define PCI_DEVICE_ID_VIA_82C693	0x0693
+#define PCI_DEVICE_ID_VIA_82C693_1	0x0698
+#define PCI_DEVICE_ID_VIA_82C926	0x0926
+#define PCI_DEVICE_ID_VIA_82C576_1	0x1571
+#define PCI_DEVICE_ID_VIA_82C595_97	0x1595
+#define PCI_DEVICE_ID_VIA_82C586_2	0x3038
+#define PCI_DEVICE_ID_VIA_82C586_3	0x3040
+#define PCI_DEVICE_ID_VIA_6305		0x3044
+#define PCI_DEVICE_ID_VIA_82C596_3	0x3050
+#define PCI_DEVICE_ID_VIA_82C596B_3	0x3051
+#define PCI_DEVICE_ID_VIA_82C686_4	0x3057
+#define PCI_DEVICE_ID_VIA_82C686_5	0x3058
+#define PCI_DEVICE_ID_VIA_8233_5	0x3059
+#define PCI_DEVICE_ID_VIA_8233_7	0x3065
+#define PCI_DEVICE_ID_VIA_82C686_6	0x3068
+#define PCI_DEVICE_ID_VIA_8233_0	0x3074
+#define PCI_DEVICE_ID_VIA_8633_0	0x3091
+#define PCI_DEVICE_ID_VIA_8367_0	0x3099
+#define PCI_DEVICE_ID_VIA_8653_0	0x3101
+#define PCI_DEVICE_ID_VIA_8622		0x3102
+#define PCI_DEVICE_ID_VIA_8233C_0	0x3109
+#define PCI_DEVICE_ID_VIA_8361		0x3112
+#define PCI_DEVICE_ID_VIA_XM266		0x3116
+#define PCI_DEVICE_ID_VIA_612X		0x3119
+#define PCI_DEVICE_ID_VIA_862X_0	0x3123
+#define PCI_DEVICE_ID_VIA_8753_0	0x3128
+#define PCI_DEVICE_ID_VIA_8233A		0x3147
+#define PCI_DEVICE_ID_VIA_8703_51_0	0x3148
+#define PCI_DEVICE_ID_VIA_8237_SATA	0x3149
+#define PCI_DEVICE_ID_VIA_XN266		0x3156
+#define PCI_DEVICE_ID_VIA_8754C_0	0x3168
+#define PCI_DEVICE_ID_VIA_8235		0x3177
+#define PCI_DEVICE_ID_VIA_P4N333	0x3178
+#define PCI_DEVICE_ID_VIA_8385_0	0x3188
+#define PCI_DEVICE_ID_VIA_8377_0	0x3189
+#define PCI_DEVICE_ID_VIA_8378_0	0x3205
+#define PCI_DEVICE_ID_VIA_8783_0	0x3208
+#define PCI_DEVICE_ID_VIA_P4M400	0x3209
+#define PCI_DEVICE_ID_VIA_8237		0x3227
+#define PCI_DEVICE_ID_VIA_3296_0	0x0296
+#define PCI_DEVICE_ID_VIA_86C100A	0x6100
+#define PCI_DEVICE_ID_VIA_8231		0x8231
+#define PCI_DEVICE_ID_VIA_8231_4	0x8235
+#define PCI_DEVICE_ID_VIA_8365_1	0x8305
+#define PCI_DEVICE_ID_VIA_8371_1	0x8391
+#define PCI_DEVICE_ID_VIA_8501_1	0x8501
+#define PCI_DEVICE_ID_VIA_82C597_1	0x8597
+#define PCI_DEVICE_ID_VIA_82C598_1	0x8598
+#define PCI_DEVICE_ID_VIA_8601_1	0x8601
+#define PCI_DEVICE_ID_VIA_8505_1	0x8605
+#define PCI_DEVICE_ID_VIA_8633_1	0xB091
+#define PCI_DEVICE_ID_VIA_8367_1	0xB099
+#define PCI_DEVICE_ID_VIA_P4X266_1	0xB101
+#define PCI_DEVICE_ID_VIA_8615_1	0xB103
+#define PCI_DEVICE_ID_VIA_8361_1	0xB112
+#define PCI_DEVICE_ID_VIA_8235_1	0xB168
+#define PCI_DEVICE_ID_VIA_838X_1	0xB188
+#define PCI_DEVICE_ID_VIA_83_87XX_1	0xB198
+
+#define PCI_VENDOR_ID_SIEMENS           0x110A
+#define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
+
+#define PCI_VENDOR_ID_SMC2		0x1113
+#define PCI_DEVICE_ID_SMC2_1211TX	0x1211
+
+#define PCI_VENDOR_ID_VORTEX		0x1119
+#define PCI_DEVICE_ID_VORTEX_GDT60x0	0x0000
+#define PCI_DEVICE_ID_VORTEX_GDT6000B	0x0001
+#define PCI_DEVICE_ID_VORTEX_GDT6x10	0x0002
+#define PCI_DEVICE_ID_VORTEX_GDT6x20	0x0003
+#define PCI_DEVICE_ID_VORTEX_GDT6530	0x0004
+#define PCI_DEVICE_ID_VORTEX_GDT6550	0x0005
+#define PCI_DEVICE_ID_VORTEX_GDT6x17	0x0006
+#define PCI_DEVICE_ID_VORTEX_GDT6x27	0x0007
+#define PCI_DEVICE_ID_VORTEX_GDT6537	0x0008
+#define PCI_DEVICE_ID_VORTEX_GDT6557	0x0009
+#define PCI_DEVICE_ID_VORTEX_GDT6x15	0x000a
+#define PCI_DEVICE_ID_VORTEX_GDT6x25	0x000b
+#define PCI_DEVICE_ID_VORTEX_GDT6535	0x000c
+#define PCI_DEVICE_ID_VORTEX_GDT6555	0x000d
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP	0x0100
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP	0x0101
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP	0x0102
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1	0x0110
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1	0x0111
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP1	0x0112
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP1	0x0113
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1	0x0114
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1	0x0115
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2	0x0120
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2	0x0121
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP2	0x0122
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP2	0x0123
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2	0x0124
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2	0x0125
+
+#define PCI_VENDOR_ID_EF		0x111a
+#define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
+#define PCI_DEVICE_ID_EF_ATM_ASIC	0x0002
+#define PCI_VENDOR_ID_EF_ATM_LANAI2	0x0003
+#define PCI_VENDOR_ID_EF_ATM_LANAIHB	0x0005
+
+#define PCI_VENDOR_ID_IDT		0x111d
+#define PCI_DEVICE_ID_IDT_IDT77201	0x0001
+
+#define PCI_VENDOR_ID_FORE		0x1127
+#define PCI_DEVICE_ID_FORE_PCA200PC	0x0210
+#define PCI_DEVICE_ID_FORE_PCA200E	0x0300
+
+#define PCI_VENDOR_ID_IMAGINGTECH	0x112f
+#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI	0x0000
+
+#define PCI_VENDOR_ID_PHILIPS		0x1131
+#define PCI_DEVICE_ID_PHILIPS_SAA7145	0x7145
+#define PCI_DEVICE_ID_PHILIPS_SAA7146	0x7146
+#define PCI_DEVICE_ID_PHILIPS_SAA9730	0x9730
+
+#define PCI_VENDOR_ID_EICON		0x1133
+#define PCI_DEVICE_ID_EICON_DIVA20PRO	0xe001
+#define PCI_DEVICE_ID_EICON_DIVA20	0xe002
+#define PCI_DEVICE_ID_EICON_DIVA20PRO_U	0xe003
+#define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
+#define PCI_DEVICE_ID_EICON_DIVA201	0xe005
+#define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
+#define PCI_DEVICE_ID_EICON_MAESTRA	0xe010
+#define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
+#define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
+#define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
+
+#define PCI_VENDOR_ID_ZIATECH		0x1138
+#define PCI_DEVICE_ID_ZIATECH_5550_HC	0x5550
+ 
+#define PCI_VENDOR_ID_CYCLONE		0x113c
+#define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
+
+#define PCI_VENDOR_ID_ALLIANCE		0x1142
+#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO	0x3210
+#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO	0x6422
+#define PCI_DEVICE_ID_ALLIANCE_AT24	0x6424
+#define PCI_DEVICE_ID_ALLIANCE_AT3D	0x643d
+
+#define PCI_VENDOR_ID_SYSKONNECT	0x1148
+#define PCI_DEVICE_ID_SYSKONNECT_FP	0x4000
+#define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
+#define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
+#define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
+#define PCI_DEVICE_ID_SYSKONNECT_9DXX	0x4400
+#define PCI_DEVICE_ID_SYSKONNECT_9MXX	0x4500
+
+#define PCI_VENDOR_ID_VMIC		0x114a
+#define PCI_DEVICE_ID_VMIC_VME		0x7587
+
+#define PCI_VENDOR_ID_DIGI		0x114f
+#define PCI_DEVICE_ID_DIGI_EPC		0x0002
+#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH	0x0003
+#define PCI_DEVICE_ID_DIGI_XEM		0x0004
+#define PCI_DEVICE_ID_DIGI_XR		0x0005
+#define PCI_DEVICE_ID_DIGI_CX		0x0006
+#define PCI_DEVICE_ID_DIGI_XRJ		0x0009
+#define PCI_DEVICE_ID_DIGI_EPCJ		0x000a
+#define PCI_DEVICE_ID_DIGI_XR_920	0x0027
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E	0x0070
+#define PCI_DEVICE_ID_DIGI_DF_M_E	0x0071
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A	0x0072
+#define PCI_DEVICE_ID_DIGI_DF_M_A	0x0073
+#define PCI_DEVICE_ID_NEO_2DB9          0x00C8
+#define PCI_DEVICE_ID_NEO_2DB9PRI       0x00C9
+#define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
+#define PCI_DEVICE_ID_NEO_2RJ45PRI      0x00CB
+
+#define PCI_VENDOR_ID_MUTECH		0x1159
+#define PCI_DEVICE_ID_MUTECH_MV1000	0x0001
+
+#define PCI_VENDOR_ID_XIRCOM		0x115d
+#define PCI_DEVICE_ID_XIRCOM_X3201_ETH	0x0003
+#define PCI_DEVICE_ID_XIRCOM_RBM56G	0x0101
+#define PCI_DEVICE_ID_XIRCOM_X3201_MDM	0x0103
+
+#define PCI_VENDOR_ID_RENDITION		0x1163
+#define PCI_DEVICE_ID_RENDITION_VERITE	0x0001
+#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
+
+#define PCI_VENDOR_ID_SERVERWORKS	  0x1166
+#define PCI_DEVICE_ID_SERVERWORKS_HE	  0x0008
+#define PCI_DEVICE_ID_SERVERWORKS_LE	  0x0009
+#define PCI_DEVICE_ID_SERVERWORKS_CIOB30  0x0010
+#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011
+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4	  0x0200
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5	  0x0201
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6    0x0203
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE    0x0225
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE2   0x0227
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
+
+#define PCI_VENDOR_ID_SBE		0x1176
+#define PCI_DEVICE_ID_SBE_WANXL100	0x0301
+#define PCI_DEVICE_ID_SBE_WANXL200	0x0302
+#define PCI_DEVICE_ID_SBE_WANXL400	0x0104
+
+#define PCI_VENDOR_ID_TOSHIBA		0x1179
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO	0x0102
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1	0x0103
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2	0x0105
+#define PCI_DEVICE_ID_TOSHIBA_601	0x0601
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_A 0x0603
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_B 0x060a
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC100	0x0617
+
+#define PCI_VENDOR_ID_TOSHIBA_2		0x102f
+#define PCI_DEVICE_ID_TOSHIBA_TX3927	0x000a
+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF	0x0030
+#define PCI_DEVICE_ID_TOSHIBA_TX4927	0x0180
+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC	0x0108
+
+#define PCI_VENDOR_ID_RICOH		0x1180
+#define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
+#define PCI_DEVICE_ID_RICOH_RL5C466	0x0466
+#define PCI_DEVICE_ID_RICOH_RL5C475	0x0475
+#define PCI_DEVICE_ID_RICOH_RL5C476	0x0476
+#define PCI_DEVICE_ID_RICOH_RL5C478	0x0478
+
+#define PCI_VENDOR_ID_DLINK		0x1186
+#define PCI_DEVICE_ID_DLINK_DGE510T	0x4c00
+
+#define PCI_VENDOR_ID_ARTOP		0x1191
+#define PCI_DEVICE_ID_ARTOP_ATP8400	0x0004
+#define PCI_DEVICE_ID_ARTOP_ATP850UF	0x0005
+#define PCI_DEVICE_ID_ARTOP_ATP860	0x0006
+#define PCI_DEVICE_ID_ARTOP_ATP860R	0x0007
+#define PCI_DEVICE_ID_ARTOP_ATP865	0x0008
+#define PCI_DEVICE_ID_ARTOP_ATP865R	0x0009
+#define PCI_DEVICE_ID_ARTOP_AEC7610	0x8002
+#define PCI_DEVICE_ID_ARTOP_AEC7612UW	0x8010
+#define PCI_DEVICE_ID_ARTOP_AEC7612U	0x8020
+#define PCI_DEVICE_ID_ARTOP_AEC7612S	0x8030
+#define PCI_DEVICE_ID_ARTOP_AEC7612D	0x8040
+#define PCI_DEVICE_ID_ARTOP_AEC7612SUW	0x8050
+#define PCI_DEVICE_ID_ARTOP_8060	0x8060
+#define PCI_DEVICE_ID_ARTOP_AEC67160	0x8080
+#define PCI_DEVICE_ID_ARTOP_AEC67160_2	0x8081
+#define PCI_DEVICE_ID_ARTOP_AEC67162	0x808a
+
+#define PCI_VENDOR_ID_ZEITNET		0x1193
+#define PCI_DEVICE_ID_ZEITNET_1221	0x0001
+#define PCI_DEVICE_ID_ZEITNET_1225	0x0002
+
+#define PCI_VENDOR_ID_OMEGA		0x119b
+#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
+
+#define PCI_VENDOR_ID_FUJITSU_ME	0x119e
+#define PCI_DEVICE_ID_FUJITSU_FS155	0x0001
+#define PCI_DEVICE_ID_FUJITSU_FS50	0x0003
+
+#define PCI_SUBVENDOR_ID_KEYSPAN	0x11a9
+#define PCI_SUBDEVICE_ID_KEYSPAN_SX2	0x5334
+
+#define PCI_VENDOR_ID_MARVELL		0x11ab
+#define PCI_DEVICE_ID_MARVELL_GT64011	0x4146
+#define PCI_DEVICE_ID_MARVELL_GT64111	0x4146
+#define PCI_DEVICE_ID_MARVELL_GT64260	0x6430
+#define PCI_DEVICE_ID_MARVELL_MV64360	0x6460
+#define PCI_DEVICE_ID_MARVELL_MV64460	0x6480
+#define PCI_DEVICE_ID_MARVELL_GT96100	0x9652
+#define PCI_DEVICE_ID_MARVELL_GT96100A	0x9653
+
+#define PCI_VENDOR_ID_LITEON		0x11ad
+#define PCI_DEVICE_ID_LITEON_LNE100TX	0x0002
+
+#define PCI_VENDOR_ID_V3		0x11b0
+#define PCI_DEVICE_ID_V3_V960		0x0001
+#define PCI_DEVICE_ID_V3_V350		0x0001
+#define PCI_DEVICE_ID_V3_V961		0x0002
+#define PCI_DEVICE_ID_V3_V351		0x0002
+
+#define PCI_VENDOR_ID_NP		0x11bc
+#define PCI_DEVICE_ID_NP_PCI_FDDI	0x0001
+
+#define PCI_VENDOR_ID_ATT		0x11c1
+#define PCI_DEVICE_ID_ATT_L56XMF	0x0440
+#define PCI_DEVICE_ID_ATT_VENUS_MODEM	0x480
+
+#define PCI_VENDOR_ID_NEC2		0x11c3 /* NEC (2nd) */
+
+#define PCI_VENDOR_ID_SPECIALIX		0x11cb
+#define PCI_DEVICE_ID_SPECIALIX_IO8	0x2000
+#define PCI_DEVICE_ID_SPECIALIX_XIO	0x4000
+#define PCI_DEVICE_ID_SPECIALIX_RIO	0x8000
+#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
+
+#define PCI_VENDOR_ID_AURAVISION	0x11d1
+#define PCI_DEVICE_ID_AURAVISION_VXP524	0x01f7
+
+#define PCI_VENDOR_ID_ANALOG_DEVICES	0x11d4
+#define PCI_DEVICE_ID_AD1889JS		0x1889
+
+#define PCI_VENDOR_ID_IKON		0x11d5
+#define PCI_DEVICE_ID_IKON_10115	0x0115
+#define PCI_DEVICE_ID_IKON_10117	0x0117
+
+#define PCI_VENDOR_ID_SEGA		0x11db
+#define PCI_DEVICE_ID_SEGA_BBA		0x1234
+
+#define PCI_VENDOR_ID_ZORAN		0x11de
+#define PCI_DEVICE_ID_ZORAN_36057	0x6057
+#define PCI_DEVICE_ID_ZORAN_36120	0x6120
+
+#define PCI_VENDOR_ID_KINETIC		0x11f4
+#define PCI_DEVICE_ID_KINETIC_2915	0x2915
+
+#define PCI_VENDOR_ID_COMPEX		0x11f6
+#define PCI_DEVICE_ID_COMPEX_ENET100VG4	0x0112
+#define PCI_DEVICE_ID_COMPEX_RL2000	0x1401
+
+#define PCI_VENDOR_ID_RP		0x11fe
+#define PCI_DEVICE_ID_RP32INTF		0x0001
+#define PCI_DEVICE_ID_RP8INTF		0x0002
+#define PCI_DEVICE_ID_RP16INTF		0x0003
+#define PCI_DEVICE_ID_RP4QUAD		0x0004
+#define PCI_DEVICE_ID_RP8OCTA		0x0005
+#define PCI_DEVICE_ID_RP8J		0x0006
+#define PCI_DEVICE_ID_RP4J		0x0007
+#define PCI_DEVICE_ID_RP8SNI		0x0008	
+#define PCI_DEVICE_ID_RP16SNI		0x0009	
+#define PCI_DEVICE_ID_RPP4		0x000A
+#define PCI_DEVICE_ID_RPP8		0x000B
+#define PCI_DEVICE_ID_RP8M		0x000C
+#define PCI_DEVICE_ID_RP4M		0x000D
+#define PCI_DEVICE_ID_RP2_232		0x000E
+#define PCI_DEVICE_ID_RP2_422		0x000F
+#define PCI_DEVICE_ID_URP32INTF		0x0801
+#define PCI_DEVICE_ID_URP8INTF		0x0802
+#define PCI_DEVICE_ID_URP16INTF		0x0803
+#define PCI_DEVICE_ID_URP8OCTA		0x0805
+#define PCI_DEVICE_ID_UPCI_RM3_8PORT	0x080C       
+#define PCI_DEVICE_ID_UPCI_RM3_4PORT	0x080D
+#define PCI_DEVICE_ID_CRP16INTF		0x0903       
+
+#define PCI_VENDOR_ID_CYCLADES		0x120e
+#define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
+#define PCI_DEVICE_ID_CYCLOM_Y_Hi	0x0101
+#define PCI_DEVICE_ID_CYCLOM_4Y_Lo	0x0102
+#define PCI_DEVICE_ID_CYCLOM_4Y_Hi	0x0103
+#define PCI_DEVICE_ID_CYCLOM_8Y_Lo	0x0104
+#define PCI_DEVICE_ID_CYCLOM_8Y_Hi	0x0105
+#define PCI_DEVICE_ID_CYCLOM_Z_Lo	0x0200
+#define PCI_DEVICE_ID_CYCLOM_Z_Hi	0x0201
+#define PCI_DEVICE_ID_PC300_RX_2	0x0300
+#define PCI_DEVICE_ID_PC300_RX_1	0x0301
+#define PCI_DEVICE_ID_PC300_TE_2	0x0310
+#define PCI_DEVICE_ID_PC300_TE_1	0x0311
+#define PCI_DEVICE_ID_PC300_TE_M_2	0x0320
+#define PCI_DEVICE_ID_PC300_TE_M_1	0x0321
+
+/* Allied Telesyn */
+#define PCI_VENDOR_ID_AT    		0x1259
+#define PCI_SUBDEVICE_ID_AT_2701FX	0x2703
+
+#define PCI_VENDOR_ID_ESSENTIAL		0x120f
+#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER	0x0001
+
+#define PCI_VENDOR_ID_O2		0x1217
+#define PCI_DEVICE_ID_O2_6729		0x6729
+#define PCI_DEVICE_ID_O2_6730		0x673a
+#define PCI_DEVICE_ID_O2_6832		0x6832
+#define PCI_DEVICE_ID_O2_6836		0x6836
+
+#define PCI_VENDOR_ID_3DFX		0x121a
+#define PCI_DEVICE_ID_3DFX_VOODOO	0x0001
+#define PCI_DEVICE_ID_3DFX_VOODOO2	0x0002
+#define PCI_DEVICE_ID_3DFX_BANSHEE	0x0003
+#define PCI_DEVICE_ID_3DFX_VOODOO3	0x0005
+#define PCI_DEVICE_ID_3DFX_VOODOO5	0x0009
+
+#define PCI_VENDOR_ID_SIGMADES		0x1236
+#define PCI_DEVICE_ID_SIGMADES_6425	0x6401
+
+#define PCI_VENDOR_ID_CCUBE		0x123f
+
+#define PCI_VENDOR_ID_AVM		0x1244
+#define PCI_DEVICE_ID_AVM_B1		0x0700
+#define PCI_DEVICE_ID_AVM_C4		0x0800
+#define PCI_DEVICE_ID_AVM_A1		0x0a00
+#define PCI_DEVICE_ID_AVM_A1_V2		0x0e00
+#define PCI_DEVICE_ID_AVM_C2		0x1100
+#define PCI_DEVICE_ID_AVM_T1		0x1200
+
+#define PCI_VENDOR_ID_DIPIX		0x1246
+
+#define PCI_VENDOR_ID_STALLION		0x124d
+#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
+#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
+#define PCI_DEVICE_ID_STALLION_EIOPCI	0x0003
+
+#define PCI_VENDOR_ID_OPTIBASE		0x1255
+#define PCI_DEVICE_ID_OPTIBASE_FORGE	0x1110
+#define PCI_DEVICE_ID_OPTIBASE_FUSION	0x1210
+#define PCI_DEVICE_ID_OPTIBASE_VPLEX	0x2110
+#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC	0x2120
+#define PCI_DEVICE_ID_OPTIBASE_VQUEST	0x2130
+
+/* Allied Telesyn */
+#define PCI_VENDOR_ID_AT    		0x1259
+#define PCI_SUBDEVICE_ID_AT_2700FX	0x2701
+#define PCI_SUBDEVICE_ID_AT_2701FX	0x2703
+
+#define PCI_VENDOR_ID_ESS		0x125d
+#define PCI_DEVICE_ID_ESS_ESS1968	0x1968
+#define PCI_DEVICE_ID_ESS_AUDIOPCI	0x1969
+#define PCI_DEVICE_ID_ESS_ESS1978	0x1978
+
+#define PCI_VENDOR_ID_SATSAGEM		0x1267
+#define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
+#define PCI_DEVICE_ID_SATSAGEM_PCR2101	0x5352
+#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
+
+#define PCI_VENDOR_ID_HUGHES		0x1273
+#define PCI_DEVICE_ID_HUGHES_DIRECPC	0x0002
+
+#define PCI_VENDOR_ID_ENSONIQ		0x1274
+#define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
+#define PCI_DEVICE_ID_ENSONIQ_ES1370	0x5000
+#define PCI_DEVICE_ID_ENSONIQ_ES1371	0x1371
+
+#define PCI_VENDOR_ID_TRANSMETA		0x1279
+#define PCI_DEVICE_ID_EFFICEON		0x0060
+
+#define PCI_VENDOR_ID_ROCKWELL		0x127A
+
+#define PCI_VENDOR_ID_ITE		0x1283
+#define PCI_DEVICE_ID_ITE_IT8172G	0x8172
+#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
+#define PCI_DEVICE_ID_ITE_8872		0x8872
+#define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
+
+/* formerly Platform Tech */
+#define PCI_VENDOR_ID_ESS_OLD		0x1285
+#define PCI_DEVICE_ID_ESS_ESS0100	0x0100
+
+#define PCI_VENDOR_ID_ALTEON		0x12ae
+#define PCI_DEVICE_ID_ALTEON_ACENIC	0x0001
+
+#define PCI_VENDOR_ID_USR		0x12B9
+
+#define PCI_SUBVENDOR_ID_CONNECT_TECH			0x12c4
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232		0x0001
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232		0x0002
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232		0x0003
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485		0x0004
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4	0x0005
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485		0x0006
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2	0x0007
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485		0x0008
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6	0x0009
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1	0x000A
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1	0x000B
+
+#define PCI_VENDOR_ID_PICTUREL		0x12c5
+#define PCI_DEVICE_ID_PICTUREL_PCIVST	0x0081
+
+#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2
+#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
+
+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST		0x12E0
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4		0x0031
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8		0x0021
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16	0x0011
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC	0x0041
+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS		0x124D
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4		0xF001
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8		0xF010
+
+#define PCI_VENDOR_ID_AUREAL		0x12eb
+#define PCI_DEVICE_ID_AUREAL_VORTEX_1	0x0001
+#define PCI_DEVICE_ID_AUREAL_VORTEX_2	0x0002
+#define PCI_DEVICE_ID_AUREAL_ADVANTAGE	0x0003
+
+#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
+#define PCI_DEVICE_ID_LML_33R10		0x8a02
+
+#define PCI_VENDOR_ID_CBOARDS		0x1307
+#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
+
+#define PCI_VENDOR_ID_SIIG		0x131f
+#define PCI_DEVICE_ID_SIIG_1S_10x_550	0x1000
+#define PCI_DEVICE_ID_SIIG_1S_10x_650	0x1001
+#define PCI_DEVICE_ID_SIIG_1S_10x_850	0x1002
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550	0x1010
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650	0x1011
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850	0x1012
+#define PCI_DEVICE_ID_SIIG_1P_10x	0x1020
+#define PCI_DEVICE_ID_SIIG_2P_10x	0x1021
+#define PCI_DEVICE_ID_SIIG_2S_10x_550	0x1030
+#define PCI_DEVICE_ID_SIIG_2S_10x_650	0x1031
+#define PCI_DEVICE_ID_SIIG_2S_10x_850	0x1032
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550	0x1034
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650	0x1035
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850	0x1036
+#define PCI_DEVICE_ID_SIIG_4S_10x_550	0x1050
+#define PCI_DEVICE_ID_SIIG_4S_10x_650	0x1051
+#define PCI_DEVICE_ID_SIIG_4S_10x_850	0x1052
+#define PCI_DEVICE_ID_SIIG_1S_20x_550	0x2000
+#define PCI_DEVICE_ID_SIIG_1S_20x_650	0x2001
+#define PCI_DEVICE_ID_SIIG_1S_20x_850	0x2002
+#define PCI_DEVICE_ID_SIIG_1P_20x	0x2020
+#define PCI_DEVICE_ID_SIIG_2P_20x	0x2021
+#define PCI_DEVICE_ID_SIIG_2S_20x_550	0x2030
+#define PCI_DEVICE_ID_SIIG_2S_20x_650	0x2031
+#define PCI_DEVICE_ID_SIIG_2S_20x_850	0x2032
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550	0x2040
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650	0x2041
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850	0x2042
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550	0x2010
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650	0x2011
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850	0x2012
+#define PCI_DEVICE_ID_SIIG_4S_20x_550	0x2050
+#define PCI_DEVICE_ID_SIIG_4S_20x_650	0x2051
+#define PCI_DEVICE_ID_SIIG_4S_20x_850	0x2052
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550	0x2060
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650	0x2061
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850	0x2062
+
+#define PCI_VENDOR_ID_RADISYS		0x1331
+#define PCI_DEVICE_ID_RADISYS_ENP2611	0x0030
+
+#define PCI_VENDOR_ID_DOMEX		0x134a
+#define PCI_DEVICE_ID_DOMEX_DMX3191D	0x0001
+
+#define PCI_VENDOR_ID_QUATECH		0x135C
+#define PCI_DEVICE_ID_QUATECH_QSC100	0x0010
+#define PCI_DEVICE_ID_QUATECH_DSC100	0x0020
+#define PCI_DEVICE_ID_QUATECH_DSC200	0x0030
+#define PCI_DEVICE_ID_QUATECH_QSC200	0x0040
+#define PCI_DEVICE_ID_QUATECH_ESC100D	0x0050
+#define PCI_DEVICE_ID_QUATECH_ESC100M	0x0060
+
+#define PCI_VENDOR_ID_SEALEVEL		0x135e
+#define PCI_DEVICE_ID_SEALEVEL_U530	0x7101
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM2	0x7201
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422	0x7402
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232	0x7202
+#define PCI_DEVICE_ID_SEALEVEL_COMM4	0x7401
+#define PCI_DEVICE_ID_SEALEVEL_COMM8	0x7801
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM8	0x7804
+
+#define PCI_VENDOR_ID_HYPERCOPE		0x1365
+#define PCI_DEVICE_ID_HYPERCOPE_PLX	0x9050
+#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO	0x0104
+#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO		0x0106
+#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO	0x0107
+#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2	0x0108
+#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS	0x0109
+
+#define PCI_VENDOR_ID_KAWASAKI		0x136b
+#define PCI_DEVICE_ID_MCHIP_KL5A72002	0xff01
+
+#define PCI_VENDOR_ID_CNET		0x1371
+#define PCI_DEVICE_ID_CNET_GIGACARD	0x434e
+
+#define PCI_VENDOR_ID_LMC		0x1376
+#define PCI_DEVICE_ID_LMC_HSSI		0x0003
+#define PCI_DEVICE_ID_LMC_DS3		0x0004
+#define PCI_DEVICE_ID_LMC_SSI		0x0005
+#define PCI_DEVICE_ID_LMC_T1		0x0006
+
+#define PCI_VENDOR_ID_NETGEAR		0x1385
+#define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
+#define PCI_DEVICE_ID_NETGEAR_GA622	0x622a
+
+#define PCI_VENDOR_ID_APPLICOM		0x1389
+#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
+#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
+#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
+
+#define PCI_VENDOR_ID_MOXA		0x1393
+#define PCI_DEVICE_ID_MOXA_RC7000	0x0001
+#define PCI_DEVICE_ID_MOXA_CP102	0x1020
+#define PCI_DEVICE_ID_MOXA_CP102UL	0x1021
+#define PCI_DEVICE_ID_MOXA_CP102U	0x1022
+#define PCI_DEVICE_ID_MOXA_C104		0x1040
+#define PCI_DEVICE_ID_MOXA_CP104U	0x1041
+#define PCI_DEVICE_ID_MOXA_CP104JU	0x1042
+#define PCI_DEVICE_ID_MOXA_CT114	0x1140
+#define PCI_DEVICE_ID_MOXA_CP114	0x1141
+#define PCI_DEVICE_ID_MOXA_CP118U	0x1180
+#define PCI_DEVICE_ID_MOXA_CP132	0x1320
+#define PCI_DEVICE_ID_MOXA_CP132U	0x1321
+#define PCI_DEVICE_ID_MOXA_CP134U	0x1340
+#define PCI_DEVICE_ID_MOXA_C168		0x1680
+#define PCI_DEVICE_ID_MOXA_CP168U	0x1681
+#define PCI_DEVICE_ID_MOXA_CP204J	0x2040
+#define PCI_DEVICE_ID_MOXA_C218		0x2180
+#define PCI_DEVICE_ID_MOXA_C320		0x3200
+
+#define PCI_VENDOR_ID_CCD		0x1397
+#define PCI_DEVICE_ID_CCD_2BD0		0x2bd0
+#define PCI_DEVICE_ID_CCD_B000		0xb000
+#define PCI_DEVICE_ID_CCD_B006		0xb006
+#define PCI_DEVICE_ID_CCD_B007		0xb007
+#define PCI_DEVICE_ID_CCD_B008		0xb008
+#define PCI_DEVICE_ID_CCD_B009		0xb009
+#define PCI_DEVICE_ID_CCD_B00A		0xb00a
+#define PCI_DEVICE_ID_CCD_B00B		0xb00b
+#define PCI_DEVICE_ID_CCD_B00C		0xb00c
+#define PCI_DEVICE_ID_CCD_B100		0xb100
+
+#define PCI_VENDOR_ID_EXAR		0x13a8
+#define PCI_DEVICE_ID_EXAR_XR17C152	0x0152
+#define PCI_DEVICE_ID_EXAR_XR17C154	0x0154
+#define PCI_DEVICE_ID_EXAR_XR17C158	0x0158
+
+#define PCI_VENDOR_ID_MICROGATE		0x13c0
+#define PCI_DEVICE_ID_MICROGATE_USC	0x0010
+#define PCI_DEVICE_ID_MICROGATE_SCC	0x0020
+#define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
+#define PCI_DEVICE_ID_MICROGATE_USC2	0x0210
+
+#define PCI_VENDOR_ID_3WARE		0x13C1
+#define PCI_DEVICE_ID_3WARE_1000	0x1000
+#define PCI_DEVICE_ID_3WARE_7000	0x1001
+#define PCI_DEVICE_ID_3WARE_9000	0x1002
+
+#define PCI_VENDOR_ID_IOMEGA		0x13ca
+#define PCI_DEVICE_ID_IOMEGA_BUZ	0x4231
+
+#define PCI_VENDOR_ID_ABOCOM		0x13D1
+#define PCI_DEVICE_ID_ABOCOM_2BD1       0x2BD1
+
+#define PCI_VENDOR_ID_CMEDIA		0x13f6
+#define PCI_DEVICE_ID_CMEDIA_CM8338A	0x0100
+#define PCI_DEVICE_ID_CMEDIA_CM8338B	0x0101
+#define PCI_DEVICE_ID_CMEDIA_CM8738	0x0111
+#define PCI_DEVICE_ID_CMEDIA_CM8738B	0x0112
+
+#define PCI_VENDOR_ID_LAVA		0x1407
+#define PCI_DEVICE_ID_LAVA_DSERIAL	0x0100 /* 2x 16550 */
+#define PCI_DEVICE_ID_LAVA_QUATRO_A	0x0101 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATRO_B	0x0102 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_A	0x0180 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_B	0x0181 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_PORT_PLUS	0x0200 /* 2x 16650 */
+#define PCI_DEVICE_ID_LAVA_QUAD_A	0x0201 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUAD_B	0x0202 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_SSERIAL	0x0500 /* 1x 16550 */
+#define PCI_DEVICE_ID_LAVA_PORT_650	0x0600 /* 1x 16650 */
+#define PCI_DEVICE_ID_LAVA_PARALLEL	0x8000
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A	0x8002 /* The Lava Dual Parallel is */
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B	0x8003 /* two PCI devices on a card */
+#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR	0x8800
+
+#define PCI_VENDOR_ID_TIMEDIA		0x1409
+#define PCI_DEVICE_ID_TIMEDIA_1889	0x7168
+
+#define PCI_VENDOR_ID_OXSEMI		0x1415
+#define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
+#define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
+#define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP	0x9513
+#define PCI_DEVICE_ID_OXSEMI_16PCI952	0x9521
+
+#define PCI_VENDOR_ID_SAMSUNG		0x144d
+
+#define PCI_VENDOR_ID_AIRONET		0x14b9
+#define PCI_DEVICE_ID_AIRONET_4800_1	0x0001
+#define PCI_DEVICE_ID_AIRONET_4800	0x4500 // values switched?  see
+#define PCI_DEVICE_ID_AIRONET_4500	0x4800 // drivers/net/aironet4500_card.c
+
+#define PCI_VENDOR_ID_TITAN		0x14D2
+#define PCI_DEVICE_ID_TITAN_010L	0x8001
+#define PCI_DEVICE_ID_TITAN_100L	0x8010
+#define PCI_DEVICE_ID_TITAN_110L	0x8011
+#define PCI_DEVICE_ID_TITAN_200L	0x8020
+#define PCI_DEVICE_ID_TITAN_210L	0x8021
+#define PCI_DEVICE_ID_TITAN_400L	0x8040
+#define PCI_DEVICE_ID_TITAN_800L	0x8080
+#define PCI_DEVICE_ID_TITAN_100		0xA001
+#define PCI_DEVICE_ID_TITAN_200		0xA005
+#define PCI_DEVICE_ID_TITAN_400		0xA003
+#define PCI_DEVICE_ID_TITAN_800B	0xA004
+
+#define PCI_VENDOR_ID_PANACOM		0x14d4
+#define PCI_DEVICE_ID_PANACOM_QUADMODEM	0x0400
+#define PCI_DEVICE_ID_PANACOM_DUALMODEM	0x0402
+
+#define PCI_VENDOR_ID_SIPACKETS		0x14d9
+#define PCI_DEVICE_ID_SP_HT		0x0010
+
+#define PCI_VENDOR_ID_AFAVLAB		0x14db
+#define PCI_DEVICE_ID_AFAVLAB_P028	0x2180
+#define PCI_DEVICE_ID_AFAVLAB_P030	0x2182
+
+#define PCI_VENDOR_ID_BROADCOM		0x14e4
+#define PCI_DEVICE_ID_TIGON3_5752	0x1600
+#define PCI_DEVICE_ID_TIGON3_5752M	0x1601
+#define PCI_DEVICE_ID_TIGON3_5700	0x1644
+#define PCI_DEVICE_ID_TIGON3_5701	0x1645
+#define PCI_DEVICE_ID_TIGON3_5702	0x1646
+#define PCI_DEVICE_ID_TIGON3_5703	0x1647
+#define PCI_DEVICE_ID_TIGON3_5704	0x1648
+#define PCI_DEVICE_ID_TIGON3_5704S_2	0x1649
+#define PCI_DEVICE_ID_NX2_5706		0x164a
+#define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
+#define PCI_DEVICE_ID_TIGON3_5705	0x1653
+#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
+#define PCI_DEVICE_ID_TIGON3_5720	0x1658
+#define PCI_DEVICE_ID_TIGON3_5721	0x1659
+#define PCI_DEVICE_ID_TIGON3_5705M	0x165d
+#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e
+#define PCI_DEVICE_ID_TIGON3_5705F	0x166e
+#define PCI_DEVICE_ID_TIGON3_5750	0x1676
+#define PCI_DEVICE_ID_TIGON3_5751	0x1677
+#define PCI_DEVICE_ID_TIGON3_5750M	0x167c
+#define PCI_DEVICE_ID_TIGON3_5751M	0x167d
+#define PCI_DEVICE_ID_TIGON3_5751F	0x167e
+#define PCI_DEVICE_ID_TIGON3_5782	0x1696
+#define PCI_DEVICE_ID_TIGON3_5788	0x169c
+#define PCI_DEVICE_ID_TIGON3_5789	0x169d
+#define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
+#define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
+#define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
+#define PCI_DEVICE_ID_NX2_5706S		0x16aa
+#define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
+#define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
+#define PCI_DEVICE_ID_TIGON3_5781	0x16dd
+#define PCI_DEVICE_ID_TIGON3_5753	0x16f7
+#define PCI_DEVICE_ID_TIGON3_5753M	0x16fd
+#define PCI_DEVICE_ID_TIGON3_5753F	0x16fe
+#define PCI_DEVICE_ID_TIGON3_5901	0x170d
+#define PCI_DEVICE_ID_BCM4401B1		0x170c
+#define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
+#define PCI_DEVICE_ID_BCM4401		0x4401
+#define PCI_DEVICE_ID_BCM4401B0		0x4402
+
+#define PCI_VENDOR_ID_TOPIC		0x151f
+#define PCI_DEVICE_ID_TOPIC_TP560	0x0000
+
+#define PCI_VENDOR_ID_ENE		0x1524
+#define PCI_DEVICE_ID_ENE_1211		0x1211
+#define PCI_DEVICE_ID_ENE_1225		0x1225
+#define PCI_DEVICE_ID_ENE_1410		0x1410
+#define PCI_DEVICE_ID_ENE_1420		0x1420
+
+#define PCI_VENDOR_ID_SYBA		0x1592
+#define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
+#define PCI_DEVICE_ID_SYBA_1P_ECP	0x0783
+
+#define PCI_VENDOR_ID_MORETON		0x15aa
+#define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
+
+#define PCI_VENDOR_ID_ZOLTRIX		0x15b0
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0 
+
+#define PCI_VENDOR_ID_MELLANOX		0x15b3
+#define PCI_DEVICE_ID_MELLANOX_TAVOR	0x5a44
+#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
+#define PCI_DEVICE_ID_MELLANOX_ARBEL	0x6282
+#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
+#define PCI_DEVICE_ID_MELLANOX_SINAI	0x6274
+
+#define PCI_VENDOR_ID_PDC		0x15e9
+#define PCI_DEVICE_ID_PDC_1841		0x1841
+
+#define PCI_VENDOR_ID_MACROLINK		0x15ed
+#define PCI_DEVICE_ID_MACROLINK_MCCS8	0x1000
+#define PCI_DEVICE_ID_MACROLINK_MCCS	0x1001
+#define PCI_DEVICE_ID_MACROLINK_MCCS8H	0x1002
+#define PCI_DEVICE_ID_MACROLINK_MCCSH	0x1003
+#define PCI_DEVICE_ID_MACROLINK_MCCR8	0x2000
+#define PCI_DEVICE_ID_MACROLINK_MCCR	0x2001
+
+#define PCI_VENDOR_ID_FARSITE           0x1619
+#define PCI_DEVICE_ID_FARSITE_T2P       0x0400
+#define PCI_DEVICE_ID_FARSITE_T4P       0x0440
+#define PCI_DEVICE_ID_FARSITE_T1U       0x0610
+#define PCI_DEVICE_ID_FARSITE_T2U       0x0620
+#define PCI_DEVICE_ID_FARSITE_T4U       0x0640
+#define PCI_DEVICE_ID_FARSITE_TE1       0x1610
+#define PCI_DEVICE_ID_FARSITE_TE1C      0x1612
+
+#define PCI_VENDOR_ID_SIBYTE		0x166d
+#define PCI_DEVICE_ID_BCM1250_HT	0x0002
+
+#define PCI_VENDOR_ID_LINKSYS		0x1737
+#define PCI_DEVICE_ID_LINKSYS_EG1032	0x1032
+#define PCI_DEVICE_ID_LINKSYS_EG1064	0x1064
+
+#define PCI_VENDOR_ID_ALTIMA		0x173b
+#define PCI_DEVICE_ID_ALTIMA_AC1000	0x03e8
+#define PCI_DEVICE_ID_ALTIMA_AC1001	0x03e9
+#define PCI_DEVICE_ID_ALTIMA_AC9100	0x03ea
+#define PCI_DEVICE_ID_ALTIMA_AC1003	0x03eb
+
+#define PCI_VENDOR_ID_S2IO		0x17d5
+#define	PCI_DEVICE_ID_S2IO_WIN		0x5731
+#define	PCI_DEVICE_ID_S2IO_UNI		0x5831
+#define PCI_DEVICE_ID_HERC_WIN		0x5732
+#define PCI_DEVICE_ID_HERC_UNI		0x5832
+
+#define PCI_VENDOR_ID_INFINICON		0x1820
+
+#define PCI_VENDOR_ID_TOPSPIN		0x1867
+
+#define PCI_VENDOR_ID_TDI               0x192E
+#define PCI_DEVICE_ID_TDI_EHCI          0x0101
+
+#define PCI_VENDOR_ID_SYMPHONY		0x1c1c
+#define PCI_DEVICE_ID_SYMPHONY_101	0x0001
+
+#define PCI_VENDOR_ID_TEKRAM		0x1de1
+#define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
+
+#define PCI_VENDOR_ID_HINT             0x3388
+#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
+
+#define PCI_VENDOR_ID_3DLABS		0x3d3d
+#define PCI_DEVICE_ID_3DLABS_300SX	0x0001
+#define PCI_DEVICE_ID_3DLABS_500TX	0x0002
+#define PCI_DEVICE_ID_3DLABS_DELTA	0x0003
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA	0x0004
+#define PCI_DEVICE_ID_3DLABS_MX		0x0006
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2	0x0007
+#define PCI_DEVICE_ID_3DLABS_GAMMA	0x0008
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V	0x0009
+
+#define PCI_VENDOR_ID_AVANCE		0x4005
+#define PCI_DEVICE_ID_AVANCE_ALG2064	0x2064
+#define PCI_DEVICE_ID_AVANCE_2302	0x2302
+
+#define PCI_VENDOR_ID_AKS		0x416c
+#define PCI_DEVICE_ID_AKS_ALADDINCARD	0x0100
+#define PCI_DEVICE_ID_AKS_CPC		0x0200
+
+#define PCI_VENDOR_ID_REDCREEK		0x4916
+#define PCI_DEVICE_ID_RC45		0x1960
+
+#define PCI_VENDOR_ID_NETVIN		0x4a14
+#define PCI_DEVICE_ID_NETVIN_NV5000SC	0x5000
+
+#define PCI_VENDOR_ID_S3		0x5333
+#define PCI_DEVICE_ID_S3_PLATO_PXS	0x0551
+#define PCI_DEVICE_ID_S3_ViRGE		0x5631
+#define PCI_DEVICE_ID_S3_TRIO		0x8811
+#define PCI_DEVICE_ID_S3_AURORA64VP	0x8812
+#define PCI_DEVICE_ID_S3_TRIO64UVP	0x8814
+#define PCI_DEVICE_ID_S3_ViRGE_VX	0x883d
+#define PCI_DEVICE_ID_S3_868		0x8880
+#define PCI_DEVICE_ID_S3_928		0x88b0
+#define PCI_DEVICE_ID_S3_864_1		0x88c0
+#define PCI_DEVICE_ID_S3_864_2		0x88c1
+#define PCI_DEVICE_ID_S3_964_1		0x88d0
+#define PCI_DEVICE_ID_S3_964_2		0x88d1
+#define PCI_DEVICE_ID_S3_968		0x88f0
+#define PCI_DEVICE_ID_S3_TRIO64V2	0x8901
+#define PCI_DEVICE_ID_S3_PLATO_PXG	0x8902
+#define PCI_DEVICE_ID_S3_ViRGE_DXGX	0x8a01
+#define PCI_DEVICE_ID_S3_ViRGE_GX2	0x8a10
+#define PCI_DEVICE_ID_S3_SAVAGE4	0x8a25
+#define PCI_DEVICE_ID_S3_ViRGE_MX	0x8c01
+#define PCI_DEVICE_ID_S3_ViRGE_MXP	0x8c02
+#define PCI_DEVICE_ID_S3_ViRGE_MXPMV	0x8c03
+#define PCI_DEVICE_ID_S3_PROSAVAGE8	0x8d04
+#define PCI_DEVICE_ID_S3_SONICVIBES	0xca00
+
+#define PCI_VENDOR_ID_DUNORD		0x5544
+#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
+
+#define PCI_VENDOR_ID_DCI		0x6666
+#define PCI_DEVICE_ID_DCI_PCCOM4	0x0001
+#define PCI_DEVICE_ID_DCI_PCCOM8	0x0002
+
+#define PCI_VENDOR_ID_DUNORD		0x5544
+#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
+
+#define PCI_VENDOR_ID_GENROCO		0x5555
+#define PCI_DEVICE_ID_GENROCO_HFP832	0x0003
+
+#define PCI_VENDOR_ID_INTEL		0x8086
+#define PCI_DEVICE_ID_INTEL_EESSC	0x0008
+#define PCI_DEVICE_ID_INTEL_21145	0x0039
+#define PCI_DEVICE_ID_INTEL_82375	0x0482
+#define PCI_DEVICE_ID_INTEL_82424	0x0483
+#define PCI_DEVICE_ID_INTEL_82378	0x0484
+#define PCI_DEVICE_ID_INTEL_82430	0x0486
+#define PCI_DEVICE_ID_INTEL_82434	0x04a3
+#define PCI_DEVICE_ID_INTEL_I960	0x0960
+#define PCI_DEVICE_ID_INTEL_I960RM	0x0962
+#define PCI_DEVICE_ID_INTEL_82562ET	0x1031
+#define PCI_DEVICE_ID_INTEL_82801CAM	0x1038
+#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130
+#define PCI_DEVICE_ID_INTEL_82815_AB	0x1131
+#define PCI_DEVICE_ID_INTEL_82815_CGC	0x1132
+#define PCI_DEVICE_ID_INTEL_82559ER	0x1209
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222
+#define PCI_DEVICE_ID_INTEL_7116	0x1223
+#define PCI_DEVICE_ID_INTEL_7505_0	0x2550  
+#define PCI_DEVICE_ID_INTEL_7505_1	0x2552  
+#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
+#define PCI_DEVICE_ID_INTEL_82596	0x1226
+#define PCI_DEVICE_ID_INTEL_82865	0x1227
+#define PCI_DEVICE_ID_INTEL_82557	0x1229
+#define PCI_DEVICE_ID_INTEL_82437	0x122d
+#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e
+#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
+#define PCI_DEVICE_ID_INTEL_82371MX	0x1234
+#define PCI_DEVICE_ID_INTEL_82437MX	0x1235
+#define PCI_DEVICE_ID_INTEL_82441	0x1237
+#define PCI_DEVICE_ID_INTEL_82380FB	0x124b
+#define PCI_DEVICE_ID_INTEL_82439	0x1250
+#define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
+#define PCI_DEVICE_ID_INTEL_82840_HB	0x1a21
+#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30
+#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
+#define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
+#define PCI_DEVICE_ID_INTEL_82801AA_2	0x2412
+#define PCI_DEVICE_ID_INTEL_82801AA_3	0x2413
+#define PCI_DEVICE_ID_INTEL_82801AA_5	0x2415
+#define PCI_DEVICE_ID_INTEL_82801AA_6	0x2416
+#define PCI_DEVICE_ID_INTEL_82801AA_8	0x2418
+#define PCI_DEVICE_ID_INTEL_82801AB_0	0x2420
+#define PCI_DEVICE_ID_INTEL_82801AB_1	0x2421
+#define PCI_DEVICE_ID_INTEL_82801AB_2	0x2422
+#define PCI_DEVICE_ID_INTEL_82801AB_3	0x2423
+#define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
+#define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
+#define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
+#define PCI_DEVICE_ID_INTEL_82801BA_0	0x2440
+#define PCI_DEVICE_ID_INTEL_82801BA_1	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BA_2	0x2443
+#define PCI_DEVICE_ID_INTEL_82801BA_3	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BA_4	0x2445
+#define PCI_DEVICE_ID_INTEL_82801BA_5	0x2446
+#define PCI_DEVICE_ID_INTEL_82801BA_6	0x2448
+#define PCI_DEVICE_ID_INTEL_82801BA_7	0x2449
+#define PCI_DEVICE_ID_INTEL_82801BA_8	0x244a
+#define PCI_DEVICE_ID_INTEL_82801BA_9	0x244b
+#define PCI_DEVICE_ID_INTEL_82801BA_10	0x244c
+#define PCI_DEVICE_ID_INTEL_82801BA_11	0x244e
+#define PCI_DEVICE_ID_INTEL_82801E_0	0x2450
+#define PCI_DEVICE_ID_INTEL_82801E_2	0x2452
+#define PCI_DEVICE_ID_INTEL_82801E_3	0x2453
+#define PCI_DEVICE_ID_INTEL_82801E_9	0x2459
+#define PCI_DEVICE_ID_INTEL_82801E_11	0x245b
+#define PCI_DEVICE_ID_INTEL_82801E_13	0x245d
+#define PCI_DEVICE_ID_INTEL_82801E_14	0x245e
+#define PCI_DEVICE_ID_INTEL_82801CA_0	0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_2	0x2482
+#define PCI_DEVICE_ID_INTEL_82801CA_3	0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_4	0x2484
+#define PCI_DEVICE_ID_INTEL_82801CA_5	0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_6	0x2486
+#define PCI_DEVICE_ID_INTEL_82801CA_7	0x2487
+#define PCI_DEVICE_ID_INTEL_82801CA_10	0x248a
+#define PCI_DEVICE_ID_INTEL_82801CA_11	0x248b
+#define PCI_DEVICE_ID_INTEL_82801CA_12	0x248c
+#define PCI_DEVICE_ID_INTEL_82801DB_0	0x24c0
+#define PCI_DEVICE_ID_INTEL_82801DB_1	0x24c1
+#define PCI_DEVICE_ID_INTEL_82801DB_2	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DB_3	0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DB_4	0x24c4
+#define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DB_7	0x24c7
+#define PCI_DEVICE_ID_INTEL_82801DB_9	0x24c9
+#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
+#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
+#define PCI_DEVICE_ID_INTEL_82801DB_13	0x24cd
+#define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
+#define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
+#define PCI_DEVICE_ID_INTEL_82801EB_2	0x24d2
+#define PCI_DEVICE_ID_INTEL_82801EB_3	0x24d3
+#define PCI_DEVICE_ID_INTEL_82801EB_4	0x24d4
+#define PCI_DEVICE_ID_INTEL_82801EB_5	0x24d5
+#define PCI_DEVICE_ID_INTEL_82801EB_6	0x24d6
+#define PCI_DEVICE_ID_INTEL_82801EB_7	0x24d7
+#define PCI_DEVICE_ID_INTEL_82801EB_11	0x24db
+#define PCI_DEVICE_ID_INTEL_82801EB_13	0x24dd
+#define PCI_DEVICE_ID_INTEL_ESB_1	0x25a1
+#define PCI_DEVICE_ID_INTEL_ESB_2	0x25a2
+#define PCI_DEVICE_ID_INTEL_ESB_3	0x25a3
+#define PCI_DEVICE_ID_INTEL_ESB_31	0x25b0
+#define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
+#define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
+#define PCI_DEVICE_ID_INTEL_ESB_6	0x25a7
+#define PCI_DEVICE_ID_INTEL_ESB_7	0x25a9
+#define PCI_DEVICE_ID_INTEL_ESB_8	0x25aa
+#define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_11	0x25ac
+#define PCI_DEVICE_ID_INTEL_ESB_12	0x25ad
+#define PCI_DEVICE_ID_INTEL_ESB_13	0x25ae
+#define PCI_DEVICE_ID_INTEL_82820_HB	0x2500
+#define PCI_DEVICE_ID_INTEL_82820_UP_HB	0x2501
+#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
+#define PCI_DEVICE_ID_INTEL_82860_HB	0x2531
+#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
+#define PCI_DEVICE_ID_INTEL_82845G_IG	0x2562
+#define PCI_DEVICE_ID_INTEL_82865_HB	0x2570
+#define PCI_DEVICE_ID_INTEL_82865_IG	0x2572
+#define PCI_DEVICE_ID_INTEL_82875_HB	0x2578
+#define PCI_DEVICE_ID_INTEL_82875_IG	0x257b
+#define PCI_DEVICE_ID_INTEL_82915G_HB	0x2580
+#define PCI_DEVICE_ID_INTEL_82915G_IG	0x2582
+#define PCI_DEVICE_ID_INTEL_82915GM_HB	0x2590
+#define PCI_DEVICE_ID_INTEL_82915GM_IG	0x2592
+#define PCI_DEVICE_ID_INTEL_82945G_HB	0x2770
+#define PCI_DEVICE_ID_INTEL_82945G_IG	0x2772
+#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640
+#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641
+#define PCI_DEVICE_ID_INTEL_ICH6_2	0x2642
+#define PCI_DEVICE_ID_INTEL_ICH6_3	0x2651
+#define PCI_DEVICE_ID_INTEL_ICH6_4	0x2652
+#define PCI_DEVICE_ID_INTEL_ICH6_5	0x2653
+#define PCI_DEVICE_ID_INTEL_ICH6_6	0x2658
+#define PCI_DEVICE_ID_INTEL_ICH6_7	0x2659
+#define PCI_DEVICE_ID_INTEL_ICH6_8	0x265a
+#define PCI_DEVICE_ID_INTEL_ICH6_9	0x265b
+#define PCI_DEVICE_ID_INTEL_ICH6_10	0x265c
+#define PCI_DEVICE_ID_INTEL_ICH6_11	0x2660
+#define PCI_DEVICE_ID_INTEL_ICH6_12	0x2662
+#define PCI_DEVICE_ID_INTEL_ICH6_13	0x2664
+#define PCI_DEVICE_ID_INTEL_ICH6_14	0x2666
+#define PCI_DEVICE_ID_INTEL_ICH6_15	0x2668
+#define PCI_DEVICE_ID_INTEL_ICH6_16	0x266a
+#define PCI_DEVICE_ID_INTEL_ICH6_17	0x266d
+#define PCI_DEVICE_ID_INTEL_ICH6_18	0x266e
+#define PCI_DEVICE_ID_INTEL_ICH6_19	0x266f
+#define PCI_DEVICE_ID_INTEL_ESB2_0	0x2670
+#define PCI_DEVICE_ID_INTEL_ESB2_1	0x2680
+#define PCI_DEVICE_ID_INTEL_ESB2_2	0x2681
+#define PCI_DEVICE_ID_INTEL_ESB2_3	0x2682
+#define PCI_DEVICE_ID_INTEL_ESB2_4	0x2683
+#define PCI_DEVICE_ID_INTEL_ESB2_5	0x2688
+#define PCI_DEVICE_ID_INTEL_ESB2_6	0x2689
+#define PCI_DEVICE_ID_INTEL_ESB2_7	0x268a
+#define PCI_DEVICE_ID_INTEL_ESB2_8	0x268b
+#define PCI_DEVICE_ID_INTEL_ESB2_9	0x268c
+#define PCI_DEVICE_ID_INTEL_ESB2_10	0x2690
+#define PCI_DEVICE_ID_INTEL_ESB2_11	0x2692
+#define PCI_DEVICE_ID_INTEL_ESB2_12	0x2694
+#define PCI_DEVICE_ID_INTEL_ESB2_13	0x2696
+#define PCI_DEVICE_ID_INTEL_ESB2_14	0x2698
+#define PCI_DEVICE_ID_INTEL_ESB2_15	0x2699
+#define PCI_DEVICE_ID_INTEL_ESB2_16	0x269a
+#define PCI_DEVICE_ID_INTEL_ESB2_17	0x269b
+#define PCI_DEVICE_ID_INTEL_ESB2_18	0x269e
+#define PCI_DEVICE_ID_INTEL_ICH7_0	0x27b8
+#define PCI_DEVICE_ID_INTEL_ICH7_1	0x27b9
+#define PCI_DEVICE_ID_INTEL_ICH7_2	0x27c0
+#define PCI_DEVICE_ID_INTEL_ICH7_3	0x27c1
+#define PCI_DEVICE_ID_INTEL_ICH7_30	0x27b0
+#define PCI_DEVICE_ID_INTEL_ICH7_31	0x27bd
+#define PCI_DEVICE_ID_INTEL_ICH7_5	0x27c4
+#define PCI_DEVICE_ID_INTEL_ICH7_6	0x27c5
+#define PCI_DEVICE_ID_INTEL_ICH7_7	0x27c8
+#define PCI_DEVICE_ID_INTEL_ICH7_8	0x27c9
+#define PCI_DEVICE_ID_INTEL_ICH7_9	0x27ca
+#define PCI_DEVICE_ID_INTEL_ICH7_10	0x27cb
+#define PCI_DEVICE_ID_INTEL_ICH7_11	0x27cc
+#define PCI_DEVICE_ID_INTEL_ICH7_12	0x27d0
+#define PCI_DEVICE_ID_INTEL_ICH7_13	0x27d2
+#define PCI_DEVICE_ID_INTEL_ICH7_14	0x27d4
+#define PCI_DEVICE_ID_INTEL_ICH7_15	0x27d6
+#define PCI_DEVICE_ID_INTEL_ICH7_16	0x27d8
+#define PCI_DEVICE_ID_INTEL_ICH7_17	0x27da
+#define PCI_DEVICE_ID_INTEL_ICH7_18	0x27dc
+#define PCI_DEVICE_ID_INTEL_ICH7_19	0x27dd
+#define PCI_DEVICE_ID_INTEL_ICH7_20	0x27de
+#define PCI_DEVICE_ID_INTEL_ICH7_21	0x27df
+#define PCI_DEVICE_ID_INTEL_ICH7_22	0x27e0
+#define PCI_DEVICE_ID_INTEL_ICH7_23	0x27e2
+#define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340
+#define PCI_DEVICE_ID_INTEL_ESB2_19	0x3500
+#define PCI_DEVICE_ID_INTEL_ESB2_20	0x3501
+#define PCI_DEVICE_ID_INTEL_ESB2_21	0x3504
+#define PCI_DEVICE_ID_INTEL_ESB2_22	0x3505
+#define PCI_DEVICE_ID_INTEL_ESB2_23	0x350c
+#define PCI_DEVICE_ID_INTEL_ESB2_24	0x350d
+#define PCI_DEVICE_ID_INTEL_ESB2_25	0x3510
+#define PCI_DEVICE_ID_INTEL_ESB2_26	0x3511
+#define PCI_DEVICE_ID_INTEL_ESB2_27	0x3514
+#define PCI_DEVICE_ID_INTEL_ESB2_28	0x3515
+#define PCI_DEVICE_ID_INTEL_ESB2_29	0x3518
+#define PCI_DEVICE_ID_INTEL_ESB2_30	0x3519
+#define PCI_DEVICE_ID_INTEL_82830_HB	0x3575
+#define PCI_DEVICE_ID_INTEL_82830_CGC	0x3577
+#define PCI_DEVICE_ID_INTEL_82855GM_HB	0x3580
+#define PCI_DEVICE_ID_INTEL_82855GM_IG	0x3582
+#define PCI_DEVICE_ID_INTEL_E7520_MCH	0x3590
+#define PCI_DEVICE_ID_INTEL_E7320_MCH	0x3592
+#define PCI_DEVICE_ID_INTEL_MCH_PA	0x3595
+#define PCI_DEVICE_ID_INTEL_MCH_PA1	0x3596
+#define PCI_DEVICE_ID_INTEL_MCH_PB	0x3597
+#define PCI_DEVICE_ID_INTEL_MCH_PB1	0x3598
+#define PCI_DEVICE_ID_INTEL_MCH_PC	0x3599
+#define PCI_DEVICE_ID_INTEL_MCH_PC1	0x359a
+#define PCI_DEVICE_ID_INTEL_E7525_MCH	0x359e
+#define PCI_DEVICE_ID_INTEL_80310	0x530d
+#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
+#define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
+#define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
+#define PCI_DEVICE_ID_INTEL_82437VX	0x7030
+#define PCI_DEVICE_ID_INTEL_82439TX	0x7100
+#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110
+#define PCI_DEVICE_ID_INTEL_82371AB	0x7111
+#define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
+#define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
+#define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
+#define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
+#define PCI_DEVICE_ID_INTEL_82810_MC3	0x7122
+#define PCI_DEVICE_ID_INTEL_82810_IG3	0x7123
+#define PCI_DEVICE_ID_INTEL_82810E_MC	0x7124
+#define PCI_DEVICE_ID_INTEL_82810E_IG	0x7125
+#define PCI_DEVICE_ID_INTEL_82443LX_0	0x7180
+#define PCI_DEVICE_ID_INTEL_82443LX_1	0x7181
+#define PCI_DEVICE_ID_INTEL_82443BX_0	0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_1	0x7191
+#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
+#define PCI_DEVICE_ID_INTEL_440MX	0x7195
+#define PCI_DEVICE_ID_INTEL_82443MX_0	0x7198
+#define PCI_DEVICE_ID_INTEL_82443MX_1	0x7199
+#define PCI_DEVICE_ID_INTEL_82443MX_2	0x719a
+#define PCI_DEVICE_ID_INTEL_82443MX_3	0x719b
+#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0
+#define PCI_DEVICE_ID_INTEL_82443GX_1	0x71a1
+#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2
+#define PCI_DEVICE_ID_INTEL_82372FB_0	0x7600
+#define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601
+#define PCI_DEVICE_ID_INTEL_82372FB_2	0x7602
+#define PCI_DEVICE_ID_INTEL_82372FB_3	0x7603
+#define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
+#define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
+#define PCI_DEVICE_ID_INTEL_82451NX	0x84ca
+#define PCI_DEVICE_ID_INTEL_82454NX     0x84cb
+#define PCI_DEVICE_ID_INTEL_84460GX	0x84ea
+#define PCI_DEVICE_ID_INTEL_IXP4XX	0x8500
+#define PCI_DEVICE_ID_INTEL_IXP2400	0x9001
+#define PCI_DEVICE_ID_INTEL_IXP2800	0x9004
+#define PCI_DEVICE_ID_INTEL_S21152BB	0xb152
+
+#define PCI_VENDOR_ID_COMPUTONE		0x8e0e
+#define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
+#define PCI_DEVICE_ID_COMPUTONE_PG	0x0302
+#define PCI_SUBVENDOR_ID_COMPUTONE	0x8e0e
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG4	0x0001
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG8	0x0002
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG6	0x0003
+
+#define PCI_VENDOR_ID_KTI		0x8e2e
+#define PCI_DEVICE_ID_KTI_ET32P2	0x3000
+
+#define PCI_VENDOR_ID_ADAPTEC		0x9004
+#define PCI_DEVICE_ID_ADAPTEC_7810	0x1078
+#define PCI_DEVICE_ID_ADAPTEC_7821	0x2178
+#define PCI_DEVICE_ID_ADAPTEC_38602	0x3860
+#define PCI_DEVICE_ID_ADAPTEC_7850	0x5078
+#define PCI_DEVICE_ID_ADAPTEC_7855	0x5578
+#define PCI_DEVICE_ID_ADAPTEC_5800	0x5800
+#define PCI_DEVICE_ID_ADAPTEC_3860	0x6038
+#define PCI_DEVICE_ID_ADAPTEC_1480A	0x6075
+#define PCI_DEVICE_ID_ADAPTEC_7860	0x6078
+#define PCI_DEVICE_ID_ADAPTEC_7861	0x6178
+#define PCI_DEVICE_ID_ADAPTEC_7870	0x7078
+#define PCI_DEVICE_ID_ADAPTEC_7871	0x7178
+#define PCI_DEVICE_ID_ADAPTEC_7872	0x7278
+#define PCI_DEVICE_ID_ADAPTEC_7873	0x7378
+#define PCI_DEVICE_ID_ADAPTEC_7874	0x7478
+#define PCI_DEVICE_ID_ADAPTEC_7895	0x7895
+#define PCI_DEVICE_ID_ADAPTEC_7880	0x8078
+#define PCI_DEVICE_ID_ADAPTEC_7881	0x8178
+#define PCI_DEVICE_ID_ADAPTEC_7882	0x8278
+#define PCI_DEVICE_ID_ADAPTEC_7883	0x8378
+#define PCI_DEVICE_ID_ADAPTEC_7884	0x8478
+#define PCI_DEVICE_ID_ADAPTEC_7885	0x8578
+#define PCI_DEVICE_ID_ADAPTEC_7886	0x8678
+#define PCI_DEVICE_ID_ADAPTEC_7887	0x8778
+#define PCI_DEVICE_ID_ADAPTEC_7888	0x8878
+#define PCI_DEVICE_ID_ADAPTEC_1030	0x8b78
+
+#define PCI_VENDOR_ID_ADAPTEC2		0x9005
+#define PCI_DEVICE_ID_ADAPTEC2_2940U2	0x0010
+#define PCI_DEVICE_ID_ADAPTEC2_2930U2	0x0011
+#define PCI_DEVICE_ID_ADAPTEC2_7890B	0x0013
+#define PCI_DEVICE_ID_ADAPTEC2_7890	0x001f
+#define PCI_DEVICE_ID_ADAPTEC2_3940U2	0x0050
+#define PCI_DEVICE_ID_ADAPTEC2_3950U2D	0x0051
+#define PCI_DEVICE_ID_ADAPTEC2_7896	0x005f
+#define PCI_DEVICE_ID_ADAPTEC2_7892A	0x0080
+#define PCI_DEVICE_ID_ADAPTEC2_7892B	0x0081
+#define PCI_DEVICE_ID_ADAPTEC2_7892D	0x0083
+#define PCI_DEVICE_ID_ADAPTEC2_7892P	0x008f
+#define PCI_DEVICE_ID_ADAPTEC2_7899A	0x00c0
+#define PCI_DEVICE_ID_ADAPTEC2_7899B	0x00c1
+#define PCI_DEVICE_ID_ADAPTEC2_7899D	0x00c3
+#define PCI_DEVICE_ID_ADAPTEC2_7899P	0x00cf
+#define PCI_DEVICE_ID_ADAPTEC2_SCAMP	0x0503
+
+#define PCI_VENDOR_ID_ATRONICS		0x907f
+#define PCI_DEVICE_ID_ATRONICS_2015	0x2015
+
+#define PCI_VENDOR_ID_HOLTEK		0x9412
+#define PCI_DEVICE_ID_HOLTEK_6565	0x6565
+
+#define PCI_VENDOR_ID_NETMOS		0x9710
+#define PCI_DEVICE_ID_NETMOS_9705	0x9705
+#define PCI_DEVICE_ID_NETMOS_9715	0x9715
+#define PCI_DEVICE_ID_NETMOS_9735	0x9735
+#define PCI_DEVICE_ID_NETMOS_9745	0x9745
+#define PCI_DEVICE_ID_NETMOS_9755	0x9755
+#define PCI_DEVICE_ID_NETMOS_9805	0x9805
+#define PCI_DEVICE_ID_NETMOS_9815	0x9815
+#define PCI_DEVICE_ID_NETMOS_9835	0x9835
+#define PCI_DEVICE_ID_NETMOS_9845	0x9845
+#define PCI_DEVICE_ID_NETMOS_9855	0x9855
+
+#define PCI_SUBVENDOR_ID_EXSYS		0xd84d
+#define PCI_SUBDEVICE_ID_EXSYS_4014	0x4014
+
+#define PCI_VENDOR_ID_TIGERJET		0xe159
+#define PCI_DEVICE_ID_TIGERJET_300	0x0001
+#define PCI_DEVICE_ID_TIGERJET_100	0x0002
+
+#define PCI_VENDOR_ID_TTTECH		0x0357
+#define PCI_DEVICE_ID_TTTECH_MC322	0x000A
+
+#define PCI_VENDOR_ID_ARK		0xedd8
+#define PCI_DEVICE_ID_ARK_STING		0xa091
+#define PCI_DEVICE_ID_ARK_STINGARK	0xa099
+#define PCI_DEVICE_ID_ARK_2000MT	0xa0a1
diff --git a/usb/store/host/ohci-pci/pcixbios.h b/usb/store/host/ohci-pci/pcixbios.h
new file mode 100644
index 0000000..5788130
--- /dev/null
+++ b/usb/store/host/ohci-pci/pcixbios.h
@@ -0,0 +1,342 @@
+/* TOS 4.04 Xbios PCI for the CT60 board
+*  Didier Mequignon 2005, e-mail: aniplay@wanadoo.fr
+*
+*  This library is free software; you can redistribute it and/or
+*  modify it under the terms of the GNU Lesser General Public
+*  License as published by the Free Software Foundation; either
+*  version 2.1 of the License, or (at your option) any later version.
+*
+*  This library is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+*  Lesser General Public License for more details.
+*
+*  You should have received a copy of the GNU Lesser General Public
+*  License along with this library; if not, write to the Free Software
+*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef	_OHCI_PCI_PCIXBIOS_H
+#define	_OHCI_PCI_PCIXBIOS_H
+
+#define PCIIDR                0x00   /* PCI Configuration ID Register       */
+#define PCICSR                0x04   /* PCI Command/Status Register         */
+#define PCICR                 0x04   /* PCI Command Register                */
+#define PCISR                 0x06   /* PCI Status Register                 */
+#define PCIREV                0x08   /* PCI Revision ID Register            */
+#define PCICCR                0x09   /* PCI Class Code Register             */
+#define PCICLSR               0x0C   /* PCI Cache Line Size Register        */
+#define PCILTR                0x0D   /* PCI Latency Timer Register          */
+#define PCIHTR                0x0E   /* PCI Header Type Register            */
+#define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
+#define PCIBAR0               0x10   /* PCI Base Address Register for Memory
+                                        Accesses to Local, Runtime, and DMA */
+#define PCIBAR1               0x14   /* PCI Base Address Register for I/O
+                                        Accesses to Local, Runtime, and DMA */
+#define PCIBAR2               0x18   /* PCI Base Address Register for Memory
+                                        Accesses to Local Address Space 0   */
+#define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
+                                        Accesses to Local Address Space 1   */ 
+#define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
+#define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
+#define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
+#define PCISVID               0x2C   /* PCI Subsystem Vendor ID             */
+#define PCISID                0x2E   /* PCI Subsystem ID                    */
+#define PCIERBAR              0x30   /* PCI Expansion ROM Base Register     */
+#define CAP_PTR               0x34   /* New Capability Pointer              */
+#define PCIILR                0x3C   /* PCI Interrupt Line Register         */
+#define PCIIPR                0x3D   /* PCI Interrupt Pin Register          */
+#define PCIMGR                0x3E   /* PCI Min_Gnt Register                */
+#define PCIMLR                0x3F   /* PCI Max_Lat Register                */
+#define PMCAPID               0x40   /* Power Management Capability ID      */
+#define PMNEXT                0x41   /* Power Management Next Capability
+                                        Pointer                             */
+#define PMC                   0x42   /* Power Management Capabilities       */
+#define PMCSR                 0x44   /* Power Management Control/Status     */
+#define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
+#define PMDATA                0x47   /* Power Management Data               */
+#define HS_CNTL               0x48   /* Hot Swap Control                    */
+#define HS_NEXT               0x49   /* Hot Swap Next Capability Pointer    */
+#define HS_CSR                0x4A   /* Hot Swap Control/Status             */
+#define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
+#define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
+                                        Capability Pointer                  */
+#define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
+#define PVPDATA               0x50   /* PCI VPD Data                        */
+
+typedef struct
+{
+  unsigned long *subcookie;
+  unsigned long version;
+  long routine[45];
+} PCI_COOKIE;
+
+typedef struct                       /* structure of resource descriptor    */
+{
+	unsigned short next;               /* length of the following structure   */
+	unsigned short flags;              /* type of resource and misc. flags    */
+	unsigned long start;               /* start-address of resource           */
+	unsigned long length;              /* length of resource                  */
+	unsigned long offset;              /* offset PCI to phys. CPU Address     */
+	unsigned long dmaoffset;           /* offset for DMA-transfers            */
+} PCI_RSC_DESC;
+
+typedef struct                       /* structure of address conversion     */
+{
+	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
+	unsigned long len;                 /* length of memory range              */
+} PCI_CONV_ADR;
+
+/******************************************************************************/
+/*                          PCI-BIOS Error Codes                              */
+/******************************************************************************/
+#define PCI_SUCCESSFUL            0  /* everything's fine         */
+#define PCI_FUNC_NOT_SUPPORTED   -2  /* function not supported    */
+#define PCI_BAD_VENDOR_ID        -3  /* wrong Vendor ID           */
+#define PCI_DEVICE_NOT_FOUND     -4  /* PCI-Device not found      */
+#define PCI_BAD_REGISTER_NUMBER  -5  /* wrong register number     */
+#define PCI_SET_FAILED           -6  /* reserved for later use    */
+#define PCI_BUFFER_TOO_SMALL     -7  /* reserved for later use    */
+#define PCI_GENERAL_ERROR        -8  /* general BIOS error code   */
+#define PCI_BAD_HANDLE           -9  /* wrong/unknown PCI-handle  */
+
+/******************************************************************************/
+/*                      Flags used in Resource-Descriptor                     */
+/******************************************************************************/
+#define FLG_IO        0x4000         /* Ressource in IO range               */
+#define FLG_LAST      0x8000         /* last ressource                      */
+#define FLG_8BIT      0x0100         /* 8 bit accesses allowed              */
+#define FLG_16BIT     0x0200         /* 16 bit accesses allowed             */
+#define FLG_32BIT     0x0400         /* 32 bit accesses allowed             */
+#define FLG_ENDMASK   0x000F         /* mask for byte ordering              */
+
+/******************************************************************************/
+/*                 Values used in FLG_ENDMASK for Byte Ordering               */
+/******************************************************************************/
+#define ORD_MOTOROLA       0         /* Motorola (big endian)               */
+#define ORD_INTEL_AS       1         /* Intel (little endian), addr.swapped */
+#define ORD_INTEL_LS       2         /* Intel (little endian), lane swapped */
+#define ORD_UNKNOWN       15         /* unknown (BIOS-calls allowed only)   */
+
+/******************************************************************************/
+/*                   Status Info used in Device-Descriptor                    */
+/******************************************************************************/
+#define DEVICE_FREE        0         /* Device is not used                  */
+#define DEVICE_USED        1         /* Device is used by another driver    */
+#define DEVICE_CALLBACK    2         /* used, but driver can be cancelled   */
+#define DEVICE_AVAILABLE   3         /* used, not available                 */
+#define NO_DEVICE         -1         /* no device detected                  */
+
+/******************************************************************************/
+/*                            Callback-Routine                                */
+/******************************************************************************/
+ #define GET_DRIVER_ID      0        /* CB-Routine 0: Get Driver ID         */
+ #define REMOVE_DRIVER      1        /* CB-Routine 1: Remove Driver         */
+
+/******************************************************************************/
+/*                              Functions                                     */
+/******************************************************************************/
+//#ifndef OSBIND_CLOBBER_LIST
+//#define OSBIND_CLOBBER_LIST
+//#endif
+
+#ifndef trap_14_wlw
+#define trap_14_wlw(n, a, b)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	\
+	__asm__ volatile (	\
+		"movw	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(8),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wll
+#define trap_14_wll(n, a, b)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long _a = (long) (a);	\
+	long _b = (long) (b);	\
+	\
+	__asm__ volatile (	\
+		"movl	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(10),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlww
+#define trap_14_wlww(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	short  _c = (short) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movw	%3,sp@-\n\t"	\
+		"movw	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(10),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlwl
+#define trap_14_wlwl(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	long  _c = (long) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movw	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(12),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlll
+#define trap_14_wlll(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	long  _b = (long) (b);	\
+	long  _c = (long) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movl	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(14),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+
+#define find_pci_device(id,index) (long)trap_14_wlw((short)(300),(unsigned long)(id),(unsigned short)(index))
+#define find_pci_classcode(classcode,index) (long)trap_14_wlw((short)(301),(unsigned long)(classcode),(unsigned short)(index))
+#define read_config_byte(handle,reg,address) (long)trap_14_wlwl((short)(302),(long)(handle),(unsigned short)(reg),(unsigned char *)(address))
+#define read_config_word(handle,reg,address) (long)trap_14_wlwl((short)(303),(long)(handle),(unsigned short)(reg),(unsigned short *)(address))
+#define read_config_longword(handle,reg,address) (long)trap_14_wlwl((short)(304),(long)(handle),(unsigned short)(reg),(unsigned long *)(address))
+#define fast_read_config_byte(handle,reg) (unsigned char)trap_14_wlw((short)(305),(long)(handle),(unsigned short)(reg))
+#define fast_read_config_word(handle,reg) (unsigned short)trap_14_wlw((short)(306),(long)(handle),(unsigned short)(reg))
+#define fast_read_config_longword(handle,reg) (unsigned long)trap_14_wlw((short)(307),(long)(handle),(unsigned short)(reg))
+#define write_config_byte(handle,reg,data) (long)trap_14_wlww((short)(308),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
+#define write_config_word(handle,reg,data) (long)trap_14_wlww((short)(309),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
+#define write_config_longword(handle,reg,data) (long)trap_14_wlwl((short)(310),(long)(handle),(unsigned short)(reg),(unsigned long)(data))
+#define hook_interrupt(handle,routine,parameter) (long)trap_14_wlll((short)(311),(long)(handle),(unsigned long *)(routine),(unsigned long *)(parameter))
+#define unhook_interrupt(handle) (long)trap_14_wl((short)(312),(long)(handle))
+#define special_cycle(bus_number,special_cycle) (long)trap_14_wwl((short)(313),(unsigned short)(bus_number),(unsigned long)(special_cycle))
+#define get_routing(handle) (long)trap_14_wl((short)(314),(long)(handle))
+#define set_interrupt(handle,mode) (long)trap_14_wlw((short)(315),(long)(handle),(short)(mode))
+#define get_resource(handle) (long)trap_14_wl((short)(316),(long)(handle))
+#define get_card_used(handle,callback) (long)trap_14_wll((short)(317),(long)(handle),(long *)(address))
+#define set_card_used(handle,callback) (long)trap_14_wll((short)(318),(long)(handle),(long *)(callback))
+#define read_mem_byte(handle,offset,address) (long)trap_14_wlll((short)(319),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
+#define read_mem_word(handle,offset,address) (long)trap_14_wlll((short)(320),(unsigned long)(offset),(unsigned short *)(address))
+#define read_mem_longword(handle,offset,address) (long)trap_14_wlll((short)(321),(unsigned long)(offset),(unsigned long *)(address))
+#define fast_read_mem_byte(handle,offset) (unsigned char)trap_14_wll((short)(322),(long)(handle),(unsigned long)(offset))
+#define fast_read_mem_word(handle,offset) (unsigned short)trap_14_wll((short)(323),(long)(handle),(unsigned long)(offset))
+#define fast_read_mem_longword(handle,offset) (unsigned long)trap_14_wll((short)(324),(long)(handle),(unsigned long)(offset))
+#define write_mem_byte(handle,offset,data) (long)trap_14_wllw((short)(325),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_mem_word(handle,offset,data) (long)trap_14_wllw((short)(326),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_mem_longword(handle,offset,data) (long)trap_14_wlll((short)(327),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
+#define read_io_byte(handle,offset,address) (long)trap_14_wlll((short)(328),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
+#define read_io_word(handle,offset,address) (long)trap_14_wlll((short)(329),(long)(handle),(unsigned long)(offset),(unsigned short *)(address))
+#define read_io_longword(handle,offset,address) (long)trap_14_wlll((short)(330),(long)(handle),(unsigned long)(offset),(unsigned long *)(address))
+#define fast_read_io_byte(handle,offset) (unsigned char)trap_14_wll((short)(331),(long)(handle),(unsigned long)(offset))
+#define fast_read_io_word(handle,offset) (unsigned short)trap_14_wll((short)(332),(long)(handle),(unsigned long)(offset))
+#define fast_read_io_longword(handle,offset) (unsigned long)trap_14_wll((short)(333),(long)(handle),(unsigned long)(offset))
+#define write_io_byte(handle,offset,data) (long)trap_14_wllw((short)(334),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_io_word(handle,offset,data) (long)trap_14_wllw((short)(335),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_io_longword(handle,offset,data) (long)trap_14_wlll((short)(336),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
+#define get_machine_id() (long)trap_14_w((short)(337))
+#define get_pagesize() (long)trap_14_w((short)(338))
+#define virt_to_bus(handle,address,pointer) (long)trap_14_wlll((short)(339),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
+#define bus_to_virt(handle,address,pointer) (long)trap_14_wlll((short)(340),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
+#define virt_to_phys(address,pointer) (long)trap_14_wll((short)(341),(unsigned long)(address),(unsigned long *)(pointer))
+#define phys_to_virt(address,pointer) (long)trap_14_wll((short)(342),(unsigned long)(address),(unsigned long *)(pointer))
+#define dma_setbuffer(pci_address,local_address,size) (long)trap_14_wlll((short)(350),(unsigned long)(pci_address),(unsigned long)(local_address),(unsigned long)(size))
+#define dma_buffoper(mode) (long)trap_14_ww((short)(351),(short)(mode))
+#define read_mailbox(mailbox,pointer)  (long)trap_14_wwl((short)(352),(short)(mailbox),(unsigned long *)(pointer))
+#define write_mailbox(mailbox,data) (long)trap_14_wwl((short)(353),(short)(mailbox),(unsigned long)(data))
+
+extern long Find_pci_device(unsigned long id, unsigned short index);
+extern long Find_pci_classcode(unsigned long class, unsigned short index);
+extern long Read_config_byte(long handle, unsigned short reg, unsigned char *address);
+extern long Read_config_word(long handle, unsigned short reg, unsigned short *address);
+extern long Read_config_longword(long handle, unsigned short reg, unsigned long *address);
+extern unsigned char Fast_read_config_byte(long handle, unsigned short reg);
+extern unsigned short Fast_read_config_word(long handle, unsigned short reg);
+extern unsigned long Fast_read_config_longword(long handle, unsigned short reg);
+extern long Write_config_byte(long handle, unsigned short reg, unsigned short val);
+extern long Write_config_word(long handle, unsigned short reg, unsigned short val);
+extern long Write_config_longword(long handle, unsigned short reg, unsigned long val);
+extern long Hook_interrupt(long handle, unsigned long *routine, unsigned long *parameter);
+extern long Unhook_interrupt(long handle);
+extern long Special_cycle(unsigned short bus, unsigned long data);
+extern long Get_routing(long handle);
+extern long Set_interrupt(long handle);
+extern long Get_resource(long handle);
+extern long Get_card_used(long handle, unsigned long *address);
+extern long Set_card_used(long handle, unsigned long *callback);
+extern long Read_mem_byte(long handle, unsigned long offset, unsigned char *address);
+extern long Read_mem_word(long handle, unsigned long offset, unsigned short *address);
+extern long Read_mem_longword(long handle, unsigned long offset, unsigned long *address);
+extern unsigned char Fast_read_mem_byte(long handle, unsigned long offset);
+extern unsigned short Fast_read_mem_word(long handle, unsigned long offset);
+extern unsigned long Fast_read_mem_longword(long handle, unsigned long offset);
+extern long Write_mem_byte(long handle, unsigned long offset, unsigned short val);
+extern long Write_mem_word(long handle, unsigned long offset, unsigned short val);
+extern long Write_mem_longword(long handle, unsigned long offset, unsigned long val);
+extern long Read_io_byte(long handle, unsigned long offset, unsigned char *address);
+extern long Read_io_word(long handle, unsigned long offset, unsigned short *address);
+extern long Read_io_longword(long handle, unsigned long offset, unsigned long *address);
+extern unsigned char Fast_read_io_byte(long handle, unsigned long offset);
+extern unsigned short Fast_read_io_word(long handle, unsigned long offset);
+extern unsigned long Fast_read_io_longword(long handle, unsigned long offset);
+extern long Write_io_byte(long handle, unsigned long offset, unsigned short val);
+extern long Write_io_word(long handle, unsigned long offset, unsigned short val);
+extern long Write_io_longword(long handle, unsigned long offset, unsigned long val);
+extern long Get_machine_id(void);
+extern long Get_pagesize(void);
+extern long Virt_to_bus(long handle, unsigned long address, PCI_CONV_ADR *pointer);
+extern long Bus_to_virt(long handle, unsigned long address, PCI_CONV_ADR *pointer);
+extern long Virt_to_phys(unsigned long address, PCI_CONV_ADR *pointer);
+extern long Phys_to_virt(unsigned long address, PCI_CONV_ADR *pointer);
+
+#endif
diff --git a/usb/store/main.c b/usb/store/main.c
new file mode 100644
index 0000000..32d7f4b
--- /dev/null
+++ b/usb/store/main.c
@@ -0,0 +1,206 @@
+/* 
+ * David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ * PCI code taken from FireTos by Didier Mequignon
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include "config.h"
+#include "usb.h"
+#include "super.h"
+#include "debug.h"
+#ifdef PCI_XBIOS
+#include "host/ohci-pci/pci_ids.h"
+#include "host/ohci-pci/pcixbios.h"
+#endif
+#include <mint/basepage.h>
+#include <mint/cookie.h>
+
+extern long install_usb_stor(int dev_num, unsigned long part_type, 
+			     unsigned long part_offset, unsigned long part_size, 
+			     char *vendor, char *revision, char *product);
+extern int do_usb(int argc, char **argv);
+extern unsigned long _PgmSize;
+extern long __mint;
+#ifdef PCI_XBIOS
+extern struct pci_device_id usb_pci_table[]; /* ohci-hcd.c */
+#endif
+
+int usb_stor_curr_dev;
+unsigned long usb_1st_disk_drive;
+short max_logical_drive;
+
+#ifdef PCI_XBIOS
+short pci_init(void)
+{
+/* PCI devices detection */ 
+	struct pci_device_id *board;
+	long handle;
+	short usb_found;
+
+	short idx;
+	long err;
+	unsigned long class;
+		
+	usb_found = 0;
+	idx = 0;
+	do {
+		handle = find_pci_device(0x0000FFFFL, idx++);
+printf("idx %d PCI handle: %lx\n", idx -1, handle); /* Galvez: Debug */
+		if(handle >= 0)	{
+			unsigned long id = 0;
+			err = read_config_longword(handle, PCIIDR, &id);
+
+			if((err >= 0) && !usb_found) {
+				if(read_config_longword(handle, PCIREV, &class) >= 0
+					&& ((class >> 16) == PCI_CLASS_SERIAL_USB)) {	
+					if((class >> 8) == PCI_CLASS_SERIAL_USB_UHCI)
+						(void) Cconws("UHCI USB controller found\r\n");
+					else if((class >> 8) == PCI_CLASS_SERIAL_USB_OHCI) {
+						(void) Cconws("OHCI USB controller found\r\n");
+#ifdef CONFIG_USB_OHCI
+						board = usb_pci_table; /* compare table */
+						while(board->vendor) {
+							if((board->vendor == (id & 0xFFFF))
+				 				&& (board->device == (id >> 16))) {
+								if(usb_init(handle, board) >= 0)
+									usb_found = 1;
+								break;
+							}
+							board++;
+						}
+#endif /* CONFIG_USB_OHCI */
+					}
+					else if((class >> 8) == PCI_CLASS_SERIAL_USB_EHCI)
+						(void) Cconws("EHCI USB controller found\r\n");
+				}
+			}
+		}    
+	}
+	while(handle >= 0);
+	return usb_found;
+}
+#endif /* PCI_XBIOS */
+
+int main(int argc, char **argv)
+{
+#ifdef CONFIG_USB_STORAGE			
+	long p = 0;
+	int r;
+
+	if (__mint)
+		max_logical_drive = 24;
+	else max_logical_drive = 16;
+
+	if (argc == 1) {
+		short usb_found = 0;
+	
+		usb_stor_curr_dev = -1;
+		usb_1st_disk_drive = 0;
+
+		usb_stop();
+#ifdef PCI_XBIOS
+		usb_found = pci_init();	
+#else
+		if (usb_init() >= 0)
+			usb_found = 1;
+#endif /* PCI_XBIOS */
+		if (usb_found) {
+			/* Scan and get info from all the storage devices found */
+			usb_stor_curr_dev = usb_stor_scan();
+			/* it doesn't really return current device *
+			 * only 0 if it has found any store device *
+			 * -1 otherwise				   */
+			if (usb_stor_curr_dev != -1) {
+				int dev_num = usb_stor_curr_dev;
+				block_dev_desc_t *stor_dev;
+	
+				while ((stor_dev = usb_stor_get_dev(dev_num)) != NULL) {
+					int part_num = 1;
+					unsigned long part_type, part_offset, part_size;
+					/* Now find partitions in this storage device */	
+					while (!fat_register_device(stor_dev, part_num, &part_type, 
+								    &part_offset, &part_size)) {
+		 				if (!(Super(SUP_INQUIRE))) {
+							p = SuperFromUser ();
+						}
+
+						/* install partition */
+						r = install_usb_stor(dev_num, part_type, part_offset, 
+								     part_size, stor_dev->vendor, 
+								     stor_dev->revision, stor_dev->product);
+						if (r == -1)
+							printf("unable to install storage device\n");		
+
+						if (p)
+							SuperToUser(p);
+						
+						part_num++;
+					}	
+					dev_num++;
+				}
+			
+			}
+#if 0			
+			long *drvbits;
+			long value;
+
+			p = SuperFromUser();
+					
+			drvbits =  0x000004c2;
+						
+			value = *drvbits;
+			printf("\ndrvbits: %x \n", (unsigned)value);
+			SuperToUser(p);	
+#endif		
+
+		}
+		
+		if (!__mint) {	
+			printf(" Press any key");
+			Bconin(DEV_CONSOLE);
+		}	
+		Ptermres( _PgmSize, 0);	
+	}
+#endif	/* CONFIG_USB_STORAGE */
+
+	if (strncmp(argv[1], "tree", 4) == 0) {
+		argc = 2;
+		argv[1] = "start";
+		do_usb(argc, argv);
+
+		argv[1] = "inf";
+		do_usb(argc, argv);
+
+		argv[1] = "tree";
+		do_usb(argc, argv);
+	
+		argv[1] = "storage";
+		do_usb(argc, argv);
+
+//		argc = 3;
+//		argv[1] = "dev";
+//		argv[2] = "0";
+//		do_usb(argc, argv);
+
+//		argc = 2;
+		argv[1] = "stop";
+		do_usb (argc, argv);
+
+		printf(" Press any key\r\n");
+		Bconin(DEV_CONSOLE);
+	}	
+	return 0;	
+}
diff --git a/usb/store/makefile b/usb/store/makefile
new file mode 100644
index 0000000..2164391
--- /dev/null
+++ b/usb/store/makefile
@@ -0,0 +1,85 @@
+
+ifeq ($(CROSS),yes)
+CC			= m68k-atari-mint-gcc
+STRIP			= m68k-atari-mint-strip
+STACK			= m68k-atari-mint-stack
+INCLUDE_GEM_PATH	= /usr/local/cross-mint/m68k-atari-mint/include
+LIB_GEM_PATH		= /usr/local/cross-mint/m68k-atari-mint/lib
+else
+CC			= gcc
+STRIP			= /usr/bin/strip
+STACK			= stack
+COMPRESS		= upx
+INCLUDE_GEM_PATH	= /usr/GEM/include
+LIB_GEM_PATH		= /usr/GEM/lib
+endif
+
+
+ifeq ($(MAKECMDGOALS), aranym)
+HCD_S			= ./host/aranym/natfeat_asm.S
+HCD_C			= ./host/aranym/aranym-hcd.c ./host/aranym/natfeat.c
+HCD_H			= ./host/aranym/nf_ops.h ./host/aranym/usbhost_nfapi.h
+PROGRAM			= stor_ara.tos
+endif
+ifeq ($(MAKECMDGOALS), netusbee)
+HCD_C			= ./host/netusbee/isp116x-hcd.c
+HCD_H			= ./host/netusbee/isp116x.h
+PROGRAM			= stor_ntu.tos
+endif
+ifeq ($(MAKECMDGOALS), ethernat)
+HCD_C			= ./host/ethernat/isp116x-hcd.c
+HCD_H			= ./host/ethernat/isp116x.h
+PROGRAM 		= stor_etn.tos
+endif
+ifeq ($(MAKECMDGOALS), ohci-pci)
+HCD_C			= ./host/ohci-pci/ohci-hcd.c ./host/ohci-pci/ltoa.c
+HCD_H			= ./host/ohci-pci/ohci.h ./host/ohci-pci/pcixbios.h
+DEFS			= -DPCI_XBIOS
+PROGRAM 		= stor_pci.tos
+endif
+
+STACKSIZE		= 64k
+OPTIMISATION		= -O -fomit-frame-pointer
+CPU			= -m68020-60
+LIB			= 
+ASFLAGS			= $(CPU)
+CFLAGS			= $(CPU) $(OPTIMISATION) -Wall -Wshadow -I$(INCLUDE_GEM_PATH) $(DEFS) -g
+LFLAGS			= -L$(LIB_GEM_PATH)
+COBJS 			= main.c udelay.c cmd_usb.c usb.c usb_mem.c usb_storage.c debug.c $(HCD_C)
+SOBJS 			= debug2.S bios.S $(HCD_S)
+HSRC			= config.h debug.h part.h scsi.h super.h usb.h usb_defs.h vars.h $(HCD_H)
+COBJECTS 		= $(COBJS:.c=.o)
+SOBJECTS 		= $(SOBJS:.S=.o)
+
+all:
+	make ethernat
+	make netusbee
+	make aranym
+	rm -f *.o
+	make ohci-pci
+	
+ethernat: $(PROGRAM)
+	
+aranym: $(PROGRAM)
+	
+netusbee: $(PROGRAM)
+
+ohci-pci: $(PROGRAM)
+	
+$(PROGRAM): $(COBJECTS) $(SOBJECTS) $(HSRC)
+	$(CC) -o $@ $(COBJECTS) $(SOBJECTS)
+
+strip:
+	$(STRIP) $(PROGRAM)
+
+stack:
+	$(STACK) -S $(STACKSIZE) $(PROGRAM)
+
+compress:
+	$(COMPRESS) $(PROGRAM)
+	
+clean:
+	rm -f *.tos *.log
+	find ./ -type f -name "*.o" -exec rm -f {} \;
+
+
diff --git a/usb/store/part.h b/usb/store/part.h
new file mode 100644
index 0000000..96ae888
--- /dev/null
+++ b/usb/store/part.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PART_H
+#define _PART_H
+
+typedef unsigned long long uint64_t;
+typedef unsigned long lbaint_t;
+
+typedef struct block_dev_desc {
+	int		if_type;	/* type of the interface */
+	int		dev;		/* device number */
+	unsigned char	part_type;	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
+#endif
+	lbaint_t		lba;		/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	char		vendor [40+1];	/* IDE model, SCSI Vendor */
+	char		product[20+1];	/* IDE Serial no, SCSI product */
+	char		revision[8+1];	/* firmware revision */
+	unsigned long	(*block_read)(int dev, unsigned long start, lbaint_t blkcnt, void *buffer);
+	unsigned long	(*block_write)(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer);
+	void		*priv;		/* driver private struct pointer */
+}block_dev_desc_t;
+
+/* Interface types: */
+#define IF_TYPE_UNKNOWN		0
+#define IF_TYPE_IDE		1
+#define IF_TYPE_SCSI		2
+#define IF_TYPE_ATAPI		3
+#define IF_TYPE_USB		4
+#define IF_TYPE_DOC		5
+#define IF_TYPE_MMC		6
+#define IF_TYPE_SD		7
+#define IF_TYPE_SATA		8
+
+/* Part types */
+#define PART_TYPE_UNKNOWN	0x00
+#define PART_TYPE_MAC		0x01
+#define PART_TYPE_DOS		0x02
+#define PART_TYPE_ISO		0x03
+#define PART_TYPE_AMIGA		0x04
+#define PART_TYPE_EFI		0x05
+
+/*
+ * Type string for U-Boot bootable partitions
+ */
+#define BOOT_PART_TYPE	"U-Boot"	/* primary boot partition type	*/
+#define BOOT_PART_COMP	"PPCBoot"	/* PPCBoot compatibility type	*/
+
+/* device types */
+#define DEV_TYPE_UNKNOWN	0xff	/* not connected */
+#define DEV_TYPE_HARDDISK	0x00	/* harddisk */
+#define DEV_TYPE_TAPE		0x01	/* Tape */
+#define DEV_TYPE_CDROM		0x05	/* CD-ROM */
+#define DEV_TYPE_OPDISK		0x07	/* optical disk */
+
+void print_part(block_dev_desc_t *dev_desc);
+void init_part(block_dev_desc_t *dev_desc);
+void dev_print(block_dev_desc_t *dev_desc);
+
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no, unsigned long *part_type, unsigned long *part_offset, unsigned long *part_size);
+
+#endif /* _PART_H */
diff --git a/usb/store/readme.txt b/usb/store/readme.txt
new file mode 100644
index 0000000..a1de9ad
--- /dev/null
+++ b/usb/store/readme.txt
@@ -0,0 +1,68 @@
+This application allows you to mount an USB mass storage device though 
+the Ethernat hardware or the Aranym USB Natfeat, read or copy files from/to this device.
+It's derived from the work done by Didier Mequignon for FireTOS.
+
+This is still quite experimental so i am not responsable for any data loss
+or corruption, play with it at your own risk. Please backup your data ;-)
+
+**** Binaries ****
+
+stor_etn.tos ---> EtherNat
+stor_ara.tos ---> Aranym
+stor_ntu.tos ---> NetUSBee
+stor_pci.tos ---> PCI-OHCI
+
+Note that NetUSBee and PCI-OHCI don't work yet
+
+**** How it works *****
+
+Depending on your hardware run stor_etn.tos or stor_ara.tos application from your desktop,
+if everything goes well you can use the "install partition" option in your desktop menu to 
+access the new partitions.
+
+It has been tested it under CT060 TOS and MiNT 1.16.3.
+Teted in Aranym with MiNT 1.17.0 beta and TOS 4.04.
+
+**** Limits/Problems *****
+
+- The supported partitions are the supported partitions by the OS.
+It has been tested with FAT16 in TOS4.04, with FAT16, FAT32 and ext2 with MiNT.
+
+- There is still no handle for mounting/unmounting partitions. Neither detection for
+devices already plugged, so when you mount one device you can't unmount it.
+If you run the application several times with the same USB stick plugged, it
+will mount the device again as a new different logical partition.
+
+- It's VERY VERY slow, for now the transfer rate it's quite ridiculous. I hope
+to solve this soon. Under Aranym it can be better.
+
+- I don't think that it works together with umouse from Jan Thomas.
+
+- This is only a start don't expect too much.
+
+- Thing desktop crashes when inquiring to show info about the device.
+
+For feedback, suggestions or tips mail me at dgalvez75@gmail.com
+
+**** Histoy ****
+* 5/10/2010 (alfa 05)
+ - XHDI working (assembler version).
+ - Under MiNT FAT32 and ext2 partitions can be accesed.
+ - Introduced NetUSBee sources (not working yet)
+ - Introduced OHCI-PCI sources (to be tested)
+* 27/8/2010 (alfa 04)
+ - Start XHDI translation to C.
+ - Support for Aranym HCD.
+* 19/5/2010 (alfa 03)
+ - Killed a bug that could produce some corruption in the pun_info struct.
+* 26/4/2010 (alfa 02) 
+ - Under MiNT if the number of partitions was greater than 16, the driver wasn't installed.
+ - Wait for a key pess before retuning the desktop under TOS when driver is loaded.
+ - Resolved big bug that produced that data written/read above the first 16 MB to be corrupted.
+* 1/3/2010 (alfa 01)
+ - Initial release 
+
+David Galvez 	05/10/2010
+Version: alfa 05
+ 
+
diff --git a/usb/store/scsi.h b/usb/store/scsi.h
new file mode 100644
index 0000000..a42c0a3
--- /dev/null
+++ b/usb/store/scsi.h
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ #ifndef _SCSI_H
+ #define _SCSI_H
+
+typedef struct SCSI_cmd_block{
+	unsigned char		cmd[16];					/* command				   */
+	unsigned char		sense_buf[64];		/* for request sense */
+	unsigned char		status;						/* SCSI Status			 */
+	unsigned char		target;						/* Target ID				 */
+	unsigned char		lun;							/* Target LUN        */
+	unsigned char		cmdlen;						/* command len				*/
+	unsigned long		datalen;					/* Total data length	*/
+	unsigned char	*	pdata;						/* pointer to data		*/
+	unsigned char		msgout[12];				/* Messge out buffer (NOT USED) */
+	unsigned char		msgin[12];				/* Message in buffer	*/
+	unsigned char		sensecmdlen;			/* Sense command len	*/
+	unsigned long		sensedatalen;			/* Sense data len			*/
+	unsigned char		sensecmd[6];			/* Sense command			*/
+	unsigned long		contr_stat;				/* Controller Status	*/
+	unsigned long		trans_bytes;			/* tranfered bytes		*/
+
+	unsigned int		priv;
+}ccb;
+
+/*-----------------------------------------------------------
+**
+**	SCSI  constants.
+**
+**-----------------------------------------------------------
+*/
+
+/*
+**	Messages
+*/
+
+#define	M_COMPLETE	(0x00)
+#define	M_EXTENDED	(0x01)
+#define	M_SAVE_DP	(0x02)
+#define	M_RESTORE_DP	(0x03)
+#define	M_DISCONNECT	(0x04)
+#define	M_ID_ERROR	(0x05)
+#define	M_ABORT		(0x06)
+#define	M_REJECT	(0x07)
+#define	M_NOOP		(0x08)
+#define	M_PARITY	(0x09)
+#define	M_LCOMPLETE	(0x0a)
+#define	M_FCOMPLETE	(0x0b)
+#define	M_RESET		(0x0c)
+#define	M_ABORT_TAG	(0x0d)
+#define	M_CLEAR_QUEUE	(0x0e)
+#define	M_INIT_REC	(0x0f)
+#define	M_REL_REC	(0x10)
+#define	M_TERMINATE	(0x11)
+#define	M_SIMPLE_TAG	(0x20)
+#define	M_HEAD_TAG	(0x21)
+#define	M_ORDERED_TAG	(0x22)
+#define	M_IGN_RESIDUE	(0x23)
+#define	M_IDENTIFY	(0x80)
+
+#define	M_X_MODIFY_DP	(0x00)
+#define	M_X_SYNC_REQ	(0x01)
+#define	M_X_WIDE_REQ	(0x03)
+#define	M_X_PPR_REQ	(0x04)
+
+
+/*
+**	Status
+*/
+
+#define	S_GOOD		(0x00)
+#define	S_CHECK_COND	(0x02)
+#define	S_COND_MET	(0x04)
+#define	S_BUSY		(0x08)
+#define	S_INT		(0x10)
+#define	S_INT_COND_MET	(0x14)
+#define	S_CONFLICT	(0x18)
+#define	S_TERMINATED	(0x20)
+#define	S_QUEUE_FULL	(0x28)
+#define	S_ILLEGAL	(0xff)
+#define	S_SENSE		(0x80)
+
+/*
+ * Sense_keys
+ */
+
+#define SENSE_NO_SENSE				0x0
+#define SENSE_RECOVERED_ERROR	0x1
+#define SENSE_NOT_READY				0x2
+#define SENSE_MEDIUM_ERROR		0x3
+#define SENSE_HARDWARE_ERROR	0x4
+#define SENSE_ILLEGAL_REQUEST	0x5
+#define SENSE_UNIT_ATTENTION	0x6
+#define SENSE_DATA_PROTECT		0x7
+#define SENSE_BLANK_CHECK			0x8
+#define SENSE_VENDOR_SPECIFIC	0x9
+#define SENSE_COPY_ABORTED		0xA
+#define SENSE_ABORTED_COMMAND	0xB
+#define SENSE_VOLUME_OVERFLOW	0xD
+#define SENSE_MISCOMPARE			0xE
+
+
+#define SCSI_CHANGE_DEF	0x40		/* Change Definition (Optional) */
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_COPY			0x18		/* Copy (O) */
+#define SCSI_COP_VERIFY	0x3A		/* Copy and Verify (O) */
+#define SCSI_INQUIRY		0x12		/* Inquiry (MANDATORY) */
+#define SCSI_LOG_SELECT	0x4C		/* Log Select (O) */
+#define SCSI_LOG_SENSE	0x4D		/* Log Sense (O) */
+#define SCSI_MODE_SEL6	0x15		/* Mode Select 6-byte (Device Specific) */
+#define SCSI_MODE_SEL10	0x55		/* Mode Select 10-byte (Device Specific) */
+#define SCSI_MODE_SEN6	0x1A		/* Mode Sense 6-byte (Device Specific) */
+#define SCSI_MODE_SEN10	0x5A		/* Mode Sense 10-byte (Device Specific) */
+#define SCSI_READ_BUFF	0x3C		/* Read Buffer (O) */
+#define SCSI_REQ_SENSE	0x03		/* Request Sense (MANDATORY) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostic (O) */
+#define SCSI_TST_U_RDY	0x00		/* Test Unit Ready (MANDATORY) */
+#define SCSI_WRITE_BUFF	0x3B		/* Write Buffer (O) */
+/***************************************************************************
+ *			  %%% Commands Unique to Direct Access Devices %%%
+ ***************************************************************************/
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_FORMAT		0x04		/* Format Unit (MANDATORY) */
+#define SCSI_LCK_UN_CAC	0x36		/* Lock Unlock Cache (O) */
+#define SCSI_PREFETCH	0x34		/* Prefetch (O) */
+#define SCSI_MED_REMOVL	0x1E		/* Prevent/Allow medium Removal (O) */
+#define SCSI_READ6		0x08		/* Read 6-byte (MANDATORY) */
+#define SCSI_READ10		0x28		/* Read 10-byte (MANDATORY) */
+#define SCSI_RD_CAPAC	0x25		/* Read Capacity (MANDATORY) */
+#define SCSI_RD_DEFECT	0x37		/* Read Defect Data (O) */
+#define SCSI_READ_LONG	0x3E		/* Read Long (O) */
+#define SCSI_REASS_BLK	0x07		/* Reassign Blocks (O) */
+#define SCSI_RCV_DIAG	0x1C		/* Receive Diagnostic Results (O) */
+#define SCSI_RELEASE	0x17		/* Release Unit (MANDATORY) */
+#define SCSI_REZERO		0x01		/* Rezero Unit (O) */
+#define SCSI_SRCH_DAT_E	0x31		/* Search Data Equal (O) */
+#define SCSI_SRCH_DAT_H	0x30		/* Search Data High (O) */
+#define SCSI_SRCH_DAT_L	0x32		/* Search Data Low (O) */
+#define SCSI_SEEK6		0x0B		/* Seek 6-Byte (O) */
+#define SCSI_SEEK10		0x2B		/* Seek 10-Byte (O) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostics (MANDATORY) */
+#define SCSI_SET_LIMIT	0x33		/* Set Limits (O) */
+#define SCSI_START_STP	0x1B		/* Start/Stop Unit (O) */
+#define SCSI_SYNC_CACHE	0x35		/* Synchronize Cache (O) */
+#define SCSI_VERIFY		0x2F		/* Verify (O) */
+#define SCSI_WRITE6		0x0A		/* Write 6-Byte (MANDATORY) */
+#define SCSI_WRITE10	0x2A		/* Write 10-Byte (MANDATORY) */
+#define SCSI_WRT_VERIFY	0x2E		/* Write and Verify (O) */
+#define SCSI_WRITE_LONG	0x3F		/* Write Long (O) */
+#define SCSI_WRITE_SAME	0x41		/* Write Same (O) */
+
+#if 0
+/****************************************************************************
+ * decleration of functions which have to reside in the LowLevel Part Driver
+ */
+
+void scsi_print_error(ccb *pccb);
+int scsi_exec(ccb *pccb);
+void scsi_bus_reset(void);
+void scsi_low_level_init(int busdevfunc);
+
+
+/***************************************************************************
+ * functions residing inside cmd_scsi.c
+ */
+void scsi_init(void);
+
+#endif
+
+#define SCSI_IDENTIFY					0xC0  /* not used */
+
+/* Hardware errors  */
+#define SCSI_SEL_TIME_OUT			 0x00000101	 /* Selection time out */
+#define SCSI_HNS_TIME_OUT			 0x00000102  /* Handshake */
+#define SCSI_MA_TIME_OUT			 0x00000103  /* Phase error */
+#define SCSI_UNEXP_DIS				 0x00000104  /* unexpected disconnect */
+
+#define SCSI_INT_STATE				 0x00010000  /* unknown Interrupt number is stored in 16 LSB */
+
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif /* _SCSI_H */
diff --git a/usb/store/super.h b/usb/store/super.h
new file mode 100644
index 0000000..017beb9
--- /dev/null
+++ b/usb/store/super.h
@@ -0,0 +1,58 @@
+/*
+ * super.h 
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _SUPER_H
+#define _SUPER_H
+
+static inline
+long SuperFromUser()
+{
+	register long retvalue __asm__("d0");
+
+	__asm__ volatile
+	(
+		"clr.l -(%%sp)\n\t"
+		"move.w #0x20,-(%%sp)\n\t"
+		"trap #1\n\t"
+		"addq.l #6,%%sp"
+		: "=r"(retvalue)				/* outputs */
+	:							/* inputs  */
+	: "d1", "d2", "a0", "a1", "a2"	/* clobbered regs */
+	);
+
+	return retvalue;
+}
+
+static inline
+void SuperToUser(long ssp)
+{
+	register long spbackup;
+
+	__asm__ volatile
+	(
+		"move.l sp,%0\n\t"
+		"move.l %1,-(%%sp)\n\t"
+		"move.w #0x20,-(%%sp)\n\t"
+		"trap #1\n\t"
+		"move.l %0,sp"
+	: "=&r"(spbackup)						/* outputs */
+	: "g"(ssp)							/* inputs  */
+	: "d0", "d1", "d2", "a0", "a1", "a2"	/* clobbered regs */
+	);
+}
+#endif /* _SUPER_H */
diff --git a/usb/store/udelay.c b/usb/store/udelay.c
new file mode 100644
index 0000000..d685aad
--- /dev/null
+++ b/usb/store/udelay.c
@@ -0,0 +1,39 @@
+/* 
+ * David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ * Modified from MiNTlib
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <stdio.h>
+#include <errno.h>
+#include <time.h>
+#include <mint/mintbind.h>
+
+#define USEC_PER_TICK (1000000L / ((unsigned long)CLOCKS_PER_SEC))
+#define	USEC_TO_CLOCK_TICKS(us)	((us) / USEC_PER_TICK )
+
+/*
+ * Galvez: We should use usleep POSIX function in MiNTlib, but it gives problems related with
+ * Fselect system call, until we trace where the problems come from we are using this function 
+ */
+
+void udelay(unsigned long usec)
+{
+	long stop;
+	
+	stop = _clock() + USEC_TO_CLOCK_TICKS(usec);
+	while (_clock() < stop);
+}
diff --git a/usb/store/usb.c b/usb/store/usb.c
new file mode 100644
index 0000000..6b3335d
--- /dev/null
+++ b/usb/store/usb.c
@@ -0,0 +1,1422 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *
+ * Most of this source has been derived from the Linux USB
+ * project:
+ * (C) Copyright Linus Torvalds 1999
+ * (C) Copyright Johannes Erdfelt 1999-2001
+ * (C) Copyright Andreas Gal 1999
+ * (C) Copyright Gregory P. Smith 1999
+ * (C) Copyright Deti Fliegl 1999 (new USB architecture)
+ * (C) Copyright Randy Dunlap 2000
+ * (C) Copyright David Brownell 2000 (kernel hotplug, usb_device_id)
+ * (C) Copyright Yggdrasil Computing, Inc. 2000
+ *     (usb_device_id matching changes by Adam J. Richter)
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * How it works:
+ *
+ * Since this is a bootloader, the devices will not be automatic
+ * (re)configured on hotplug, but after a restart of the USB the
+ * device should work.
+ *
+ * For each transfer (except "Interrupt") we wait for completion.
+ */
+#include "config.h" 
+#include "debug.h"
+#include "usb.h"
+
+#ifdef CONFIG_4xx
+#include <asm/4xx_pci.h>
+#endif
+
+#include <sys/types.h>
+
+#define DEBUG_USB_LOCAL 1
+#ifndef	DEBUG_USB_LOCAL
+#define	DEBUG_USB(fmt, args...)
+#endif
+
+#define USB_BUFSIZ	512
+
+void udelay(unsigned long usec);
+
+static struct usb_device usb_dev[USB_MAX_DEVICE];
+static int dev_index;
+static int running;
+static int asynch_allowed;
+static struct devrequest setup_packet;
+
+char usb_started; /* flag for the started/stopped USB status */
+
+/**********************************************************************
+ * some forward declerations...
+ */
+void usb_scan_devices(void);
+
+int usb_hub_probe(struct usb_device *dev, int ifnum);
+void usb_hub_reset(void);
+static int hub_port_reset(struct usb_device *dev, int port,
+			  unsigned short *portstat);
+
+/***********************************************************************
+ * wait_ms
+ */
+
+inline void wait_ms(unsigned long ms)
+{
+	udelay( ms * 1000);
+}
+
+/***************************************************************************
+ * Init USB Device
+ */
+
+#ifndef PCI_XBIOS
+int usb_init(void)
+#else
+int usb_init(long handle, const struct pci_device_id *ent)
+#endif
+{
+	int result;
+	
+	running = 0;
+	dev_index = 0;
+	asynch_allowed = 1;
+	usb_hub_reset();
+	
+	/* Added by Didier */
+	if(usb_mem_init())
+	{
+		usb_started = 0;
+		return -1; /* out of memoy */
+	}
+	
+	/* init low_level USB */
+	printf("USB:   ");
+#ifndef PCI_XBIOS
+	result = usb_lowlevel_init( );
+#else
+	result = usb_lowlevel_init(0,NULL);
+#endif
+	/* if lowlevel init is OK, scan the bus for devices
+	 * i.e. search HUBs and configure them */
+	if (result == 0) {
+		printf("scanning bus for devices... ");
+		running = 1;
+		usb_scan_devices();
+		usb_started = 1;
+		return 0;
+	} else {
+		printf("Error, couldn't init Lowlevel part\n");
+		usb_started = 0;
+		return -1;
+	}
+}
+
+/******************************************************************************
+ * Stop USB this stops the LowLevel Part and deregisters USB devices.
+ */
+int usb_stop(void)
+{
+	int res = 0;
+
+	if (usb_started) {
+		asynch_allowed = 1;
+		usb_started = 0;
+		usb_hub_reset();
+		res = usb_lowlevel_stop();
+	}
+	return res;
+}
+
+/*
+ * disables the asynch behaviour of the control message. This is used for data
+ * transfers that uses the exclusiv access to the control and bulk messages.
+ */
+void usb_disable_asynch(int disable)
+{
+#if 0
+/* Added by Didier */
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+	if(!asynch_allowed && !disable)
+	{
+		DEBUG_USB("Enable interrupts\r\n");
+		usb_enable_interrupt(1);
+	}
+	else if(asynch_allowed && disable)
+	{
+		DEBUG_USB("Disable interrupts\r\n");
+		usb_enable_interrupt(0);
+	}
+#endif
+#endif
+	asynch_allowed = !disable;
+}
+
+
+/*-------------------------------------------------------------------
+ * Message wrappers.
+ *
+ */
+
+/*
+ * submits an Interrupt Message
+ */
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len, int interval)
+{
+	return submit_int_msg(dev, pipe, buffer, transfer_len, interval);
+}
+
+/*
+ * submits a control message and waits for comletion (at least timeout * 1ms)
+ * If timeout is 0, we don't wait for completion (used as example to set and
+ * clear keyboards LEDs). For data transfers, (storage transfers) we don't
+ * allow control messages with 0 timeout, by previousely resetting the flag
+ * asynch_allowed (usb_disable_asynch(1)).
+ * returns the transfered length if OK or -1 if error. The transfered length
+ * and the current status are stored in the dev->act_len and dev->status.
+ */
+int usb_control_msg(struct usb_device *dev, unsigned int pipe,
+			unsigned char request, unsigned char requesttype,
+			unsigned short value, unsigned short idx,
+			void *data, unsigned short size, int timeout)
+{
+	if ((timeout == 0) && (!asynch_allowed)) {
+		/* request for a asynch control pipe is not allowed */
+		return -1;
+	}
+
+	/* set setup command */
+	setup_packet.requesttype = requesttype;
+	setup_packet.request = request;
+	setup_packet.value = __cpu_to_le16(value);
+	setup_packet.index = __cpu_to_le16(idx);
+	setup_packet.length = __cpu_to_le16(size);
+	DEBUG_USB("usb_control_msg: request: 0x%X, requesttype: 0x%X, " \
+		   "value 0x%X idx 0x%X length 0x%X\n",
+		   request, requesttype, value, idx, size);
+	dev->status = USB_ST_NOT_PROC; /*not yet processed */
+
+	submit_control_msg(dev, pipe, data, size, &setup_packet);
+	if (timeout == 0){
+		DEBUG_USB("size %d \r\n", size);
+		return (int)size;
+	}
+
+	if (dev->status != 0) {
+		/*
+		 * Let's wait a while for the timeout to elapse.
+		 * It has no real use, but it keeps the interface happy.
+		 */
+		DEBUG_USB("status %ld \n\r", dev->status);
+		wait_ms(timeout);
+		return -1;
+	}
+	return dev->act_len;
+}
+
+/*-------------------------------------------------------------------
+ * submits bulk message, and waits for completion. returns 0 if Ok or
+ * -1 if Error.
+ * synchronous behavior
+ */
+int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
+			void *data, int len, int *actual_length, int timeout)
+{
+	if (len < 0)
+		return -1;
+	dev->status = USB_ST_NOT_PROC; /*not yet processed */
+	submit_bulk_msg(dev, pipe, data, len);
+	while (timeout--) {
+		if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC))
+			break;
+		wait_ms(1);
+	}
+
+	*actual_length = dev->act_len;
+	if (dev->status == 0)
+		return 0;
+	else
+		return -1;
+}
+
+
+/*-------------------------------------------------------------------
+ * Max Packet stuff
+ */
+
+/*
+ * returns the max packet size, depending on the pipe direction and
+ * the configurations values
+ */
+int usb_maxpacket(struct usb_device *dev, unsigned long pipe)
+{
+	/* direction is out -> use emaxpacket out */
+	if ((pipe & USB_DIR_IN) == 0)
+		return dev->epmaxpacketout[((pipe>>15) & 0xf)];
+	else
+		return dev->epmaxpacketin[((pipe>>15) & 0xf)];
+}
+
+/* The routine usb_set_maxpacket_ep() is extracted from the loop of routine
+ * usb_set_maxpacket(), because the optimizer of GCC 4.x chokes on this routine
+ * when it is inlined in 1 single routine. What happens is that the register r3
+ * is used as loop-count 'i', but gets overwritten later on.
+ * This is clearly a compiler bug, but it is easier to workaround it here than
+ * to update the compiler (Occurs with at least several GCC 4.{1,2},x
+ * CodeSourcery compilers like e.g. 2007q3, 2008q1, 2008q3 lite editions on ARM)
+ */
+static void  __attribute__((noinline))
+usb_set_maxpacket_ep(struct usb_device *dev, struct usb_endpoint_descriptor *ep)
+{
+	int b;
+
+	b = ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+
+	if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+						USB_ENDPOINT_XFER_CONTROL) {
+		/* Control => bidirectional */
+		dev->epmaxpacketout[b] = ep->wMaxPacketSize;
+		dev->epmaxpacketin[b] = ep->wMaxPacketSize;
+		DEBUG_USB("##Control EP epmaxpacketout/in[%d] = %d\n",
+			   b, dev->epmaxpacketin[b]);
+	} else {
+		if ((ep->bEndpointAddress & 0x80) == 0) {
+			/* OUT Endpoint */
+			if (ep->wMaxPacketSize > dev->epmaxpacketout[b]) {
+				dev->epmaxpacketout[b] = ep->wMaxPacketSize;
+				DEBUG_USB("##EP epmaxpacketout[%d] = %d\n",
+					   b, dev->epmaxpacketout[b]);
+			}
+		} else {
+			/* IN Endpoint */
+			if (ep->wMaxPacketSize > dev->epmaxpacketin[b]) {
+				dev->epmaxpacketin[b] = ep->wMaxPacketSize;
+				DEBUG_USB("##EP epmaxpacketin[%d] = %d\n",
+					   b, dev->epmaxpacketin[b]);
+			}
+		} /* if out */
+	} /* if control */
+}
+
+/*
+ * set the max packed value of all endpoints in the given configuration
+ */
+int usb_set_maxpacket(struct usb_device *dev)
+{
+	int i, ii;
+
+	for (i = 0; i < dev->config.bNumInterfaces; i++)
+		for (ii = 0; ii < dev->config.if_desc[i].bNumEndpoints; ii++)
+			usb_set_maxpacket_ep(dev,
+					  &dev->config.if_desc[i].ep_desc[ii]);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * Parse the config, located in buffer, and fills the dev->config structure.
+ * Note that all little/big endian swapping are done automatically.
+ */
+int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno)
+{
+	struct usb_descriptor_header *head;
+	int idx, ifno, epno, curr_if_num;
+	int i;
+	unsigned char *ch;
+
+	ifno = -1;
+	epno = -1;
+	curr_if_num = -1;
+
+	dev->configno = cfgno;
+	head = (struct usb_descriptor_header *) &buffer[0];
+	if (head->bDescriptorType != USB_DT_CONFIG) {
+		printf(" ERROR: NOT USB_CONFIG_DESC %x\n",
+			head->bDescriptorType);
+		return -1;
+	}
+	memcpy(&dev->config, buffer, buffer[0]);
+	__le16_to_cpus(&(dev->config.wTotalLength));
+	dev->config.no_of_if = 0;
+
+	idx = dev->config.bLength;
+	/* Ok the first entry must be a configuration entry,
+	 * now process the others */
+	head = (struct usb_descriptor_header *) &buffer[idx];
+	while (idx + 1 < dev->config.wTotalLength) {
+		switch (head->bDescriptorType) {
+		case USB_DT_INTERFACE:
+			if (((struct usb_interface_descriptor *) \
+			     &buffer[idx])->bInterfaceNumber != curr_if_num) {
+				/* this is a new interface, copy new desc */
+				ifno = dev->config.no_of_if;
+				dev->config.no_of_if++;
+				memcpy(&dev->config.if_desc[ifno],
+					&buffer[idx], buffer[idx]);
+				dev->config.if_desc[ifno].no_of_ep = 0;
+				dev->config.if_desc[ifno].num_altsetting = 1;
+				curr_if_num =
+				     dev->config.if_desc[ifno].bInterfaceNumber;
+			} else {
+				/* found alternate setting for the interface */
+				dev->config.if_desc[ifno].num_altsetting++;
+			}
+			break;
+		case USB_DT_ENDPOINT:
+			epno = dev->config.if_desc[ifno].no_of_ep;
+			/* found an endpoint */
+			dev->config.if_desc[ifno].no_of_ep++;
+			memcpy(&dev->config.if_desc[ifno].ep_desc[epno],
+				&buffer[idx], buffer[idx]);
+			__le16_to_cpus(&(dev->config.if_desc[ifno].ep_desc[epno].\
+							       wMaxPacketSize));
+			DEBUG_USB("if %d, ep %d\n", ifno, epno);
+			break;
+		default:
+			if (head->bLength == 0)
+				return 1;
+
+			DEBUG_USB("unknown Description Type : %x\n",
+				   head->bDescriptorType);
+
+			{
+				ch = (unsigned char *)head;
+				for (i = 0; i < head->bLength; i++)
+					DEBUG_USB("%02X ", *ch++);
+				DEBUG_USB("\n\n\n");
+			}
+			break;
+		}
+		idx += head->bLength;
+		head = (struct usb_descriptor_header *)&buffer[idx];
+	}
+	return 1;
+}
+
+/***********************************************************************
+ * Clears an endpoint
+ * endp: endpoint number in bits 0-3;
+ * direction flag in bit 7 (1 = IN, 0 = OUT)
+ */
+int usb_clear_halt(struct usb_device *dev, int pipe)
+{
+	int result;
+	int endp = usb_pipeendpoint(pipe)|(usb_pipein(pipe)<<7);
+
+	result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				 USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0,
+				 endp, NULL, 0, USB_CNTL_TIMEOUT * 3);
+
+	/* don't clear if failed */
+	if (result < 0)
+		return result;
+
+	/*
+	 * NOTE: we do not get status and verify reset was successful
+	 * as some devices are reported to lock up upon this check..
+	 */
+
+	usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+
+	/* toggle is reset on clear */
+	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0);
+	return 0;
+}
+
+
+/**********************************************************************
+ * get_descriptor type
+ */
+int usb_get_descriptor(struct usb_device *dev, unsigned char type,
+			unsigned char idx, void *buf, int size)
+{
+	int res;
+DEBUG_USB( "%s\n",__FUNCTION__);
+	res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
+			(type << 8) + idx, 0,
+			buf, size, USB_CNTL_TIMEOUT);
+	return res;
+}
+
+/**********************************************************************
+ * gets configuration cfgno and store it in the buffer
+ */
+int usb_get_configuration_no(struct usb_device *dev,
+			     unsigned char *buffer, int cfgno)
+{
+	int result;
+	unsigned int tmp;
+	struct usb_config_descriptor *config;
+
+
+	config = (struct usb_config_descriptor *)&buffer[0];
+	result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 9);
+	if (result < 9) {
+		if (result < 0)
+			printf("unable to get descriptor, error %lX\n",
+				dev->status);
+		else
+			printf("config descriptor too short " \
+				"(expected %i, got %i)\n", 9, result);
+		return -1;
+	}
+	tmp = __le16_to_cpu(config->wTotalLength);
+
+	if (tmp > USB_BUFSIZ) {
+		DEBUG_USB("usb_get_configuration_no: failed to get " \
+			   "descriptor - too long: %d\n", tmp);
+		return -1;
+	}
+
+	result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp);
+	DEBUG_USB("get_conf_no %d Result %d, wLength %d\n",
+		   cfgno, result, tmp);
+	return result;
+}
+
+/********************************************************************
+ * set address of a device to the value in dev->devnum.
+ * This can only be done by addressing the device via the default address (0)
+ */
+int usb_set_address(struct usb_device *dev)
+{
+	int res;
+
+	DEBUG_USB("set address %d\n", dev->devnum);
+	res = usb_control_msg(dev, usb_snddefctrl(dev),
+				USB_REQ_SET_ADDRESS, 0,
+				(dev->devnum), 0,
+				NULL, 0, USB_CNTL_TIMEOUT);
+	return res;
+}
+
+/********************************************************************
+ * set interface number to interface
+ */
+int usb_set_interface(struct usb_device *dev, int interface, int alternate)
+{
+	struct usb_interface_descriptor *if_face = NULL;
+	int ret, i;
+
+	for (i = 0; i < dev->config.bNumInterfaces; i++) {
+		if (dev->config.if_desc[i].bInterfaceNumber == interface) {
+			if_face = &dev->config.if_desc[i];
+			break;
+		}
+	}
+	if (!if_face) {
+		printf("selecting invalid interface %d", interface);
+		return -1;
+	}
+	/*
+	 * We should return now for devices with only one alternate setting.
+	 * According to 9.4.10 of the Universal Serial Bus Specification
+	 * Revision 2.0 such devices can return with a STALL. This results in
+	 * some USB sticks timeouting during initialization and then being
+	 * unusable in U-Boot.
+	 */
+	if (if_face->num_altsetting == 1)
+		return 0;
+
+	ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE,
+				alternate, interface, NULL, 0,
+				USB_CNTL_TIMEOUT * 5);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+/********************************************************************
+ * set configuration number to configuration
+ */
+int usb_set_configuration(struct usb_device *dev, int configuration)
+{
+	int res;
+	DEBUG_USB("set configuration %d\n", configuration);
+	/* set setup command */
+	res = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_SET_CONFIGURATION, 0,
+				configuration, 0,
+				NULL, 0, USB_CNTL_TIMEOUT);
+	if (res == 0) {
+		dev->toggle[0] = 0;
+		dev->toggle[1] = 0;
+		return 0;
+	} else
+		return -1;
+}
+
+/********************************************************************
+ * set protocol to protocol
+ */
+int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+		USB_REQ_SET_PROTOCOL, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
+		protocol, ifnum, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * set idle
+ */
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+		USB_REQ_SET_IDLE, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
+		(duration << 8) | report_id, ifnum, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * get report
+ */
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
+		   unsigned char id, void *buf, int size)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_REPORT,
+			USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
+			(type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * get class descriptor
+ */
+int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
+		unsigned char type, unsigned char id, void *buf, int size)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+		USB_REQ_GET_DESCRIPTOR, USB_RECIP_INTERFACE | USB_DIR_IN,
+		(type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * get string index in buffer
+ */
+int usb_get_string(struct usb_device *dev, unsigned short langid,
+		   unsigned char idx, void *buf, int size)
+{
+	int i;
+	int result;
+
+	for (i = 0; i < 3; ++i) {
+		/* some devices are flaky */
+		result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
+			(USB_DT_STRING << 8) + idx, langid, buf, size,
+			USB_CNTL_TIMEOUT);
+
+		if (result > 0)
+			break;
+	}
+
+	return result;
+}
+
+
+static void usb_try_string_workarounds(unsigned char *buf, int *length)
+{
+	int newlength, oldlength = *length;
+
+	for (newlength = 2; newlength + 1 < oldlength; newlength += 2)
+	{
+		char c = buf[newlength];
+		if ((c < ' ') || (c >= 127) || buf[newlength + 1])
+			break;
+	}
+	if (newlength > 2) {
+		buf[0] = newlength;
+		*length = newlength;
+	}
+}
+
+
+static int usb_string_sub(struct usb_device *dev, unsigned int langid,
+		unsigned int idx, unsigned char *buf)
+{
+	int rc;
+
+	/* Try to read the string descriptor by asking for the maximum
+	 * possible number of bytes */
+	rc = usb_get_string(dev, langid, idx, buf, 255);
+
+	/* If that failed try to read the descriptor length, then
+	 * ask for just that many bytes */
+	if (rc < 2) {
+		rc = usb_get_string(dev, langid, idx, buf, 2);
+		if (rc == 2)
+			rc = usb_get_string(dev, langid, idx, buf, buf[0]);
+	}
+
+	if (rc >= 2) {
+		if (!buf[0] && !buf[1])
+			usb_try_string_workarounds(buf, &rc);
+
+		/* There might be extra junk at the end of the descriptor */
+		if (buf[0] < rc)
+			rc = buf[0];
+
+		rc = rc - (rc & 1); /* force a multiple of two */
+	}
+
+	if (rc < 2)
+		rc = -1;
+
+	return rc;
+}
+
+
+/********************************************************************
+ * usb_string:
+ * Get string index and translate it to ascii.
+ * returns string length (> 0) or error (< 0)
+ */
+int usb_string(struct usb_device *dev, int idx, char *buf, size_t size)
+{
+	unsigned char mybuf[USB_BUFSIZ];
+	unsigned char *tbuf;
+	int err;
+	unsigned int u, idx2;
+
+	if (size <= 0 || !buf || !idx)
+		return -1;
+	buf[0] = 0;
+	tbuf = &mybuf[0];
+
+	/* get langid for strings if it's not yet known */
+	if (!dev->have_langid) {
+		err = usb_string_sub(dev, 0, 0, tbuf);
+		if (err < 0) {
+			DEBUG_USB("error getting string descriptor 0 " \
+				   "(error=%lx)\n", dev->status);
+			return -1;
+		} else if (tbuf[0] < 4) {
+			DEBUG_USB("string descriptor 0 too short\n");
+			return -1;
+		} else {
+			dev->have_langid = -1;
+			dev->string_langid = tbuf[2] | (tbuf[3] << 8);
+				/* always use the first langid listed */
+			DEBUG_USB("USB device number %d default " \
+				   "language ID 0x%x\n",
+				   dev->devnum, dev->string_langid);
+		}
+	}
+
+	err = usb_string_sub(dev, dev->string_langid, idx, tbuf);
+	if (err < 0)
+		return err;
+
+	size--;		/* leave room for trailing NULL char in output buffer */
+	for (idx2 = 0, u = 2; u < err; u += 2) {
+		if (idx2 >= size)
+			break;
+		if (tbuf[u+1])			/* high byte */
+			buf[idx2++] = '?';  /* non-ASCII character */
+		else
+			buf[idx2++] = tbuf[u];
+	}
+	buf[idx2] = 0;
+	err = idx2;
+	return err;
+}
+
+
+/********************************************************************
+ * USB device handling:
+ * the USB device are static allocated [USB_MAX_DEVICE].
+ */
+
+
+/* returns a pointer to the device with the index [idx].
+ * if the device is not assigned (dev->devnum==-1) returns NULL
+ */
+struct usb_device *usb_get_dev_index(int idx)
+{
+	if (usb_dev[idx].devnum == -1)
+		return NULL;
+	else
+		return &usb_dev[idx];
+}
+
+
+/* returns a pointer of a new device structure or NULL, if
+ * no device struct is available
+ */
+struct usb_device *usb_alloc_new_device(void)
+{
+	int i;
+	DEBUG_USB("New Device %d\n", dev_index);
+	if (dev_index == USB_MAX_DEVICE) {
+		printf("ERROR, too many USB Devices, max=%d\n", USB_MAX_DEVICE);
+		return NULL;
+	}
+	/* default Address is 0, real addresses start with 1 */
+	usb_dev[dev_index].devnum = dev_index + 1;
+	usb_dev[dev_index].maxchild = 0;
+	for (i = 0; i < USB_MAXCHILDREN; i++)
+		usb_dev[dev_index].children[i] = NULL;
+	usb_dev[dev_index].parent = NULL;
+	dev_index++;
+	return &usb_dev[dev_index - 1];
+}
+
+
+/*
+ * By the time we get here, the device has gotten a new device ID
+ * and is in the default state. We need to identify the thing and
+ * get the ball rolling..
+ *
+ * Returns 0 for success, != 0 for error.
+ */
+int usb_new_device(struct usb_device *dev)
+{
+	int addr, err;
+	int tmp;
+	unsigned char tmpbuf[USB_BUFSIZ];
+ 
+ 	/* We still haven't set the Address yet */
+ 	addr = dev->devnum;
+ 	dev->devnum = 0;
+	
+
+#ifdef CONFIG_LEGACY_USB_INIT_SEQ
+	/* this is the old and known way of initializing devices, it is
+	 * different than what Windows and Linux are doing. Windows and Linux
+	 * both retrieve 64 bytes while reading the device descriptor
+	 * Several USB stick devices report ERR: CTL_TIMEOUT, caused by an
+	 * invalid header while reading 8 bytes as device descriptor. */
+	dev->descriptor.bMaxPacketSize0 = 8;	    /* Start off at 8 bytes  */
+	dev->maxpacketsize = PACKET_SIZE_8;
+	dev->epmaxpacketin[0] = 8;
+	dev->epmaxpacketout[0] = 8;
+
+	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8);
+	if (err < 8) {
+		printf("\n      USB device not responding, " \
+		       "giving up (status=%lX)\n", dev->status);
+		return 1;
+	}
+
+#else	
+	/* This is a Windows scheme of initialization sequence, with double
+	 * reset of the device (Linux uses the same sequence)
+	 * Some equipment is said to work only with such init sequence; this
+	 * patch is based on the work by Alan Stern:
+	 * http://sourceforge.net/mailarchive/forum.php?
+	 * thread_id=5729457&forum_id=5398
+	 */
+
+	struct usb_device_descriptor *desc;
+	int port = -1;
+	struct usb_device *parent = dev->parent;
+	unsigned short portstatus;
+
+	/* send 64-byte GET-DEVICE-DESCRIPTOR request.  Since the descriptor is
+	 * only 18 bytes long, this will terminate with a short packet.  But if
+	 * the maxpacket size is 8 or 16 the device may be waiting to transmit
+	 * some more, or keeps on retransmitting the 8 byte header. */
+
+	desc = (struct usb_device_descriptor *)tmpbuf;
+	dev->descriptor.bMaxPacketSize0 = 64;	    /* Start off at 64 bytes  */
+	/* Default to 64 byte max packet size */
+	dev->maxpacketsize = PACKET_SIZE_64;
+	dev->epmaxpacketin[0] = 64;
+	dev->epmaxpacketout[0] = 64;
+
+	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
+	if (err < 0) {
+		DEBUG_USB("usb_new_device: usb_get_descriptor() failed\n");
+		return 1;
+	}
+
+	dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0;
+
+	/* find the port number we're at */
+	if (parent) {
+		int j;
+
+		for (j = 0; j < parent->maxchild; j++) {
+			if (parent->children[j] == dev) {
+				port = j;
+				break;
+			}
+		}
+		if (port < 0) {
+			printf("usb_new_device:cannot locate device's port.\n");
+			return 1;
+		}
+
+		/* reset the port for the second time */
+		err = hub_port_reset(dev->parent, port, &portstatus);
+		if (err < 0) {
+			printf("\n     Couldn't reset port %i\n", port);
+			return 1;
+		}
+	}
+#endif
+
+	dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0;
+	dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0;
+	switch (dev->descriptor.bMaxPacketSize0) {
+	case 8:
+		dev->maxpacketsize  = PACKET_SIZE_8;
+		break;
+	case 16:
+		dev->maxpacketsize = PACKET_SIZE_16;
+		break;
+	case 32:
+		dev->maxpacketsize = PACKET_SIZE_32;
+		break;
+	case 64:
+		dev->maxpacketsize = PACKET_SIZE_64;
+		break;
+	}
+	dev->devnum = addr;
+
+	err = usb_set_address(dev); /* set address */
+
+	if (err < 0) {
+		printf("\n      USB device not accepting new address " \
+			"(error=%lX)\n", dev->status);
+		return 1;
+	}
+
+	wait_ms(10);	/* Let the SET_ADDRESS settle */
+
+	tmp = sizeof(dev->descriptor);
+
+	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0,
+				 &dev->descriptor, sizeof(dev->descriptor));
+	if (err < tmp) {
+		if (err < 0)
+			printf("unable to get device descriptor (error=%d)\n",
+			       err);
+		else
+			printf("USB device descriptor short read " \
+				"(expected %i, got %i)\n", tmp, err);
+		return 1;
+	}
+	/* correct le values */
+	__le16_to_cpus(&dev->descriptor.bcdUSB);
+	__le16_to_cpus(&dev->descriptor.idVendor);
+	__le16_to_cpus(&dev->descriptor.idProduct);
+	__le16_to_cpus(&dev->descriptor.bcdDevice);
+	/* only support for one config for now */
+	usb_get_configuration_no(dev, &tmpbuf[0], 0);
+	usb_parse_config(dev, &tmpbuf[0], 0);
+	usb_set_maxpacket(dev);
+	/* we set the default configuration here */
+	if (usb_set_configuration(dev, dev->config.bConfigurationValue)) {
+		printf("failed to set default configuration " \
+			"len %d, status %lX\n", dev->act_len, dev->status);
+		return -1;
+	}
+	DEBUG_USB("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
+		   dev->descriptor.iManufacturer, dev->descriptor.iProduct,
+		   dev->descriptor.iSerialNumber);
+	memset(dev->mf, 0, sizeof(dev->mf));
+	memset(dev->prod, 0, sizeof(dev->prod));
+	memset(dev->serial, 0, sizeof(dev->serial));
+	if (dev->descriptor.iManufacturer)
+		usb_string(dev, dev->descriptor.iManufacturer,
+			   dev->mf, sizeof(dev->mf));
+	if (dev->descriptor.iProduct)
+		usb_string(dev, dev->descriptor.iProduct,
+			   dev->prod, sizeof(dev->prod));
+	if (dev->descriptor.iSerialNumber)
+		usb_string(dev, dev->descriptor.iSerialNumber,
+			   dev->serial, sizeof(dev->serial));
+	DEBUG_USB("Manufacturer %s\n", dev->mf);
+	DEBUG_USB("Product      %s\n", dev->prod);
+	DEBUG_USB("SerialNumber %s\n", dev->serial);
+	/* now probe if the device is a hub */
+	usb_hub_probe(dev, 0);
+	return 0;
+}
+
+
+/* build device Tree  */
+void usb_scan_devices(void)
+{
+	int i;
+	struct usb_device *dev;
+
+	/* first make all devices unknown */
+	for (i = 0; i < USB_MAX_DEVICE; i++) {
+		memset(&usb_dev[i], 0, sizeof(struct usb_device));
+		usb_dev[i].devnum = -1;
+	}
+	dev_index = 0;
+	/* device 0 is always present (root hub, so let it analyze) */
+	dev = usb_alloc_new_device();
+	if (usb_new_device(dev))
+		printf("No USB Device found\n");
+	else
+		printf("%d USB Device(s) found\n", dev_index);
+	/* insert "driver" if possible */
+#ifdef CONFIG_USB_KEYBOARD
+	drv_usb_kbd_init();
+	DEBUG_USB("scan end\n");
+#endif
+
+#ifdef CONFIG_USB_MOUSE
+	drv_usb_mouse_init();
+	DEBUG_USB("scan end\n");
+#endif
+}
+
+
+/****************************************************************************
+ * HUB "Driver"
+ * Probes device for being a hub and configurate it
+ */
+
+static struct usb_hub_device hub_dev[USB_MAX_HUB];
+static int usb_hub_index;
+
+
+int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+		USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB,
+		USB_DT_HUB << 8, 0, data, size, USB_CNTL_TIMEOUT);
+}
+
+int usb_clear_hub_feature(struct usb_device *dev, int feature)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_CLEAR_FEATURE, USB_RT_HUB, feature,
+				0, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+int usb_clear_port_feature(struct usb_device *dev, int port, int feature)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_CLEAR_FEATURE, USB_RT_PORT, feature,
+				port, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+int usb_set_port_feature(struct usb_device *dev, int port, int feature)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_SET_FEATURE, USB_RT_PORT, feature,
+				port, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+int usb_get_hub_status(struct usb_device *dev, void *data)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_HUB, 0, 0,
+			data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT);
+}
+
+int usb_get_port_status(struct usb_device *dev, int port, void *data)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port,
+			data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT);
+}
+
+
+static void usb_hub_power_on(struct usb_hub_device *hub)
+{
+	int i;
+	struct usb_device *dev;
+
+	dev = hub->pusb_dev;
+	/* Enable power to the ports */
+	DEBUG_HUB("enabling power on all ports\n");
+	for (i = 0; i < dev->maxchild; i++) {
+		usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
+		DEBUG_HUB("port %d returns %lX\n", i + 1, dev->status);
+		wait_ms(hub->desc.bPwrOn2PwrGood * 2);
+	}
+}
+
+void usb_hub_reset(void)
+{
+	usb_hub_index = 0;
+}
+
+struct usb_hub_device *usb_hub_allocate(void)
+{
+	if (usb_hub_index < USB_MAX_HUB)
+		return &hub_dev[usb_hub_index++];
+
+	printf("ERROR: USB_MAX_HUB (%d) reached\n", USB_MAX_HUB);
+	return NULL;
+}
+
+#define MAX_TRIES 5
+
+static inline char *portspeed(int portstatus)
+{
+	if (portstatus & (1 << USB_PORT_FEAT_HIGHSPEED))
+		return "480 Mb/s";
+	else if (portstatus & (1 << USB_PORT_FEAT_LOWSPEED))
+		return "1.5 Mb/s";
+	else
+		return "12 Mb/s";
+}
+
+static int hub_port_reset(struct usb_device *dev, int port,
+			unsigned short *portstat)
+{
+	int tries;
+	struct usb_port_status portsts;
+	unsigned short portstatus, portchange;
+
+	DEBUG_HUB("hub_port_reset: resetting port %d...\n", port);
+	for (tries = 0; tries < MAX_TRIES; tries++) {
+
+		usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET);
+		wait_ms(200);
+
+		if (usb_get_port_status(dev, port + 1, &portsts) < 0) {
+			DEBUG_HUB("get_port_status failed status %lX\n",
+					dev->status);
+			return -1;
+		}
+		portstatus = __le16_to_cpu(portsts.wPortStatus);
+		portchange = __le16_to_cpu(portsts.wPortChange);
+
+		DEBUG_HUB("portstatus %x, change %x, %s\n",
+				portstatus, portchange,
+				portspeed(portstatus));
+
+		DEBUG_HUB("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \
+			       "  USB_PORT_STAT_ENABLE %d\n",
+			(portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0,
+			(portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0,
+			(portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0);
+
+		if ((portchange & USB_PORT_STAT_C_CONNECTION) ||
+		    !(portstatus & USB_PORT_STAT_CONNECTION))
+			return -1;
+
+		if (portstatus & USB_PORT_STAT_ENABLE)
+			break;
+
+		wait_ms(200);
+	}
+
+	if (tries == MAX_TRIES) {
+		DEBUG_HUB("Cannot enable port %i after %i retries, " \
+				"disabling port.\n", port + 1, MAX_TRIES);
+		DEBUG_HUB("Maybe the USB cable is bad?\n");
+		return -1;
+	}
+
+	usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_RESET);
+	*portstat = portstatus;
+	return 0;
+}
+
+
+void usb_hub_port_connect_change(struct usb_device *dev, int port)
+{
+	struct usb_device *usb;
+	struct usb_port_status portsts;
+	unsigned short portstatus, portchange;
+
+	/* Check status */
+	if (usb_get_port_status(dev, port + 1, &portsts) < 0) {
+		DEBUG_HUB("get_port_status failed\n");
+		return;
+	}
+
+	portstatus = __le16_to_cpu(portsts.wPortStatus);
+	portchange = __le16_to_cpu(portsts.wPortChange);
+	DEBUG_HUB("portstatus %x, change %x, %s\n",
+			portstatus, portchange, portspeed(portstatus));
+
+	/* Clear the connection change status */
+	usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION);
+
+	/* Disconnect any existing devices under this port */
+	if (((!(portstatus & USB_PORT_STAT_CONNECTION)) &&
+	     (!(portstatus & USB_PORT_STAT_ENABLE))) || (dev->children[port])) {
+		DEBUG_HUB("usb_disconnect(&hub->children[port]);\n");
+		/* Return now if nothing is connected */
+		if (!(portstatus & USB_PORT_STAT_CONNECTION))
+			return;
+	}
+	wait_ms(200);
+
+	/* Reset the port */
+	if (hub_port_reset(dev, port, &portstatus) < 0) {
+		printf("cannot reset port %i!?\n", port + 1);
+		return;
+	}
+
+	wait_ms(200);
+
+	/* Allocate a new device struct for it */
+	usb = usb_alloc_new_device();
+	if (portstatus & USB_PORT_STAT_HIGH_SPEED)
+		usb->speed = USB_SPEED_HIGH;
+	else if (portstatus & USB_PORT_STAT_LOW_SPEED)
+		usb->speed = USB_SPEED_LOW;
+	else
+		usb->speed = USB_SPEED_FULL;
+
+	dev->children[port] = usb;
+	usb->parent = dev;
+	/* Run it through the hoops (find a driver, etc) */
+	if (usb_new_device(usb)) {
+		/* Woops, disable the port */
+		DEBUG_HUB("hub: disabling port %d\n", port + 1);
+		usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE);
+	}
+}
+
+
+int usb_hub_configure(struct usb_device *dev)
+{
+	unsigned char buffer[USB_BUFSIZ], *bitmap;
+	struct usb_hub_descriptor *descriptor;
+	struct usb_hub_status *hubsts;
+	int i;
+	struct usb_hub_device *hub;
+
+	/* "allocate" Hub device */
+	hub = usb_hub_allocate();
+	if (hub == NULL)
+		return -1;
+	hub->pusb_dev = dev;
+	/* Get the the hub descriptor */
+	if (usb_get_hub_descriptor(dev, buffer, 4) < 0) {
+		DEBUG_HUB("usb_hub_configure: failed to get hub " \
+				   "descriptor, giving up %lX\n", dev->status);
+		return -1;
+	}
+	descriptor = (struct usb_hub_descriptor *)buffer;
+
+	/* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */
+	i = descriptor->bLength;
+	if (i > USB_BUFSIZ) {
+		DEBUG_HUB("usb_hub_configure: failed to get hub " \
+				"descriptor - too long: %d\n",
+				descriptor->bLength);
+		return -1;
+	}
+
+	if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) {
+		DEBUG_HUB("usb_hub_configure: failed to get hub " \
+				"descriptor 2nd giving up %lX\n", dev->status);
+		return -1;
+	}
+	memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength);
+	/* adjust 16bit values */
+	hub->desc.wHubCharacteristics =
+				__le16_to_cpu(descriptor->wHubCharacteristics);
+
+	/* set the bitmap */
+	bitmap = (unsigned char *)&hub->desc.DeviceRemovable[0];
+	/* devices not removable by default */
+	memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8);
+	bitmap = (unsigned char *)&hub->desc.PortPowerCtrlMask[0];
+	memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); /* PowerMask = 1B */
+
+	for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
+		hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i];
+
+	for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
+		hub->desc.DeviceRemovable[i] = descriptor->PortPowerCtrlMask[i];
+
+	dev->maxchild = descriptor->bNbrPorts;
+	DEBUG_HUB("%d ports detected\n", dev->maxchild);
+
+	switch (hub->desc.wHubCharacteristics & HUB_CHAR_LPSM) {
+	case 0x00:
+		DEBUG_HUB("ganged power switching\n");
+		break;
+	case 0x01:
+		DEBUG_HUB("individual port power switching\n");
+		break;
+	case 0x02:
+	case 0x03:
+		DEBUG_HUB("unknown reserved power switching mode\n");
+		break;
+	}
+
+	if (hub->desc.wHubCharacteristics & HUB_CHAR_COMPOUND) {
+		DEBUG_HUB("part of a compound device\n");
+	}
+	else {
+		DEBUG_HUB("standalone hub\n");
+	}
+
+	switch (hub->desc.wHubCharacteristics & HUB_CHAR_OCPM) {
+	case 0x00:
+		DEBUG_HUB("global over-current protection\n");
+		break;
+	case 0x08:
+		DEBUG_HUB("individual port over-current protection\n");
+		break;
+	case 0x10:
+	case 0x18:
+		DEBUG_HUB("no over-current protection\n");
+		break;
+	}
+
+	DEBUG_HUB("power on to power good time: %dms\n",
+			descriptor->bPwrOn2PwrGood * 2);
+	DEBUG_HUB("hub controller current requirement: %dmA\n",
+			descriptor->bHubContrCurrent);
+
+	for (i = 0; i < dev->maxchild; i++)
+		DEBUG_HUB("port %d is%s removable\n", i + 1,
+			hub->desc.DeviceRemovable[(i + 1) / 8] & \
+					   (1 << ((i + 1) % 8)) ? " not" : "");
+
+	if (sizeof(struct usb_hub_status) > USB_BUFSIZ) {
+		DEBUG_HUB("usb_hub_configure: failed to get Status - " \
+				"too long: %d\n", descriptor->bLength);
+		return -1;
+	}
+
+	if (usb_get_hub_status(dev, buffer) < 0) {
+		DEBUG_HUB("usb_hub_configure: failed to get Status %lX\n",
+				dev->status);
+		return -1;
+	}
+
+	hubsts = (struct usb_hub_status *)buffer;
+	DEBUG_HUB("get_hub_status returned status %X, change %X\n",
+			__le16_to_cpu(hubsts->wHubStatus),
+			__le16_to_cpu(hubsts->wHubChange));
+	DEBUG_HUB("local power source is %s\n",
+		(__le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? \
+		"lost (inactive)" : "good");
+	DEBUG_HUB("%sover-current condition exists\n",
+		(__le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \
+		"" : "no ");
+	usb_hub_power_on(hub);
+
+
+
+	for (i = 0; i < dev->maxchild; i++) {
+		struct usb_port_status portsts;
+		unsigned short portstatus, portchange;
+		
+		wait_ms (100); /* GALVEZ: add delay for MiNT/TOS */
+		
+		if (usb_get_port_status(dev, i + 1, &portsts) < 0) {
+			DEBUG_HUB("get_port_status failed\n");
+			continue;
+		}
+
+		portstatus = __le16_to_cpu(portsts.wPortStatus);
+		portchange = __le16_to_cpu(portsts.wPortChange);
+		DEBUG_HUB("Port %d Status %X Change %X\n",
+				i + 1, portstatus, portchange);
+
+		if (portchange & USB_PORT_STAT_C_CONNECTION) {
+			DEBUG_HUB("port %d connection change\n", i + 1);
+			usb_hub_port_connect_change(dev, i);
+		}
+
+		if (portchange & USB_PORT_STAT_C_ENABLE) {
+			DEBUG_HUB("port %d enable change, status %x\n",
+					i + 1, portstatus);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_C_ENABLE);
+
+			/* EM interference sometimes causes bad shielded USB
+			 * devices to be shutdown by the hub, this hack enables
+			 * them again. Works at least with mouse driver */
+			if (!(portstatus & USB_PORT_STAT_ENABLE) &&
+			     (portstatus & USB_PORT_STAT_CONNECTION) &&
+			     ((dev->children[i]))) {
+				DEBUG_HUB("already running port %i "  \
+						"disabled by hub (EMI?), " \
+						"re-enabling...\n", i + 1);
+					usb_hub_port_connect_change(dev, i);
+			}
+		}
+		if (portstatus & USB_PORT_STAT_SUSPEND) {
+			DEBUG_HUB("port %d suspend change\n", i + 1);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_SUSPEND);
+		}
+
+		if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
+			DEBUG_HUB("port %d over-current change\n", i + 1);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_C_OVER_CURRENT);
+			usb_hub_power_on(hub);
+		}
+
+		if (portchange & USB_PORT_STAT_C_RESET) {
+			DEBUG_HUB("port %d reset change\n", i + 1);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_C_RESET);
+		}
+	} /* end for i all ports */
+	return 0;
+}
+
+int usb_hub_probe(struct usb_device *dev, int ifnum)
+{
+	struct usb_interface_descriptor *iface;
+	struct usb_endpoint_descriptor *ep;
+	int ret;
+
+	iface = &dev->config.if_desc[ifnum];
+	/* Is it a hub? */
+	if (iface->bInterfaceClass != USB_CLASS_HUB)
+		return 0;
+	/* Some hubs have a subclass of 1, which AFAICT according to the */
+	/*  specs is not defined, but it works */
+	if ((iface->bInterfaceSubClass != 0) &&
+	    (iface->bInterfaceSubClass != 1))
+		return 0;
+	/* Multiple endpoints? What kind of mutant ninja-hub is this? */
+	if (iface->bNumEndpoints != 1)
+		return 0;
+	ep = &iface->ep_desc[0];
+	/* Output endpoint? Curiousier and curiousier.. */
+	if (!(ep->bEndpointAddress & USB_DIR_IN))
+		return 0;
+	/* If it's not an interrupt endpoint, we'd better punt! */
+	if ((ep->bmAttributes & 3) != 3)
+		return 0;
+	/* We found a hub */
+	DEBUG_HUB("USB hub found\n");
+	ret = usb_hub_configure(dev);
+
+	return ret;
+}
+
+/* EOF */
diff --git a/usb/store/usb.h b/usb/store/usb.h
new file mode 100644
index 0000000..ce2cd93
--- /dev/null
+++ b/usb/store/usb.h
@@ -0,0 +1,470 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *	
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_H_
+#define _USB_H_
+
+#include <mint/osbind.h>
+#include <mint/sysvars.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "host/ohci-pci/mod_devicetable.h"
+#include "usb_defs.h"
+#include "asm-m68k/types.h"
+#include "asm-m68k/byteorder.h"
+#include "part.h"
+
+#ifdef PCI_XBIOS
+
+#define in8(addr)		fast_read_mem_byte(usb_handle,addr)
+#define in16r(addr)		fast_read_mem_word(usb_handle,addr)
+#define in32r(addr)		fast_read_mem_longword(usb_handle,addr)
+#define out8(addr,val)	write_mem_byte(usb_handle,addr,val)
+#define out16r(addr,val)	write_mem_word(usb_handle,addr,val)
+#define out32r(addr,val)	write_mem_longword(usb_handle,addr,val)
+
+#else /* !PCI_XBIOS */
+
+extern long *tab_funcs_pci;
+
+#define in8(addr)		Fast_read_mem_byte(usb_handle,addr)
+#define in16r(addr)		Fast_read_mem_word(usb_handle,addr)
+#define in32r(addr)		Fast_read_mem_longword(usb_handle,addr)
+#define out8(addr,val)	Write_mem_byte(usb_handle,addr,val)
+#define out16r(addr,val)	Write_mem_word(usb_handle,addr,val)
+#define out32r(addr,val)	Write_mem_longword(usb_handle,addr,val)
+
+#endif /* PCI_XBIOS */
+
+
+/* Everything is aribtrary */
+#define USB_ALTSETTINGALLOC		4
+#define USB_MAXALTSETTING		128	/* Hard limit */
+
+#define USB_MAX_DEVICE			32
+#define USB_MAXCONFIG			8
+#define USB_MAXINTERFACES		8
+#define USB_MAXENDPOINTS		16
+#define USB_MAXCHILDREN			8	/* This is arbitrary */
+#define USB_MAX_HUB			16
+
+#define USB_CNTL_TIMEOUT 100	/* 100ms timeout */
+
+/* String descriptor */
+struct usb_string_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wData[1];
+} __attribute__ ((packed));
+
+/* device request (setup) */
+struct devrequest {
+	unsigned char	requesttype;
+	unsigned char	request;
+	unsigned short	value;
+	unsigned short	index;
+	unsigned short	length;
+} __attribute__ ((packed));
+
+/* All standard descriptors have these 2 fields in common */
+struct usb_descriptor_header {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+} __attribute__ ((packed));
+
+/* Device descriptor */
+struct usb_device_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	bcdUSB;
+	unsigned char	bDeviceClass;
+	unsigned char	bDeviceSubClass;
+	unsigned char	bDeviceProtocol;
+	unsigned char	bMaxPacketSize0;
+	unsigned short	idVendor;
+	unsigned short	idProduct;
+	unsigned short	bcdDevice;
+	unsigned char	iManufacturer;
+	unsigned char	iProduct;
+	unsigned char	iSerialNumber;
+	unsigned char	bNumConfigurations;
+} __attribute__ ((packed));
+
+/* Endpoint descriptor */
+struct usb_endpoint_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bEndpointAddress;
+	unsigned char	bmAttributes;
+	unsigned short	wMaxPacketSize;
+	unsigned char	bInterval;
+	unsigned char	bRefresh;
+	unsigned char	bSynchAddress;
+} __attribute__ ((packed)) __attribute__ ((aligned(2)));
+
+/* Interface descriptor */
+struct usb_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+
+	unsigned char	no_of_ep;
+	unsigned char	num_altsetting;
+	unsigned char	act_altsetting;
+
+	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+} __attribute__ ((packed));
+
+
+/* Configuration descriptor information.. */
+struct usb_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+
+	unsigned char	no_of_if;	/* number of interfaces */
+	struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
+} __attribute__ ((packed));
+
+enum {
+	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+	PACKET_SIZE_8   = 0,
+	PACKET_SIZE_16  = 1,
+	PACKET_SIZE_32  = 2,
+	PACKET_SIZE_64  = 3,
+};
+
+struct usb_device {
+	int	devnum;			/* Device number on USB bus */
+	int	speed;			/* full/low/high */
+	char	mf[32];			/* manufacturer */
+	char	prod[32];		/* product */
+	char	serial[32];		/* serial number */
+
+	/* Maximum packet size; one of: PACKET_SIZE_* */
+	int maxpacketsize;
+	/* one bit for each endpoint ([0] = IN, [1] = OUT) */
+	unsigned int toggle[2];
+	/* endpoint halts; one bit per endpoint # & direction;
+	 * [0] = IN, [1] = OUT
+	 */
+	unsigned int halted[2];
+	int epmaxpacketin[16];		/* INput endpoint specific maximums */
+	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
+
+	int configno;			/* selected config number */
+	struct usb_device_descriptor descriptor; /* Device Descriptor */
+	struct usb_config_descriptor config; /* config descriptor */
+
+	int have_langid;		/* whether string_langid is valid yet */
+	int string_langid;		/* language ID for strings */
+	int (*irq_handle)(struct usb_device *dev);
+	unsigned long irq_status;
+	int irq_act_len;		/* transfered bytes */
+	void *privptr;
+	/*
+	 * Child devices -  if this is a hub device
+	 * Each instance needs its own set of data structures.
+	 */
+	unsigned long status;
+	int act_len;			/* transfered bytes */
+	int maxchild;			/* Number of ports if hub */
+	int portnr;
+	struct usb_device *parent;
+	struct usb_device *children[USB_MAXCHILDREN];
+};
+
+/**********************************************************************
+ * this is how the lowlevel part communicate with the outer world
+ */
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
+	defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
+	defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
+	defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
+	defined(CONFIG_USB_ARANYM_HCD)
+
+#ifdef PCI_XBIOS
+int usb_lowlevel_init(long handle, const struct pci_device_id *ent);
+#else
+int usb_lowlevel_init(void);
+#endif
+
+int usb_lowlevel_stop(void);
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len);
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, struct devrequest *setup);
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, int interval);
+			
+#ifdef CONFIG_USB_INTERRUPT_POLLING
+void usb_event_poll(void);
+#else
+void usb_enable_interrupt(int enable);
+#endif
+
+/* Defines */
+#define USB_UHCI_VEND_ID	0x8086
+#define USB_UHCI_DEV_ID		0x7112
+
+#else
+#error USB Lowlevel not defined
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+
+#define USB_MAX_STOR_DEV 2	/* GALVEZ: DEFAULT 5 */
+block_dev_desc_t *usb_stor_get_dev(int idx);
+int usb_stor_scan(void);
+int usb_stor_info(void);
+
+#endif
+
+#ifdef CONFIG_USB_MOUSE
+int drv_usb_mouse_init(void);
+int usb_mouse_deregister(void);
+#endif
+
+
+#ifdef CONFIG_USB_KEYBOARD
+int drv_usb_kbd_init(void);
+int usb_kbd_deregister(void);
+#endif
+
+/* memory */
+void *usb_malloc(long amount);
+int usb_free(void *addr);
+int usb_mem_init(void);
+void usb_mem_stop(void);
+
+
+/* routines */
+#ifdef PCI_XBIOS
+int usb_init(long handle, const struct pci_device_id *ent); /* initialize the USB Controller */
+#else
+int usb_init(void); /* initialize the USB Controller */
+#endif
+int usb_stop(void); /* stop the USB Controller */
+
+
+int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration,
+			int report_id);
+struct usb_device *usb_get_dev_index(int idx);
+int usb_control_msg(struct usb_device *dev, unsigned int pipe,
+			unsigned char request, unsigned char requesttype,
+			unsigned short value, unsigned short idx,
+			void *data, unsigned short size, int timeout);
+int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
+			void *data, int len, int *actual_length, int timeout);
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len, int interval);
+void usb_disable_asynch(int disable);
+int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
+inline void wait_ms(unsigned long ms);
+int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer,
+				int cfgno);
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
+			unsigned char id, void *buf, int size);
+int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
+			unsigned char type, unsigned char id, void *buf,
+			int size);
+int usb_clear_halt(struct usb_device *dev, int pipe);
+int usb_string(struct usb_device *dev, int idx, char *buf, size_t size);
+int usb_set_interface(struct usb_device *dev, int interface, int alternate);
+
+/* big endian -> little endian conversion */
+/* some CPUs are already little endian e.g. the ARM920T */
+#define __swap_16(x) \
+	({ unsigned short x_ = (unsigned short)x; \
+	 (unsigned short)( \
+		((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \
+	})
+#define __swap_32(x) \
+	({ unsigned long x_ = (unsigned long)x; \
+	 (unsigned long)( \
+		((x_ & 0x000000FFUL) << 24) | \
+		((x_ & 0x0000FF00UL) <<	 8) | \
+		((x_ & 0x00FF0000UL) >>	 8) | \
+		((x_ & 0xFF000000UL) >> 24)); \
+	})
+
+#ifdef __LITTLE_ENDIAN
+# define swap_16(x) (x)
+# define swap_32(x) (x)
+#else
+# define swap_16(x) __swap_16(x)
+# define swap_32(x) __swap_32(x)
+#endif
+
+/*
+ * Calling this entity a "pipe" is glorifying it. A USB pipe
+ * is something embarrassingly simple: it basically consists
+ * of the following information:
+ *  - device number (7 bits)
+ *  - endpoint number (4 bits)
+ *  - current Data0/1 state (1 bit)
+ *  - direction (1 bit)
+ *  - speed (2 bits)
+ *  - max packet size (2 bits: 8, 16, 32 or 64)
+ *  - pipe type (2 bits: control, interrupt, bulk, isochronous)
+ *
+ * That's 18 bits. Really. Nothing more. And the USB people have
+ * documented these eighteen bits as some kind of glorious
+ * virtual data structure.
+ *
+ * Let's not fall in that trap. We'll just encode it as a simple
+ * unsigned int. The encoding is:
+ *
+ *  - max size:		bits 0-1	(00 = 8, 01 = 16, 10 = 32, 11 = 64)
+ *  - direction:	bit 7		(0 = Host-to-Device [Out],
+ *					(1 = Device-to-Host [In])
+ *  - device:		bits 8-14
+ *  - endpoint:		bits 15-18
+ *  - Data0/1:		bit 19
+ *  - speed:		bit 26		(0 = Full, 1 = Low Speed, 2 = High)
+ *  - pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt,
+ *					 10 = control, 11 = bulk)
+ *
+ * Why? Because it's arbitrary, and whatever encoding we select is really
+ * up to us. This one happens to share a lot of bit positions with the UHCI
+ * specification, so that much of the uhci driver can just mask the bits
+ * appropriately.
+ */
+/* Create various pipes... */
+#define create_pipe(dev,endpoint) \
+		(((dev)->devnum << 8) | (endpoint << 15) | \
+		((dev)->speed << 26) | (dev)->maxpacketsize)
+#define default_pipe(dev) ((dev)->speed << 26)
+
+#define usb_sndctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev))
+#define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev) | \
+					 USB_DIR_IN)
+
+/* The D0/D1 toggle bits */
+#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
+#define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << ep))
+#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
+						((dev)->toggle[out] & \
+						 ~(1 << ep)) | ((bit) << ep))
+
+/* Endpoint halt control/status */
+#define usb_endpoint_out(ep_dir)	(((ep_dir >> 7) & 1) ^ 1)
+#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep)))
+#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
+#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
+
+#define usb_packetid(pipe)	(((pipe) & USB_DIR_IN) ? USB_PID_IN : \
+				 USB_PID_OUT)
+
+#define usb_pipeout(pipe)	((((pipe) >> 7) & 1) ^ 1)
+#define usb_pipein(pipe)	(((pipe) >> 7) & 1)
+#define usb_pipedevice(pipe)	(((pipe) >> 8) & 0x7f)
+#define usb_pipe_endpdev(pipe)	(((pipe) >> 8) & 0x7ff)
+#define usb_pipeendpoint(pipe)	(((pipe) >> 15) & 0xf)
+#define usb_pipedata(pipe)	(((pipe) >> 19) & 1)
+#define usb_pipespeed(pipe)	(((pipe) >> 26) & 3)
+#define usb_pipeslow(pipe)	(usb_pipespeed(pipe) == USB_SPEED_LOW)
+#define usb_pipetype(pipe)	(((pipe) >> 30) & 3)
+#define usb_pipeisoc(pipe)	(usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
+#define usb_pipeint(pipe)	(usb_pipetype((pipe)) == PIPE_INTERRUPT)
+#define usb_pipecontrol(pipe)	(usb_pipetype((pipe)) == PIPE_CONTROL)
+#define usb_pipebulk(pipe)	(usb_pipetype((pipe)) == PIPE_BULK)
+
+
+/*************************************************************************
+ * Hub Stuff
+ */
+struct usb_port_status {
+	unsigned short wPortStatus;
+	unsigned short wPortChange;
+} __attribute__ ((packed));
+
+struct usb_hub_status {
+	unsigned short wHubStatus;
+	unsigned short wHubChange;
+} __attribute__ ((packed));
+
+
+/* Hub descriptor */
+struct usb_hub_descriptor {
+	unsigned char  bLength;
+	unsigned char  bDescriptorType;
+	unsigned char  bNbrPorts;
+	unsigned short wHubCharacteristics;
+	unsigned char  bPwrOn2PwrGood;
+	unsigned char  bHubContrCurrent;
+	unsigned char  DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
+	unsigned char  PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
+	/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
+	   bitmaps that hold max 255 entries. (bit0 is ignored) */
+} __attribute__ ((packed));
+
+
+struct usb_hub_device {
+	struct usb_device *pusb_dev;
+	struct usb_hub_descriptor desc;
+};
+
+#endif /*_USB_H_ */
diff --git a/usb/store/usb_defs.h b/usb/store/usb_defs.h
new file mode 100644
index 0000000..8032e57
--- /dev/null
+++ b/usb/store/usb_defs.h
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_DEFS_H_
+#define _USB_DEFS_H_
+
+/* USB constants */
+
+/* Device and/or Interface Class codes */
+#define USB_CLASS_PER_INTERFACE  0	/* for DeviceClass */
+#define USB_CLASS_AUDIO          1
+#define USB_CLASS_COMM           2
+#define USB_CLASS_HID            3
+#define USB_CLASS_PRINTER	       7
+#define USB_CLASS_MASS_STORAGE   8
+#define USB_CLASS_HUB            9
+#define USB_CLASS_DATA           10
+#define USB_CLASS_VENDOR_SPEC    0xff
+
+/* some HID sub classes */
+#define USB_SUB_HID_NONE        0
+#define USB_SUB_HID_BOOT        1
+
+/* some UID Protocols */
+#define USB_PROT_HID_NONE       0
+#define USB_PROT_HID_KEYBOARD   1
+#define USB_PROT_HID_MOUSE      2
+
+
+/* Sub STORAGE Classes */
+#define US_SC_RBC              1		/* Typically, flash devices */
+#define US_SC_8020             2		/* CD-ROM */
+#define US_SC_QIC              3		/* QIC-157 Tapes */
+#define US_SC_UFI              4		/* Floppy */
+#define US_SC_8070             5		/* Removable media */
+#define US_SC_SCSI             6		/* Transparent */
+#define US_SC_MIN              US_SC_RBC
+#define US_SC_MAX              US_SC_SCSI
+
+/* STORAGE Protocols */
+#define US_PR_CB               1		/* Control/Bulk w/o interrupt */
+#define US_PR_CBI              0		/* Control/Bulk/Interrupt */
+#define US_PR_BULK             0x50		/* bulk only */
+
+/* USB types */
+#define USB_TYPE_STANDARD   (0x00 << 5)
+#define USB_TYPE_CLASS      (0x01 << 5)
+#define USB_TYPE_VENDOR     (0x02 << 5)
+#define USB_TYPE_RESERVED   (0x03 << 5)
+
+/* USB recipients */
+#define USB_RECIP_DEVICE      0x00
+#define USB_RECIP_INTERFACE   0x01
+#define USB_RECIP_ENDPOINT    0x02
+#define USB_RECIP_OTHER       0x03
+
+/* USB directions */
+#define USB_DIR_OUT           0
+#define USB_DIR_IN            0x80
+
+/* USB device speeds */
+#define USB_SPEED_FULL		0x0	/* 12Mbps */
+#define USB_SPEED_LOW		0x1	/* 1.5Mbps */
+#define USB_SPEED_HIGH		0x2	/* 480Mbps */
+#define USB_SPEED_RESERVED	0x3
+
+/* Descriptor types */
+#define USB_DT_DEVICE        0x01
+#define USB_DT_CONFIG        0x02
+#define USB_DT_STRING        0x03
+#define USB_DT_INTERFACE     0x04
+#define USB_DT_ENDPOINT      0x05
+
+#define USB_DT_HID          (USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT       (USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL     (USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB          (USB_TYPE_CLASS | 0x09)
+
+/* Descriptor sizes per descriptor type */
+#define USB_DT_DEVICE_SIZE      18
+#define USB_DT_CONFIG_SIZE      9
+#define USB_DT_INTERFACE_SIZE   9
+#define USB_DT_ENDPOINT_SIZE    7
+#define USB_DT_ENDPOINT_AUDIO_SIZE  9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE  7
+#define USB_DT_HID_SIZE         9
+
+/* Endpoints */
+#define USB_ENDPOINT_NUMBER_MASK  0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK     0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK 0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL  0
+#define USB_ENDPOINT_XFER_ISOC     1
+#define USB_ENDPOINT_XFER_BULK     2
+#define USB_ENDPOINT_XFER_INT      3
+
+/* USB Packet IDs (PIDs) */
+#define USB_PID_UNDEF_0             0xf0
+#define USB_PID_OUT                 0xe1
+#define USB_PID_ACK                 0xd2
+#define USB_PID_DATA0               0xc3
+#define USB_PID_UNDEF_4             0xb4
+#define USB_PID_SOF                 0xa5
+#define USB_PID_UNDEF_6             0x96
+#define USB_PID_UNDEF_7             0x87
+#define USB_PID_UNDEF_8             0x78
+#define USB_PID_IN                  0x69
+#define USB_PID_NAK                 0x5a
+#define USB_PID_DATA1               0x4b
+#define USB_PID_PREAMBLE            0x3c
+#define USB_PID_SETUP               0x2d
+#define USB_PID_STALL               0x1e
+#define USB_PID_UNDEF_F             0x0f
+
+/* Standard requests */
+#define USB_REQ_GET_STATUS          0x00
+#define USB_REQ_CLEAR_FEATURE       0x01
+#define USB_REQ_SET_FEATURE         0x03
+#define USB_REQ_SET_ADDRESS         0x05
+#define USB_REQ_GET_DESCRIPTOR      0x06
+#define USB_REQ_SET_DESCRIPTOR      0x07
+#define USB_REQ_GET_CONFIGURATION   0x08
+#define USB_REQ_SET_CONFIGURATION   0x09
+#define USB_REQ_GET_INTERFACE       0x0A
+#define USB_REQ_SET_INTERFACE       0x0B
+#define USB_REQ_SYNCH_FRAME         0x0C
+
+/* HID requests */
+#define USB_REQ_GET_REPORT          0x01
+#define USB_REQ_GET_IDLE            0x02
+#define USB_REQ_GET_PROTOCOL        0x03
+#define USB_REQ_SET_REPORT          0x09
+#define USB_REQ_SET_IDLE            0x0A
+#define USB_REQ_SET_PROTOCOL        0x0B
+
+
+/* "pipe" definitions */
+
+#define PIPE_ISOCHRONOUS    0
+#define PIPE_INTERRUPT      1
+#define PIPE_CONTROL        2
+#define PIPE_BULK           3
+#define PIPE_DEVEP_MASK     0x0007ff00
+
+#define USB_ISOCHRONOUS    0
+#define USB_INTERRUPT      1
+#define USB_CONTROL        2
+#define USB_BULK           3
+
+/* USB-status codes: */
+#define USB_ST_ACTIVE           0x1		/* TD is active */
+#define USB_ST_STALLED          0x2		/* TD is stalled */
+#define USB_ST_BUF_ERR          0x4		/* buffer error */
+#define USB_ST_BABBLE_DET       0x8		/* Babble detected */
+#define USB_ST_NAK_REC          0x10	/* NAK Received*/
+#define USB_ST_CRC_ERR          0x20	/* CRC/timeout Error */
+#define USB_ST_BIT_ERR          0x40	/* Bitstuff error */
+#define USB_ST_NOT_PROC         0x80000000L	/* Not yet processed */
+
+
+/*************************************************************************
+ * Hub defines
+ */
+
+/*
+ * Hub request types
+ */
+
+#define USB_RT_HUB	(USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT	(USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+/*
+ * Hub Class feature numbers
+ */
+#define C_HUB_LOCAL_POWER   0
+#define C_HUB_OVER_CURRENT  1
+
+/*
+ * Port feature numbers
+ */
+#define USB_PORT_FEAT_CONNECTION     0
+#define USB_PORT_FEAT_ENABLE         1
+#define USB_PORT_FEAT_SUSPEND        2
+#define USB_PORT_FEAT_OVER_CURRENT   3
+#define USB_PORT_FEAT_RESET          4
+#define USB_PORT_FEAT_POWER          8
+#define USB_PORT_FEAT_LOWSPEED       9
+#define USB_PORT_FEAT_HIGHSPEED      10
+#define USB_PORT_FEAT_C_CONNECTION   16
+#define USB_PORT_FEAT_C_ENABLE       17
+#define USB_PORT_FEAT_C_SUSPEND      18
+#define USB_PORT_FEAT_C_OVER_CURRENT 19
+#define USB_PORT_FEAT_C_RESET        20
+
+/* wPortStatus bits */
+#define USB_PORT_STAT_CONNECTION    0x0001
+#define USB_PORT_STAT_ENABLE        0x0002
+#define USB_PORT_STAT_SUSPEND       0x0004
+#define USB_PORT_STAT_OVERCURRENT   0x0008
+#define USB_PORT_STAT_RESET         0x0010
+#define USB_PORT_STAT_POWER         0x0100
+#define USB_PORT_STAT_LOW_SPEED     0x0200
+#define USB_PORT_STAT_HIGH_SPEED    0x0400	/* support for EHCI */
+#define USB_PORT_STAT_SPEED	\
+	(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
+
+/* wPortChange bits */
+#define USB_PORT_STAT_C_CONNECTION  0x0001
+#define USB_PORT_STAT_C_ENABLE      0x0002
+#define USB_PORT_STAT_C_SUSPEND     0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET       0x0010
+
+/* wHubCharacteristics (masks) */
+#define HUB_CHAR_LPSM               0x0003
+#define HUB_CHAR_COMPOUND           0x0004
+#define HUB_CHAR_OCPM               0x0018
+
+/*
+ *Hub Status & Hub Change bit masks
+ */
+#define HUB_STATUS_LOCAL_POWER	0x0001
+#define HUB_STATUS_OVERCURRENT	0x0002
+
+#define HUB_CHANGE_LOCAL_POWER	0x0001
+#define HUB_CHANGE_OVERCURRENT	0x0002
+
+#endif /*_USB_DEFS_H_ */
diff --git a/usb/store/usb_mem.c b/usb/store/usb_mem.c
new file mode 100644
index 0000000..7397d12
--- /dev/null
+++ b/usb/store/usb_mem.c
@@ -0,0 +1,220 @@
+/*
+ * usb_mem.c
+ *
+ * based from Emutos / BDOS
+ * 
+ * Copyright (c) 2001 Lineo, Inc.
+ *
+ * Authors: Karl T. Braun, Martin Doering, Laurent Vogel
+ *
+ * This file is distributed under the GPL, version 2 or at your
+ * option any later version.
+ */
+
+#include <mint/errno.h>
+#include <mint/osbind.h> 
+#include <string.h>
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#define USB_BUFFER_SIZE 0x10000
+
+static void *usb_buffer;
+
+/* MD - Memory Descriptor */
+
+#define MD struct _md_
+
+MD
+{
+	MD *m_link;
+	long m_start;
+	long m_length;
+};
+
+/* MPB - Memory Partition Block */
+
+#define MPB struct _mpb
+
+MPB
+{
+	MD *mp_mfl;
+	MD *mp_mal;
+	MD *mp_rover;
+};
+
+#define MAXMD 100
+
+static int count_md;
+static MD tab_md[MAXMD];
+static MPB pmd;
+
+static MD *ffit(long amount, MPB *mp)
+{
+	MD *p,*q,*p1;                    /* free list is composed of MD's */
+	int maxflg;
+	long maxval;
+	if(amount != -1)
+	{
+		amount += 15;                  /* 16 bytes alignment */
+		amount &= 0xFFFFFFF0;
+	}
+	if((q = mp->mp_rover) == 0)      /* get rotating pointer */
+		return(0) ;
+	maxval = 0;
+	maxflg = (amount == -1 ? TRUE : FALSE) ;
+	p = q->m_link;                   /* start with next MD */
+	do /* search the list for an MD with enough space */
+	{
+		if(p == 0)
+		{
+			/*  at end of list, wrap back to start  */
+			q = (MD *) &mp->mp_mfl;      /*  q => mfl field  */
+			p = q->m_link;               /*  p => 1st MD     */
+		}
+		if((!maxflg) && (p->m_length >= amount))
+		{
+			/*  big enough */
+			if(p->m_length == amount)
+				q->m_link = p->m_link;     /* take the whole thing */
+			else
+			{
+				/* break it up - 1st allocate a new
+				   MD to describe the remainder */
+				if(count_md >= MAXMD)
+					return(0);
+				p1 = &tab_md[count_md++];
+				/* init new MD */
+				p1->m_length = p->m_length - amount;
+				p1->m_start = p->m_start + amount;
+				p1->m_link = p->m_link;
+				p->m_length = amount;      /* adjust allocated block */
+				q->m_link = p1;
+			}
+			/* link allocate block into allocated list,
+			    mark owner of block, & adjust rover  */
+			p->m_link = mp->mp_mal;
+			mp->mp_mal = p;
+			mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
+			return(p);                   /* got some */
+		}
+		else if(p->m_length > maxval)
+			maxval = p->m_length;
+		p = ( q=p )->m_link;
+	}
+	while(q != mp->mp_rover);
+	/*  return either the max, or 0 (error)  */
+	if(maxflg)
+	{
+		maxval -= 15; /* 16 bytes alignment */
+		if(maxval < 0)
+			maxval = 0;
+		else
+			maxval &= 0xFFFFFFF0;
+	}
+	return(maxflg ? (MD *) maxval : 0);
+}
+
+static void freeit(MD *m, MPB *mp)
+{
+	MD *p, *q;
+	q = 0;
+	for(p = mp->mp_mfl; p ; p = (q=p) -> m_link)
+	{
+		if(m->m_start <= p->m_start)
+			break;
+	}
+	m->m_link = p;
+	if(q)
+		q->m_link = m;
+	else
+		mp->mp_mfl = m;
+	if(!mp->mp_rover)
+		mp->mp_rover = m;
+	if(p)
+	{
+		if(m->m_start + m->m_length == p->m_start)
+		{ /* join to higher neighbor */
+			m->m_length += p->m_length;
+			m->m_link = p->m_link;
+			if(p == mp->mp_rover)
+				mp->mp_rover = m;
+			if(count_md>=0)
+				count_md--;
+		}
+	}
+	if(q)
+	{
+		if(q->m_start + q->m_length == m->m_start)
+		{ /* join to lower neighbor */
+			q->m_length += m->m_length;
+			q->m_link = m->m_link;
+			if(m == mp->mp_rover)
+				mp->mp_rover = q;
+			if(count_md>=0)
+				count_md--;
+		}
+	}
+}
+
+int usb_free(void *addr)
+{
+	MD *p,**q;
+	MPB *mpb;
+	mpb = &pmd;
+	if(usb_buffer == NULL)
+		return(EFAULT);
+	for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
+	{
+		if((long)addr == p->m_start)
+			break;
+	}
+	if(!p)
+		return(EFAULT);
+	*q = p->m_link;
+	freeit(p,mpb);
+	return(0);
+}
+
+void *usb_malloc(long amount)
+{
+	MD *m;
+	if(usb_buffer == NULL)
+		return(NULL);
+	if(amount == -1L)
+		return((void *)ffit(-1L,&pmd));
+	if(amount <= 0 )
+		return(0);
+	if((amount & 1))
+		amount++;
+	m = ffit(amount,&pmd);
+	if(m == NULL)
+		return(NULL);
+	return((void *)m->m_start);
+}
+
+int usb_mem_init(void)
+{
+	usb_buffer = (void *)Mxalloc(USB_BUFFER_SIZE + 16, 0); /* STRAM - cache in writethough */
+	if(usb_buffer == NULL)
+		return(-1);
+	pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
+	tab_md[0].m_link = (MD *)NULL;
+	tab_md[0].m_start = ((long)usb_buffer + 15) & ~15;
+	tab_md[0].m_length = USB_BUFFER_SIZE;	
+	pmd.mp_mal = (MD *)NULL;
+	count_md = 1;
+	return(0);
+}
+
+void usb_mem_stop(void)
+{
+	if(usb_buffer != NULL)
+		Mfree(usb_buffer);
+}
+
diff --git a/usb/store/usb_storage.c b/usb/store/usb_storage.c
new file mode 100644
index 0000000..e48724e
--- /dev/null
+++ b/usb/store/usb_storage.c
@@ -0,0 +1,1632 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *
+ * Most of this source has been derived from the Linux USB
+ * project:
+ *   (c) 1999-2002 Matthew Dharm (mdharm-usb@one-eyed-alien.net)
+ *   (c) 2000 David L. Brown, Jr. (usb-storage@davidb.org)
+ *   (c) 1999 Michael Gee (michael@linuxspecific.com)
+ *   (c) 2000 Yggdrasil Computing, Inc.
+ *
+ *
+ * Adapted for U-Boot:
+ *   (C) Copyright 2001 Denis Peter, MPL AG Switzerland
+ *
+ * For BBB support (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ * BBB support based on /sys/dev/usb/umass.c from
+ * FreeBSD.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Note:
+ * Currently only the CBI transport protocoll has been implemented, and it
+ * is only tested with a TEAC USB Floppy. Other Massstorages with CBI or CB
+ * transport protocoll may work as well.
+ */
+/*
+ * New Note:
+ * Support for USB Mass Storage Devices (BBB) has been added. It has
+ * only been tested with USB memory sticks.
+ */
+
+#include "config.h"
+#include "usb.h"
+#include "scsi.h"
+#include "super.h"
+#include "debug.h"
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) \
+			|| defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+
+/*
+ * Extra debug to the one availble in config.h
+ * These three extra debug levels go always to the log file
+ * uncomment them if you want them on
+ */
+//#define USB_STOR_DEBUG
+//#define BBB_COMDAT_TRACE
+//#define BBB_XPORT_TRACE
+
+
+extern void udelay(long usec);
+extern void ltoa(char *buf, long n, unsigned long base);
+
+/* direction table -- this indicates the direction of the data
+ * transfer for each command code -- a 1 indicates input
+ */
+unsigned char us_direction[256/8] = {
+	0x28, 0x81, 0x14, 0x14, 0x20, 0x01, 0x90, 0x77,
+	0x0C, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+#define US_DIRECTION(x) ((us_direction[x>>3] >> (x & 7)) & 1)
+
+static unsigned char *usb_stor_buf;
+static ccb usb_ccb;
+
+/*
+ * CBI style
+ */
+
+#define US_CBI_ADSC		0
+
+/*
+ * BULK only
+ */
+#define US_BBB_RESET		0xff
+#define US_BBB_GET_MAX_LUN	0xfe
+
+/* Command Block Wrapper */
+typedef struct {
+	__u32		dCBWSignature;
+#	define CBWSIGNATURE	0x43425355
+	__u32		dCBWTag;
+	__u32		dCBWDataTransferLength;
+	__u8		bCBWFlags;
+#	define CBWFLAGS_OUT	0x00
+#	define CBWFLAGS_IN	0x80
+	__u8		bCBWLUN;
+	__u8		bCDBLength;
+#	define CBWCDBLENGTH	16
+	__u8		CBWCDB[CBWCDBLENGTH];
+} umass_bbb_cbw_t;
+#define UMASS_BBB_CBW_SIZE	31
+static __u32 CBWTag;
+
+/* Command Status Wrapper */
+typedef struct {
+	__u32		dCSWSignature;
+#	define CSWSIGNATURE	0x53425355
+	__u32		dCSWTag;
+	__u32		dCSWDataResidue;
+	__u8		bCSWStatus;
+#	define CSWSTATUS_GOOD	0x0
+#	define CSWSTATUS_FAILED 0x1
+#	define CSWSTATUS_PHASE	0x2
+} umass_bbb_csw_t;
+#define UMASS_BBB_CSW_SIZE	13
+
+//#define USB_MAX_STOR_DEV 5 /* GALVEZ: Defined in usb.h */
+static int usb_max_devs; /* number of highest available usb device */
+
+static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV];
+
+struct us_data;
+typedef int (*trans_cmnd)(ccb *cb, struct us_data *data);
+typedef int (*trans_reset)(struct us_data *data);
+
+struct us_data {
+	struct usb_device *pusb_dev;	 /* this usb_device */
+
+	unsigned int	flags;			/* from filter initially */
+	unsigned char	ifnum;			/* interface number */
+	unsigned char	ep_in;			/* in endpoint */
+	unsigned char	ep_out;			/* out ....... */
+	unsigned char	ep_int;			/* interrupt . */
+	unsigned char	subclass;		/* as in overview */
+	unsigned char	protocol;		/* .............. */
+	unsigned char	attention_done;		/* force attn on first cmd */
+	unsigned short	ip_data;		/* interrupt data */
+	int		action;			/* what to do */
+	int		ip_wanted;		/* needed */
+	int		*irq_handle;		/* for USB int requests */
+	unsigned int	irqpipe;	 	/* pipe for release_irq */
+	unsigned char	irqmaxp;		/* max packed for irq Pipe */
+	unsigned char	irqinterval;		/* Intervall for IRQ Pipe */
+	ccb		*srb;			/* current srb */
+	trans_reset	transport_reset;	/* reset routine */
+	trans_cmnd	transport;		/* transport routine */
+};
+
+static struct us_data usb_stor[USB_MAX_STOR_DEV];
+
+#define USB_STOR_TRANSPORT_GOOD	   0
+#define USB_STOR_TRANSPORT_FAILED -1
+#define USB_STOR_TRANSPORT_ERROR  -2
+
+#define DEFAULT_SECTOR_SIZE 512
+
+#define DOS_PART_TBL_OFFSET	0x1be
+#define DOS_PART_MAGIC_OFFSET	0x1fe
+#define DOS_PBR_FSTYPE_OFFSET	0x36
+#define DOS_PBR_MEDIA_TYPE_OFFSET	0x15
+#define DOS_MBR	0
+#define DOS_PBR	1
+#define DOS_FS_TYPE_OFFSET 0x36
+
+typedef struct dos_partition {
+	unsigned char boot_ind;		/* 0x80 - active			*/
+	unsigned char head;		/* starting head			*/
+	unsigned char sector;		/* starting sector			*/
+	unsigned char cyl;		/* starting cylinder			*/
+	unsigned char sys_ind;		/* What partition type			*/
+	unsigned char end_head;		/* end head				*/
+	unsigned char end_sector;	/* end sector				*/
+	unsigned char end_cyl;		/* end cylinder				*/
+	unsigned char start4[4];	/* starting sector counting from 0	*/
+	unsigned char size4[4];		/* nr of sectors in partition		*/
+} dos_partition_t;
+
+typedef struct disk_partition {
+	unsigned long type;
+	unsigned long	start; /* # of first block in partition	*/
+	unsigned long	size;  /* number of blocks in partition	*/
+	unsigned long	blksz; /* block size in bytes			*/
+} disk_partition_t;
+
+//extern unsigned long swap_long(unsigned long val);
+#define le32_to_int(a) swap_32(*(unsigned long *)a)
+
+int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc);
+int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss);
+unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer);
+unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer);
+struct usb_device * usb_get_dev_index(int index);
+void uhci_show_temp_int_td(void);
+
+block_dev_desc_t *usb_stor_get_dev(int idx)
+{
+	return(idx < USB_MAX_STOR_DEV) ? &usb_dev_desc[idx] : NULL;
+}
+
+void init_part(block_dev_desc_t *dev_desc)
+{
+	unsigned char *buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE);
+	if(buffer == NULL)
+		return;
+	if((dev_desc->block_read(dev_desc->dev, 0, 1, (unsigned long *)buffer) != 1)
+	 || (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa))
+	{
+		usb_free(buffer);
+		return;
+	}
+	dev_desc->part_type = PART_TYPE_DOS;
+	DEBUG_STORAGE("DOS partition table found\r\n");
+#ifdef USB_STOR_DEBUG			
+	{
+		debug_init("usb.log");
+		int j;
+		for(j = 0; j < 512; j++)
+		{
+			if((j & 15) == 0)
+					debug("\r\n%04X ", j);
+			debug("%02X ", buffer[j]);
+			if((j & 15) == 15)
+			{
+				int k;
+					for(k = j-15; k <= j; k++)
+				{
+					if(buffer[k] < ' ' || buffer[k] >= 127)
+						debug(".");
+					else 
+						debug("%c", buffer[k]);
+				}
+			}
+		}
+		debug("\r\n");
+		debug_exit();
+	}			
+#endif	
+	usb_free(buffer);
+}
+
+static inline int is_extended(int part_type)
+{
+	return(part_type == 0x5 || part_type == 0xf || part_type == 0x85);
+}
+
+/*  Print a partition that is relative to its Extended partition table
+ */
+static int get_partition_info_extended(block_dev_desc_t *dev_desc, int ext_part_sector, int relative, int part_num, int which_part, disk_partition_t *info)
+{
+	dos_partition_t *pt;
+	int i;
+	unsigned char *buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE);
+
+	if(buffer == NULL)
+		return -1;
+	if(dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (unsigned long *)buffer) != 1)
+	{
+		DEBUG_STORAGE("Can't read partition table on %d:%d\r\n", dev_desc->dev, ext_part_sector);
+		usb_free(buffer);
+		return -1;
+	}
+	if(buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa)
+	{
+		DEBUG_STORAGE("bad MBR sector signature 0x%02x%02x\n", buffer[DOS_PART_MAGIC_OFFSET], buffer[DOS_PART_MAGIC_OFFSET + 1]);
+		usb_free(buffer);
+		return -1;
+	}
+	/* Print all primary/logical partitions */
+	pt = (dos_partition_t *)(buffer + DOS_PART_TBL_OFFSET);
+	for(i = 0; i < 4; i++, pt++)
+	{
+		/* fdisk does not show the extended partitions that are not in the MBR */
+		if((pt->sys_ind != 0) && (part_num == which_part) && (is_extended(pt->sys_ind) == 0))
+		{
+			info->type = (unsigned long)pt->sys_ind;
+			info->blksz = 512;
+			info->start = ext_part_sector + le32_to_int(pt->start4);
+			info->size = le32_to_int(pt->size4);
+			DEBUG_STORAGE("DOS partition at offset 0x%lx, size 0x%lx, type 0x%x %s\r\n", 
+					info->start, info->size, pt->sys_ind, 
+					(is_extended(pt->sys_ind) ? " Extd" : ""));
+			usb_free(buffer);
+			return 0;
+		}
+		/* Reverse engr the fdisk part# assignment rule! */
+		if((ext_part_sector == 0) || (pt->sys_ind != 0 && !is_extended (pt->sys_ind)))
+			part_num++;
+	}
+	/* Follows the extended partitions */
+	pt = (dos_partition_t *)(buffer + DOS_PART_TBL_OFFSET);
+	for(i = 0; i < 4; i++, pt++)
+	{
+		if(is_extended(pt->sys_ind))
+		{
+			int lba_start = le32_to_int(pt->start4) + relative;
+			usb_free(buffer);
+			return get_partition_info_extended(dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, part_num, which_part, info);
+		}
+	}
+	usb_free(buffer);
+	return -1;
+}
+
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no, unsigned long *part_type, unsigned long *part_offset, unsigned long *part_size)
+{
+	unsigned char *buffer;
+	disk_partition_t info;
+
+	if(!dev_desc->block_read)
+		return -1;
+		
+	buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE);
+	if(buffer == NULL)
+		return -1;
+	/* check if we have a MBR (on floppies we have only a PBR) */
+		
+	if(dev_desc->block_read(dev_desc->dev, 0, 1, (unsigned long *)buffer) != 1)
+	{
+		DEBUG_STORAGE("Can't read from device %d\r\n", dev_desc->dev);
+		usb_free(buffer);
+		return -1;
+	}
+	
+	if(buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa)
+	{
+		/* no signature found */
+		usb_free(buffer);
+		return -1;
+	}
+	
+	/* First we assume, there is a MBR */
+	if(!get_partition_info_extended(dev_desc, 0, 0, 1, part_no, &info))
+	{
+		*part_type = info.type;
+		*part_offset = info.start;
+		*part_size = info.size;
+	}
+	else if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3))
+	{
+		/* ok, we assume we are on a PBR only */
+		*part_type = 0;
+		*part_offset = 0;
+		*part_size = 0;
+	}
+	else
+	{
+		DEBUG_STORAGE("Partition %d not valid on device %d\r\n", part_no, dev_desc->dev);
+		usb_free(buffer);
+		return -1;
+	}
+	usb_free(buffer);
+	return 0;
+}
+
+#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+
+void dev_print(block_dev_desc_t *dev_desc)
+{
+#ifdef CONFIG_LBA48
+	uint64_t lba512; /* number of blocks if 512bytes block size */
+#else
+	lbaint_t lba512;
+#endif
+	if(dev_desc->type == DEV_TYPE_UNKNOWN)
+	{
+		printf("not available\r\n");
+		DEBUG_STORAGE("not available\r\n");
+		return;
+	}
+	DEBUG_STORAGE("Vendor: %s Rev: %s Prod: %s\r\n", dev_desc->vendor, dev_desc->revision, dev_desc->product);
+	DEBUG_STORAGE("\r\n");
+	printf("Vendor: %s Rev: %s Prod: %s\r\n", dev_desc->vendor, dev_desc->revision, dev_desc->product);
+	printf("\r\n");
+	if((dev_desc->lba * dev_desc->blksz) > 0L)
+	{
+		unsigned long mb, mb_quot, mb_rem, gb, gb_quot, gb_rem;
+		lbaint_t lba = dev_desc->lba;
+		lba512 = (lba * (dev_desc->blksz / 512));
+		mb = (10 * lba512) / 2048;	/* 2048 = (1024 * 1024) / 512 MB */
+		/* round to 1 digit */
+		mb_quot	= mb / 10;
+		mb_rem	= mb - (10 * mb_quot);
+		gb = mb / 1024;
+		gb_quot	= gb / 10;
+		gb_rem	= gb - (10 * gb_quot);
+#ifdef CONFIG_LBA48
+		if(dev_desc->lba48)
+			printf("Supports 48-bit addressing\r\n");
+#endif
+		DEBUG_STORAGE("Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\r\n", mb_quot, mb_rem, gb_quot, gb_rem, (unsigned long)lba, dev_desc->blksz);
+		printf("Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\r\n", mb_quot, mb_rem, gb_quot, gb_rem, (unsigned long)lba, dev_desc->blksz);
+	}
+	else {
+		DEBUG_STORAGE("Capacity: not available\r\n");
+		printf("Capacity: not available\r\n");
+	}
+}
+
+/*******************************************************************************
+ * show info on storage devices; 'usb start/init' must be invoked earlier
+ * as we only retrieve structures populated during devices initialization
+ */
+int usb_stor_info(void)
+{
+	int i;
+	if(usb_max_devs > 0)
+	{
+		for(i = 0; i < usb_max_devs; i++)
+		{
+			DEBUG_STORAGE("Device %d: ", i);
+			printf("Device %d: ", i);
+			dev_print(&usb_dev_desc[i]);
+		}
+		return 0;
+	}
+	DEBUG_STORAGE("No storage devices\r\n");
+	printf("No storage devices\r\n");
+	return 1;
+}
+
+#endif /* CONFIG_USB_OHCI */
+
+/*******************************************************************************
+ * scan the usb and reports device info to the user
+ * returns current device or -1 if no
+ */
+int usb_stor_scan(void)
+{
+	unsigned char i;
+	struct usb_device *dev;
+	DEBUG_STORAGE("usb_stor_scan()");		/* Galvez: Debug trace */
+	if(usb_stor_buf == NULL)
+		usb_stor_buf = (unsigned char *)usb_malloc(512);
+	if(usb_stor_buf == NULL)
+		return -1;
+	memset(usb_stor_buf, 0, sizeof(usb_stor_buf));
+	usb_disable_asynch(1); /* asynch transfer not allowed */
+	for(i = 0; i < USB_MAX_STOR_DEV; i++)
+	{
+		memset(&usb_dev_desc[i], 0, sizeof(block_dev_desc_t));
+		usb_dev_desc[i].target = 0xff;
+		usb_dev_desc[i].if_type = IF_TYPE_USB;
+		usb_dev_desc[i].dev = i;
+		usb_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		usb_dev_desc[i].block_read = usb_stor_read;
+		usb_dev_desc[i].block_write = usb_stor_write;
+	}
+	usb_max_devs = 0;
+	for(i = 0; i < USB_MAX_DEVICE; i++)
+	{
+		dev = usb_get_dev_index(i); /* get device */
+		if(dev == NULL)
+			break; /* no more devices avaiable */
+		DEBUG_STORAGE("Device %d\r\n", i);
+		if(usb_storage_probe(dev, 0, &usb_stor[usb_max_devs]))
+		{
+			/* ok, it is a storage devices
+			 * get info and fill it in
+			 */
+			if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs]))
+				usb_max_devs++;
+		}
+		/* if storage device */
+		if(usb_max_devs == USB_MAX_STOR_DEV)
+		{
+			printf("Max USB Storage Device reached: %d stopping\r\n", usb_max_devs);
+			break;
+		}
+	} /* for */
+	usb_disable_asynch(0); /* asynch transfer allowed */
+	DEBUG_STORAGE("%d Storage Device(s) found\r\n", usb_max_devs);
+	printf("%d Storage Device(s) found\r\n", usb_max_devs);
+	if(usb_max_devs > 0)
+		return 0;
+	return -1;
+}
+
+static int usb_stor_irq(struct usb_device *dev)
+{
+	struct us_data *us;
+	us = (struct us_data *)dev->privptr;
+	if(us->ip_wanted)
+		us->ip_wanted = 0;
+	return 0;
+}
+
+#ifdef USB_STOR_DEBUG
+
+static void usb_show_srb(ccb *pccb)
+{
+	int i;
+	debug_init("usb.log");
+	debug("SRB: len %d datalen 0x%lX\r\n ", pccb->cmdlen, pccb->datalen);
+	for (i = 0; i < 12; i++)
+		debug("%02X ", pccb->cmd[i]);
+	debug("\r\n");
+	debug_exit();
+}
+
+static void display_int_status(unsigned long tmp)
+{
+	debug_init("usb.log");
+	debug("Status: %s %s %s %s %s %s %s\r\n",
+		(tmp & USB_ST_ACTIVE) ? "Active" : "",
+		(tmp & USB_ST_STALLED) ? "Stalled" : "",
+		(tmp & USB_ST_BUF_ERR) ? "Buffer Error" : "",
+		(tmp & USB_ST_BABBLE_DET) ? "Babble Det" : "",
+		(tmp & USB_ST_NAK_REC) ? "NAKed" : "",
+		(tmp & USB_ST_CRC_ERR) ? "CRC Error" : "",
+		(tmp & USB_ST_BIT_ERR) ? "Bitstuff Error" : "");
+	debug_exit();
+}
+
+#endif
+
+/***********************************************************************
+ * Data transfer routines
+ ***********************************************************************/
+
+static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length)
+{
+	int max_size;
+	int this_xfer;
+	int result;
+	int partial;
+	int maxtry;
+	int stat;
+	/* determine the maximum packet size for these transfers */
+	max_size = usb_maxpacket(us->pusb_dev, pipe) * 16;
+	/* while we have data left to transfer */
+	while(length)
+	{
+		/* calculate how long this will be -- maximum or a remainder */
+		this_xfer = length > max_size ? max_size : length;
+		length -= this_xfer;
+		/* setup the retry counter */
+		maxtry = 10;
+		/* set up the transfer loop */
+		do
+		{
+			/* transfer the data */
+			DEBUG_STORAGE("Bulk xfer 0x%x(%d) try #%d\r\n", (unsigned int)buf, this_xfer, 11 - maxtry);
+			result = usb_bulk_msg(us->pusb_dev, pipe, buf, this_xfer, &partial, USB_CNTL_TIMEOUT * 5);
+			DEBUG_STORAGE("bulk_msg returned %d xferred %d/%d\r\n", result, partial, this_xfer);
+			if(us->pusb_dev->status != 0)
+			{
+				/* if we stall, we need to clear it before we go on */
+#ifdef USB_STOR_DEBUG
+				display_int_status(us->pusb_dev->status);
+#endif
+				if(us->pusb_dev->status & USB_ST_STALLED)
+				{
+					DEBUG_STORAGE("stalled ->clearing endpoint halt for pipe 0x%x\r\n", pipe);
+					stat = us->pusb_dev->status;
+					usb_clear_halt(us->pusb_dev, pipe);
+					us->pusb_dev->status = stat;
+					if(this_xfer == partial)
+					{
+						DEBUG_STORAGE("bulk transferred with error %lX, but data ok\r\n", us->pusb_dev->status);
+						return 0;
+					}
+					else
+						return result;
+				}
+				if(us->pusb_dev->status & USB_ST_NAK_REC)
+				{
+					DEBUG_STORAGE("Device NAKed bulk_msg\r\n");
+					return result;
+				}
+				DEBUG_STORAGE("bulk transferred with error");
+				if(this_xfer == partial)
+				{
+					DEBUG_STORAGE(" %ld, but data ok\r\n", us->pusb_dev->status);
+					return 0;
+				}
+				/* if our try counter reaches 0, bail out */
+				DEBUG_STORAGE(" %ld, data %d\r\n", us->pusb_dev->status, partial);
+				if(!maxtry--)
+					return result;
+			}
+			/* update to show what data was transferred */
+			this_xfer -= partial;
+			buf += partial;
+			/* continue until this transfer is done */
+		} while (this_xfer);
+	}
+	/* if we get here, we're done and successful */
+	return 0;
+}
+
+static int usb_stor_BBB_reset(struct us_data *us)
+{
+	int result;
+	unsigned int pipe;
+	/*
+	 * Reset recovery (5.3.4 in Universal Serial Bus Mass Storage Class)
+	 *
+	 * For Reset Recovery the host shall issue in the following order:
+	 * a) a Bulk-Only Mass Storage Reset
+	 * b) a Clear Feature HALT to the Bulk-In endpoint
+	 * c) a Clear Feature HALT to the Bulk-Out endpoint
+	 *
+	 * This is done in 3 steps.
+	 *
+	 * If the reset doesn't succeed, the device should be port reset.
+	 *
+	 * This comment stolen from FreeBSD's /sys/dev/usb/umass.c.
+	 */
+	DEBUG_STORAGE("BBB_reset\r\n");
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
+	 US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT * 5);
+	if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("RESET:stall\r\n");
+		return -1;
+	}
+	/* long wait for reset */
+	wait_ms(150);
+	DEBUG_STORAGE("BBB_reset result %d: status %lX reset\r\n", result, us->pusb_dev->status);
+	pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	result = usb_clear_halt(us->pusb_dev, pipe);
+	/* long wait for reset */
+	wait_ms(150);
+	DEBUG_STORAGE("BBB_reset result %d: status %lX clearing IN endpoint\r\n", result, us->pusb_dev->status);
+	/* long wait for reset */
+	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	result = usb_clear_halt(us->pusb_dev, pipe);
+	wait_ms(150);
+	DEBUG_STORAGE("BBB_reset result %d: status %lX clearing OUT endpoint\r\n", result, us->pusb_dev->status);
+	DEBUG_STORAGE("BBB_reset done\r\n");
+	return 0;
+}
+
+/* FIXME: this reset function doesn't really reset the port, and it
+ * should. Actually it should probably do what it's doing here, and
+ * reset the port physically
+ */
+static int usb_stor_CB_reset(struct us_data *us)
+{
+	unsigned char cmd[12];
+	int result;
+	DEBUG_STORAGE("CB_reset\r\n");
+	memset(cmd, 0xff, sizeof(cmd));
+	cmd[0] = SCSI_SEND_DIAG;
+	cmd[1] = 4;
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), 
+	 US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, cmd, sizeof(cmd), USB_CNTL_TIMEOUT * 5);
+	/* long wait for reset */
+	wait_ms(1500);
+	DEBUG_STORAGE("CB_reset result %d: status %lX clearing endpoint halt\r\n", result, us->pusb_dev->status);
+	usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_in));
+	usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_out));
+	DEBUG_STORAGE("CB_reset done\r\n");
+	return 0;
+}
+
+/*
+ * Set up the command for a BBB device. Note that the actual SCSI
+ * command is copied into cbw.CBWCDB.
+ */
+int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
+{
+	int result;
+	int actlen;
+	int dir_in;
+	unsigned int pipe;
+	umass_bbb_cbw_t *cbw = (umass_bbb_cbw_t *)usb_malloc(sizeof(umass_bbb_cbw_t));
+	if(cbw == NULL)
+	{
+		DEBUG_STORAGE("usb_stor_BBB_comdat: out of memory\r\n");
+		return -1;
+	}
+	dir_in = US_DIRECTION(srb->cmd[0]);
+	DEBUG_STORAGE("usb_stor_BBB_comdat: dir_in: %d\r\n",dir_in);
+#ifdef BBB_COMDAT_TRACE
+	debug_init ("usb.log");
+	debug("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\r\n", dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen, srb->pdata);
+	if(srb->cmdlen)
+	{
+		for(result = 0; result < srb->cmdlen; result++)
+			debug("cmd[%d] %#x ", result, srb->cmd[result]);
+		debug("\r\n");
+	}
+	debug_exit( );
+#endif
+	/* sanity checks */
+	if(!(srb->cmdlen <= CBWCDBLENGTH))
+	{
+		DEBUG_STORAGE("usb_stor_BBB_comdat: cmdlen too large\r\n");
+		usb_free(cbw);
+		return -1;
+	}
+	/* always OUT to the ep */
+	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	cbw->dCBWSignature = cpu_to_le32(CBWSIGNATURE);
+	cbw->dCBWTag = cpu_to_le32(CBWTag++);
+	cbw->dCBWDataTransferLength = cpu_to_le32(srb->datalen);
+	cbw->bCBWFlags = (dir_in ? CBWFLAGS_IN : CBWFLAGS_OUT);
+	cbw->bCBWLUN = srb->lun;
+	cbw->bCDBLength = srb->cmdlen;
+	/* copy the command data into the CBW command data buffer */
+	/* DST SRC LEN!!! */
+	memcpy(&cbw->CBWCDB, srb->cmd, srb->cmdlen);
+
+	result = usb_bulk_msg(us->pusb_dev, pipe, cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_CNTL_TIMEOUT * 5);
+	if(result < 0)
+	{	DEBUG_STORAGE("usb_stor_BBB_comdat:usb_bulk_msg error\r\n");}
+	usb_free(cbw);
+	return result;
+}
+
+/* FIXME: we also need a CBI_command which sets up the completion
+ * interrupt, and waits for it
+ */
+int usb_stor_CB_comdat(ccb *srb, struct us_data *us)
+{
+	int result = 0;
+	int dir_in, retry;
+	unsigned int pipe;
+	unsigned long status;
+	retry = 5;
+	dir_in = US_DIRECTION(srb->cmd[0]);
+	if(dir_in)
+		pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	else
+		pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	while(retry--)
+	{
+		DEBUG_STORAGE("CBI gets a command: Try %d\r\n", 5 - retry);
+#ifdef USB_STOR_DEBUG
+		usb_show_srb(srb);
+#endif
+		/* let's send the command via the control pipe */
+		result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev , 0),
+		 US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, srb->cmd, srb->cmdlen, USB_CNTL_TIMEOUT * 5);
+		DEBUG_STORAGE("CB_transport: control msg returned %d, status %lX\r\n", result, us->pusb_dev->status);
+		/* check the return code for the command */
+		if(result < 0)
+		{
+			if(us->pusb_dev->status & USB_ST_STALLED)
+			{
+				status = us->pusb_dev->status;
+				DEBUG_STORAGE(" stall during command found, clear pipe\r\n");
+				usb_clear_halt(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0));
+				us->pusb_dev->status = status;
+			}
+			DEBUG_STORAGE(" error during command %02X Stat = %lX\r\n", srb->cmd[0], us->pusb_dev->status);
+			return result;
+		}
+		/* transfer the data payload for this command, if one exists*/
+		DEBUG_STORAGE("CB_transport: control msg returned %d, direction is %s to go 0x%lx\r\n", result, dir_in ? "IN" : "OUT", srb->datalen);
+		if(srb->datalen)
+		{
+			result = us_one_transfer(us, pipe, (char *)srb->pdata, srb->datalen);
+			DEBUG_STORAGE("CBI attempted to transfer data, result is %d status %lX, len %d\r\n", result, us->pusb_dev->status, us->pusb_dev->act_len);
+			if(!(us->pusb_dev->status & USB_ST_NAK_REC))
+				break;
+		} /* if(srb->datalen) */
+		else
+			break;
+	}
+	/* return result */
+	return result;
+}
+
+int usb_stor_CBI_get_status(ccb *srb, struct us_data *us)
+{
+	int timeout;
+	us->ip_wanted = 1;
+	submit_int_msg(us->pusb_dev, us->irqpipe, (void *) &us->ip_data, us->irqmaxp, us->irqinterval);
+	timeout = 1000;
+	while(timeout--)
+	{
+		if((volatile int *) us->ip_wanted == 0)
+			break;
+		wait_ms(10);
+	}
+	if(us->ip_wanted)
+	{
+		DEBUG_STORAGE("Did not get interrupt on CBI\r\n");
+		printf("Did not get interrupt on CBI\r\n");
+		us->ip_wanted = 0;
+		return USB_STOR_TRANSPORT_ERROR;
+	}
+	DEBUG_STORAGE("Got interrupt data 0x%x, transfered %d status 0x%lX\r\n", us->ip_data, us->pusb_dev->irq_act_len, us->pusb_dev->irq_status);
+	/* UFI gives us ASC and ASCQ, like a request sense */
+	if(us->subclass == US_SC_UFI)
+	{
+		if(srb->cmd[0] == SCSI_REQ_SENSE || srb->cmd[0] == SCSI_INQUIRY)
+			return USB_STOR_TRANSPORT_GOOD; /* Good */
+		else if(us->ip_data)
+			return USB_STOR_TRANSPORT_FAILED;
+		else
+			return USB_STOR_TRANSPORT_GOOD;
+	}
+	/* otherwise, we interpret the data normally */
+	switch(us->ip_data)
+	{
+		case 0x0001: return USB_STOR_TRANSPORT_GOOD;
+		case 0x0002: return USB_STOR_TRANSPORT_FAILED;
+		default: return USB_STOR_TRANSPORT_ERROR;
+	}
+	return USB_STOR_TRANSPORT_ERROR;
+}
+
+#define USB_TRANSPORT_UNKNOWN_RETRY 5
+#define USB_TRANSPORT_NOT_READY_RETRY 10
+
+/* clear a stall on an endpoint - special for BBB devices */
+int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt)
+{
+	int result;
+	/* ENDPOINT_HALT = 0, so set value to 0 */
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
+	 USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, endpt, 0, 0, USB_CNTL_TIMEOUT * 5);
+	return result;
+}
+
+int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
+{
+	int result, retry;
+	int dir_in;
+	int actlen, data_actlen;
+	unsigned int pipe, pipein, pipeout;
+//	DEBUG_STORAGE ( );  /* GALVEZ: DEBUG */
+#ifdef BBB_XPORT_TRACE
+	unsigned char *ptr;
+	int idx;
+#endif
+	umass_bbb_csw_t *csw = (umass_bbb_csw_t *)usb_malloc(sizeof(umass_bbb_csw_t));
+	if(csw == NULL)
+	{
+		DEBUG_STORAGE("out of memory\r\n");
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	dir_in = US_DIRECTION(srb->cmd[0]);
+	/* COMMAND phase */
+	DEBUG_STORAGE("COMMAND phase\n");
+	result = usb_stor_BBB_comdat(srb, us);
+	if(result < 0)
+	{
+		DEBUG_STORAGE("failed to send CBW status %ld\r\n", us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	wait_ms(5);
+	pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	/* DATA phase + error handling */
+	data_actlen = 0;
+	/* no data, go immediately to the STATUS phase */
+	if(srb->datalen == 0)
+		goto st;
+	DEBUG_STORAGE("DATA phase\n");
+	if(dir_in)
+		pipe = pipein;
+	else
+		pipe = pipeout;
+	result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT * 5);
+	/* special handling of STALL in DATA phase */
+	if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("DATA:stall\r\n");
+		/* clear the STALL on the endpoint */
+		result = usb_stor_BBB_clear_endpt_stall(us, dir_in ? us->ep_in : us->ep_out);
+		if(result >= 0)
+			/* continue on to STATUS phase */
+			goto st;
+	}
+	if(result < 0)
+	{
+		DEBUG_STORAGE("usb_bulk_msg error status %ld\r\n", us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+#ifdef BBB_XPORT_TRACE
+	debug_init("usb.log");
+	for(idx = 0; idx < data_actlen; idx++)
+		debug("pdata[%d] %#x ", idx, srb->pdata[idx]);
+	debug("\r\n");
+	debug_exit( );
+#endif
+	/* STATUS phase + error handling */
+st:
+	retry = 0;
+again:
+	DEBUG_STORAGE("STATUS phase\n");
+	result = usb_bulk_msg(us->pusb_dev, pipein, csw, UMASS_BBB_CSW_SIZE, &actlen, USB_CNTL_TIMEOUT*5);
+	/* special handling of STALL in STATUS phase */
+
+	if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("STATUS:stall\r\n");
+		/* clear the STALL on the endpoint */
+		result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in);
+		if(result >= 0 && (retry++ < 1))
+			/* do a retry */
+			goto again;
+	}
+
+	if(result < 0)
+	{
+		DEBUG_STORAGE("usb_bulk_msg error status %ld\r\n", us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+#ifdef BBB_XPORT_TRACE
+	debug_init("usb.log");
+	ptr = (unsigned char *)csw;
+	for(idx = 0; idx < UMASS_BBB_CSW_SIZE; idx++)
+		debug("ptr[%d] %#x ", idx, ptr[idx]);
+	debug("\r\n");
+	debug_exit( );
+#endif
+	/* misuse pipe to get the residue */
+	pipe = le32_to_cpu(csw->dCSWDataResidue);
+	if(pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0)
+		pipe = srb->datalen - data_actlen;
+	if(CSWSIGNATURE != le32_to_cpu(csw->dCSWSignature))
+	{
+		DEBUG_STORAGE("!CSWSIGNATURE\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if((CBWTag - 1) != le32_to_cpu(csw->dCSWTag))
+	{
+		DEBUG_STORAGE("!Tag\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(csw->bCSWStatus > CSWSTATUS_PHASE)
+	{
+		DEBUG_STORAGE(">PHASE\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(csw->bCSWStatus == CSWSTATUS_PHASE)
+	{
+		DEBUG_STORAGE("=PHASE\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(data_actlen > srb->datalen)
+	{
+		DEBUG_STORAGE("transferred %dB instead of %ldB\r\n", data_actlen, srb->datalen);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(csw->bCSWStatus == CSWSTATUS_FAILED)
+	{
+//		printf("FAILED\r\n");      /* GALVEZ: DEBUG */
+		DEBUG_STORAGE("FAILED\r\n");
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	usb_free(csw);;
+	return result;
+}
+
+int usb_stor_CB_transport(ccb *srb, struct us_data *us)
+{
+	int result, status;
+	ccb *psrb;
+	ccb reqsrb;
+	int retry, notready;
+	psrb = &reqsrb;
+	status = USB_STOR_TRANSPORT_GOOD;
+	retry = 0;
+	notready = 0;
+	/* issue the command */
+do_retry:
+	result = usb_stor_CB_comdat(srb, us);
+	DEBUG_STORAGE("command / Data returned %d, status %lX\r\n", result, us->pusb_dev->status);
+	/* if this is an CBI Protocol, get IRQ */
+	if(us->protocol == US_PR_CBI)
+	{
+		status = usb_stor_CBI_get_status(srb, us);
+		/* if the status is error, report it */
+		if(status == USB_STOR_TRANSPORT_ERROR)
+		{
+			DEBUG_STORAGE(" USB CBI Command Error\r\n");
+			return status;
+		}
+		srb->sense_buf[12] = (unsigned char)(us->ip_data >> 8);
+		srb->sense_buf[13] = (unsigned char)(us->ip_data & 0xff);
+		if(!us->ip_data)
+		{
+			/* if the status is good, report it */
+			if(status == USB_STOR_TRANSPORT_GOOD)
+			{
+				DEBUG_STORAGE(" USB CBI Command Good\r\n");
+				return status;
+			}
+		}
+	}
+	/* do we have to issue an auto request? */
+	/* HERE we have to check the result */
+	if((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("ERROR %lX\r\n", us->pusb_dev->status);
+		us->transport_reset(us);
+		return USB_STOR_TRANSPORT_ERROR;
+	}
+	if((us->protocol == US_PR_CBI) && ((srb->cmd[0] == SCSI_REQ_SENSE) || (srb->cmd[0] == SCSI_INQUIRY)))
+	{
+		/* do not issue an autorequest after request sense */
+		DEBUG_STORAGE("No auto request and good\r\n");
+		return USB_STOR_TRANSPORT_GOOD;
+	}
+	/* issue an request_sense */
+	memset(&psrb->cmd[0], 0, 12);
+	psrb->cmd[0] = SCSI_REQ_SENSE;
+	psrb->cmd[1] = srb->lun << 5;
+	psrb->cmd[4] = 18;
+	psrb->datalen = 18;
+	psrb->pdata = &srb->sense_buf[0];
+	psrb->cmdlen = 12;
+	/* issue the command */
+	result = usb_stor_CB_comdat(psrb, us);
+	DEBUG_STORAGE("auto request returned %d\r\n", result);
+	/* if this is an CBI Protocol, get IRQ */
+	if(us->protocol == US_PR_CBI)
+		status = usb_stor_CBI_get_status(psrb, us);
+	if((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE(" AUTO REQUEST ERROR %ld\r\n", us->pusb_dev->status);
+		return USB_STOR_TRANSPORT_ERROR;
+	}
+	DEBUG_STORAGE("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\r\n", srb->sense_buf[0], srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+	/* Check the auto request result */
+	if((srb->sense_buf[2] == 0) && (srb->sense_buf[12] == 0) && (srb->sense_buf[13] == 0))
+	{
+		/* ok, no sense */
+		return USB_STOR_TRANSPORT_GOOD;
+	}
+	/* Check the auto request result */
+	switch(srb->sense_buf[2])
+	{
+		case 0x01:
+			/* Recovered Error */
+			return USB_STOR_TRANSPORT_GOOD;
+		case 0x02: /* Not Ready */
+			if(notready++ > USB_TRANSPORT_NOT_READY_RETRY)
+			{
+				DEBUG_STORAGE("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X (NOT READY)\r\n", srb->cmd[0], srb->sense_buf[0], srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+				return USB_STOR_TRANSPORT_FAILED;
+			}
+			else
+			{
+				wait_ms(100);
+				goto do_retry;
+			}
+			break;
+		default:
+			if(retry++ > USB_TRANSPORT_UNKNOWN_RETRY)
+			{
+				DEBUG_STORAGE("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X\r\n", 
+					       srb->cmd[0], srb->sense_buf[0], srb->sense_buf[2],
+					       srb->sense_buf[12], srb->sense_buf[13]);
+				return USB_STOR_TRANSPORT_FAILED;
+			}
+			else
+				goto do_retry;
+			break;
+	}
+	return USB_STOR_TRANSPORT_FAILED;
+}
+
+static int usb_inquiry(ccb *srb, struct us_data *ss)
+{
+	DEBUG_STORAGE ("usb_inquiry()");  /* GALVEZ: DEBUG */
+
+	int retry, i;
+	retry = 5;
+	do
+	{
+		memset(&srb->cmd[0], 0, 12);
+		srb->cmd[0] = SCSI_INQUIRY;
+		srb->cmd[4] = 36;
+		srb->datalen = 36;
+		srb->cmdlen = 12;
+		i = ss->transport(srb, ss);
+		DEBUG_STORAGE("inquiry returns %d\r\n", i);
+		if(i == 0)
+			break;
+	}
+	while(retry--);
+	if(!retry)
+	{
+		DEBUG_STORAGE("error in inquiry\r\n");
+		printf("error in inquiry\r\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int usb_request_sense(ccb *srb, struct us_data *ss)
+{
+	DEBUG_STORAGE("usb_request_sense()");  /* GALVEZ: DEBUG */
+	char *ptr;
+	ptr = (char *)srb->pdata;
+	memset(&srb->cmd[0], 0, /*12*/6);	/* GALVEZ: DEBUG: DEFAULT 12 */
+	srb->cmd[0] = SCSI_REQ_SENSE;
+	srb->cmd[4] = 18;
+	srb->datalen = 18;
+	srb->pdata = &srb->sense_buf[0];
+	srb->cmdlen = /*12*/6;		/* GALVEZ: DEBUG: DEFAULT 12 */
+	ss->transport(srb, ss);
+	DEBUG_STORAGE("Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+	srb->pdata = (unsigned char *)ptr;
+	return 0;
+}
+
+static int usb_test_unit_ready(ccb *srb, struct us_data *ss)
+{
+	int retries = 10;
+	DEBUG_STORAGE("usb_test_unit_ready()");  /* GALVEZ: DEBUG */
+	do
+	{
+		memset(&srb->cmd[0], 0, /*12*/ 6);	/* GALVEZ: DEBUG: DEFAULT 12 */ 
+		srb->cmd[0] = SCSI_TST_U_RDY;
+		srb->datalen = 0;
+		srb->cmdlen = /*12*/ 6;			/* GALVEZ: DEBUG: DEFAULT 12 */
+		if(ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
+			return 0;
+		usb_request_sense(srb, ss);
+		wait_ms(100);
+	}
+	while(retries--);
+	return -1;
+}
+
+static int usb_read_capacity(ccb *srb, struct us_data *ss)
+{
+	int retry;
+	/* XXX retries */
+	retry = 3;
+	DEBUG_STORAGE("usb_read_capacity()");  /* GALVEZ: DEBUG */
+	do
+	{
+		memset(&srb->cmd[0], 0, 12);
+		srb->cmd[0] = SCSI_RD_CAPAC;
+		srb->datalen = 8;
+		srb->cmdlen = 12;
+		if(ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
+			return 0;
+	}
+	while(retry--);
+	return -1;
+}
+
+static int usb_read_10(ccb *srb, struct us_data *ss, unsigned long start, unsigned short blocks)
+{
+	memset(&srb->cmd[0], 0, 12);
+	srb->cmd[0] = SCSI_READ10;
+	srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
+	srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
+	srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
+	srb->cmd[5] = ((unsigned char) (start)) & 0xff;
+	srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
+	srb->cmd[8] = (unsigned char) blocks & 0xff;
+	srb->cmdlen = 12;
+	DEBUG_STORAGE("read10: start %lx blocks %x\r\n", start, blocks);
+	return ss->transport(srb, ss);
+}
+
+static int usb_write_10(ccb *srb, struct us_data *ss, unsigned long start, unsigned short blocks)
+{
+	memset(&srb->cmd[0], 0, 12);
+	srb->cmd[0] = SCSI_WRITE10;
+	srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
+	srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
+	srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
+	srb->cmd[5] = ((unsigned char) (start)) & 0xff;
+	srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
+	srb->cmd[8] = (unsigned char) blocks & 0xff;
+	srb->cmdlen = 12;
+	DEBUG_STORAGE("write10: start %lx blocks %x\r\n", start, blocks);
+	return ss->transport(srb, ss);
+}
+
+#ifdef CONFIG_USB_BIN_FIXUP
+/*
+ * Some USB storage devices queried for SCSI identification data respond with
+ * binary strings, which if output to the console freeze the terminal. The
+ * workaround is to modify the vendor and product strings read from such
+ * device with proper values (as reported by 'usb info').
+ *
+ * Vendor and product length limits are taken from the definition of
+ * block_dev_desc_t in include/part.h.
+ */
+static void usb_bin_fixup(struct usb_device_descriptor descriptor, unsigned char vendor[], unsigned char product[])
+{
+	const unsigned char max_vendor_len = 40;
+	const unsigned char max_product_len = 20;
+	if(descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a)
+	{
+		strncpy((char *)vendor, "SMSC", max_vendor_len);
+		strncpy((char *)product, "Flash Media Cntrller", max_product_len);
+	}
+}
+#endif /* CONFIG_USB_BIN_FIXUP */
+
+#define USB_MAX_READ_BLK 20
+
+unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer)
+{
+	unsigned long start, blks, buf_addr;
+	unsigned short smallblks;
+	struct usb_device *dev;
+	int retry, i;
+	ccb *srb = &usb_ccb;
+
+
+	if(blkcnt == 0)
+		return 0;
+	device &= 0xff;	
+	/* Setup  device */
+//	printf ("blknr: %x\n\r", blknr);	/* Galvez: Debug */
+	DEBUG_STORAGE("usb_read: dev %d \r\n", device);
+	dev = NULL;
+#ifdef SUPERVISOR
+	int p = 0;	
+	/* GALVEZ: Acces to register in Supervisor */
+	if (!(Super(SUP_INQUIRE))){
+		p = SuperFromUser();
+	}
+#endif
+		
+	for(i = 0; i < USB_MAX_DEVICE; i++)
+	{
+		dev = usb_get_dev_index(i);
+		if(dev == NULL){
+#ifdef SUPERVISOR
+			/* GALVEZ: come back to user mode */
+			if ((Super(SUP_INQUIRE)) && (p)){
+				SuperToUser(p);
+			}
+#endif
+			return 0;
+		}
+		if(dev->devnum == usb_dev_desc[device].target)
+			break;
+	}
+	usb_disable_asynch(1); /* asynch transfer not allowed */
+	srb->lun = usb_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+
+	if(usb_test_unit_ready(srb, (struct us_data *)dev->privptr))
+	{
+		DEBUG_STORAGE("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+		printf("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+#ifdef SUPERVISOR
+		/* GALVEZ: come back to user mode */
+		if ((Super(SUP_INQUIRE)) && (p)){
+			SuperToUser(p);
+		}
+#endif
+		return 0;
+	}
+
+	DEBUG_STORAGE("usb_read: dev %d startblk %lx, blccnt %lx buffer %lx\r\n", device, start, blks, buf_addr);
+	do
+	{
+		/* XXX need some comment here */
+		retry = 2;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(blks > USB_MAX_READ_BLK)
+			smallblks = USB_MAX_READ_BLK;
+		else
+			smallblks = (unsigned short) blks;
+retry_it:
+		srb->datalen = usb_dev_desc[device].blksz * smallblks;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(usb_read_10(srb, (struct us_data *)dev->privptr, start, smallblks))
+		{
+			DEBUG_STORAGE("Read ERROR\r\n");
+			usb_request_sense(srb, (struct us_data *)dev->privptr);
+			if(retry--)
+				goto retry_it;
+			blkcnt -= blks;
+			break;
+		}
+		start += smallblks;
+		blks -= smallblks;
+		buf_addr += srb->datalen;
+	}
+	while(blks != 0);
+	DEBUG_STORAGE("usb_read: end startblk %lx, blccnt %x buffer %lx\r\n", start, smallblks, buf_addr);
+	usb_disable_asynch(0); /* asynch transfer allowed */
+#ifdef SUPERVISOR
+	/* GALVEZ: come back to user mode */
+	if ((Super(SUP_INQUIRE)) && (p)){
+		SuperToUser(p);
+		}
+#endif
+	return blkcnt;
+}
+
+unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer)
+{
+	unsigned long start, blks, buf_addr;
+	unsigned short smallblks;
+	struct usb_device *dev;
+	int retry, i;
+	ccb *srb = &usb_ccb;
+	
+	if(blkcnt == 0)
+		return 0;
+	device &= 0xff;
+	/* Setup  device */
+	DEBUG_STORAGE("usb_write: dev %d \r\n", device);
+#ifdef SUPERVISOR
+	int p = 0;	
+	/* GALVEZ: Acces to register in Supervisor */
+	if ( !(Super(SUP_INQUIRE))){
+		p = SuperFromUser();
+	}
+#endif
+	
+	dev = NULL;
+	for(i = 0; i < USB_MAX_DEVICE; i++)
+	{
+		dev = usb_get_dev_index(i);
+		if(dev == NULL){
+#ifdef SUPERVISOR
+			/* GALVEZ: come back to user mode */
+			if ((Super(SUP_INQUIRE)) && (p))
+				SuperToUser(p);
+#endif
+			return 0;
+		}
+		if(dev->devnum == usb_dev_desc[device].target)
+			break;
+	}
+	usb_disable_asynch(1); /* asynch transfer not allowed */
+	srb->lun = usb_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+//#if 1	/* GALVEZ: DEBUG */
+	if(usb_test_unit_ready(srb, (struct us_data *)dev->privptr))
+	{
+		DEBUG_STORAGE("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+		printf("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+#ifdef SUPERVISOR
+		/* GALVEZ: come back to user mode */
+		if ((Super(SUP_INQUIRE)) && (p))
+			SuperToUser(p);
+#endif					
+		return 0;
+	}
+//#endif
+	DEBUG_STORAGE("usb_write: dev %d startblk %lx, blccnt %lx buffer %lx\r\n", device, start, blks, buf_addr);
+	do
+	{
+		/* XXX need some comment here */
+		retry = 2;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(blks > USB_MAX_READ_BLK)
+			smallblks = USB_MAX_READ_BLK;
+		else
+			smallblks = (unsigned short)blks;
+retry_it:
+		srb->datalen = usb_dev_desc[device].blksz * smallblks;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(usb_write_10(srb, (struct us_data *)dev->privptr, start, smallblks))
+		{
+			DEBUG_STORAGE("Write ERROR\r\n");
+			usb_request_sense(srb, (struct us_data *)dev->privptr);
+			if(retry--)
+				goto retry_it;
+			blkcnt -= blks;
+			break;
+		}
+		start += smallblks;
+		blks -= smallblks;
+		buf_addr += srb->datalen;
+	}
+	while(blks != 0);
+	DEBUG_STORAGE("usb_write: end startblk %lx, blccnt %x buffer %lx\r\n", start, smallblks, buf_addr);
+	usb_disable_asynch(0); /* asynch transfer allowed */
+#ifdef SUPERVISOR
+	/* GALVEZ: come back to user mode */
+	if ((Super(SUP_INQUIRE)) && (p))
+		SuperToUser(p);
+#endif
+	return blkcnt;
+}
+
+/* Probe to see if a new device is actually a Storage device */
+int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss)
+{
+	struct usb_interface_descriptor *iface;
+	int i;
+	unsigned int flags = 0;
+	int protocol = 0;
+	int subclass = 0;
+	
+	DEBUG_STORAGE("usb_storage_probe()");
+
+	/* let's examine the device now */
+	iface = &dev->config.if_desc[ifnum];
+#if 0
+	DEBUG_STORAGE("iVendor 0x%X iProduct 0x%X\r\n", dev->descriptor.idVendor, dev->descriptor.idProduct);
+	/* this is the place to patch some storage devices */
+	if((dev->descriptor.idVendor) == 0x066b && (dev->descriptor.idProduct) == 0x0103)
+	{
+		DEBUG_STORAGE("patched for E-USB\r\n");
+		protocol = US_PR_CB;
+		subclass = US_SC_UFI;	    /* an assumption */
+	}
+#endif
+	if(dev->descriptor.bDeviceClass != 0 || iface->bInterfaceClass != USB_CLASS_MASS_STORAGE
+	 || iface->bInterfaceSubClass < US_SC_MIN || iface->bInterfaceSubClass > US_SC_MAX)
+		/* if it's not a mass storage, we go no further */
+		return 0;
+	memset(ss, 0, sizeof(struct us_data));
+	/* At this point, we know we've got a live one */
+	DEBUG_STORAGE("\r\n\r\nUSB Mass Storage device detected\r\n");
+	DEBUG_STORAGE("Protocol: %x SubClass: %x", iface->bInterfaceProtocol,       /* GALVEZ: DEBUG */
+							 iface->bInterfaceSubClass );
+	/* Initialize the us_data structure with some useful info */
+	ss->flags = flags;
+	ss->ifnum = ifnum;
+	ss->pusb_dev = dev;
+	ss->attention_done = 0;
+	/* If the device has subclass and protocol, then use that.  Otherwise,
+	 * take data from the specific interface.
+	 */
+	if(subclass)
+	{
+		ss->subclass = subclass;
+		ss->protocol = protocol;
+	}
+	else
+	{
+		ss->subclass = iface->bInterfaceSubClass;
+		ss->protocol = iface->bInterfaceProtocol;
+	}
+	/* set the handler pointers based on the protocol */
+	DEBUG_STORAGE("Transport: ");
+	switch(ss->protocol)
+	{
+		case US_PR_CB:
+			DEBUG_STORAGE("Control/Bulk\r\n");
+			ss->transport = usb_stor_CB_transport;
+			ss->transport_reset = usb_stor_CB_reset;
+			break;
+		case US_PR_CBI:
+			DEBUG_STORAGE("Control/Bulk/Interrupt\r\n");
+			ss->transport = usb_stor_CB_transport;
+			ss->transport_reset = usb_stor_CB_reset;
+			break;
+		case US_PR_BULK:
+			DEBUG_STORAGE("Bulk/Bulk/Bulk\r\n");
+			ss->transport = usb_stor_BBB_transport;
+			ss->transport_reset = usb_stor_BBB_reset;
+			break;
+		default:
+			printf("USB Storage Transport unknown / not yet implemented\r\n");
+			return 0;
+			break;
+	}
+	/*
+	 * We are expecting a minimum of 2 endpoints - in and out (bulk).
+	 * An optional interrupt is OK (necessary for CBI protocol).
+	 * We will ignore any others.
+	 */
+	DEBUG_STORAGE("Number of endpoints: %d\r\n", iface->bNumEndpoints);
+	for(i = 0; i < iface->bNumEndpoints; i++)
+	{
+		/* is it an BULK endpoint? */
+		if((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)
+		{
+			if(iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
+				ss->ep_in = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+			else
+				ss->ep_out = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+		}
+		/* is it an interrupt endpoint? */
+		if((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT)
+		{
+			ss->ep_int = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+			ss->irqinterval = iface->ep_desc[i].bInterval;
+		}
+	}
+	DEBUG_STORAGE("Endpoints In %d Out %d Int %d\r\n", ss->ep_in, ss->ep_out, ss->ep_int);
+	/* Do some basic sanity checks, and bail if we find a problem */
+	if(usb_set_interface(dev, iface->bInterfaceNumber, 0) || !ss->ep_in || !ss->ep_out
+	 || (ss->protocol == US_PR_CBI && ss->ep_int == 0))
+	{
+		DEBUG_STORAGE("Problems with device\r\n");
+		return 0;
+	}
+	/* set class specific stuff */
+	/* We only handle certain protocols.  Currently, these are
+	 * the only ones.
+	 * The SFF8070 accepts the requests used in u-boot
+	 */
+	if(ss->subclass != US_SC_UFI && ss->subclass != US_SC_SCSI && ss->subclass != US_SC_8070)
+	{
+		DEBUG_STORAGE("Sorry, protocol %d not yet supported.\r\n", ss->subclass);
+		printf("Sorry, protocol %d not yet supported.\r\n", ss->subclass);
+		return 0;
+	}
+	if(ss->ep_int)
+	{
+		/* we had found an interrupt endpoint, prepare irq pipe
+		 * set up the IRQ pipe and handler
+		 */
+		ss->irqinterval = (ss->irqinterval > 0) ? ss->irqinterval : 255;
+		ss->irqpipe = usb_rcvintpipe(ss->pusb_dev, ss->ep_int);
+		ss->irqmaxp = usb_maxpacket(dev, ss->irqpipe);
+		dev->irq_handle = usb_stor_irq;
+	}
+	dev->privptr = (void *)ss;
+	return 1;
+}
+
+int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, block_dev_desc_t *dev_desc)
+{
+	unsigned char perq, modi;
+	unsigned long cap[2];
+	unsigned long *capacity, *blksz;
+	ccb *pccb = &usb_ccb;
+	DEBUG_STORAGE("usb_stor_ger_info()");
+	/* for some reasons a couple of devices would not survive this reset */
+	if(
+	 /* Sony USM256E */
+	 (dev->descriptor.idVendor == 0x054c && dev->descriptor.idProduct == 0x019e)
+	 /* USB007 Mini-USB2 Flash Drive */
+	 || (dev->descriptor.idVendor == 0x066f && dev->descriptor.idProduct == 0x2010)
+	 /* SanDisk Corporation Cruzer Micro 20044318410546613953 */
+	 || (dev->descriptor.idVendor == 0x0781 && dev->descriptor.idProduct == 0x5151)
+	 /* SanDisk Corporation U3 Cruzer Micro 1/4GB Flash Drive 000016244373FFB4 */
+	 || (dev->descriptor.idVendor == 0x0781 && dev->descriptor.idProduct == 0x5406)
+	)
+	{	DEBUG_STORAGE("usb_stor_get_info: skipping RESET..\r\n");}
+	else
+		ss->transport_reset(ss);
+	pccb->pdata = usb_stor_buf;
+	dev_desc->target = dev->devnum;
+	pccb->lun = dev_desc->lun;
+	DEBUG_STORAGE(" address %d\r\n", dev_desc->target);
+	if(usb_inquiry(pccb, ss))
+		return -1;
+	perq = usb_stor_buf[0];
+	modi = usb_stor_buf[1];
+	if((perq & 0x1f) == 0x1f)
+		/* skip unknown devices */
+		return 0;
+	if((modi&0x80) == 0x80)
+		/* drive is removable */
+		dev_desc->removable = 1;
+	memcpy(&dev_desc->vendor[0], &usb_stor_buf[8], 8);
+	memcpy(&dev_desc->product[0], &usb_stor_buf[16], 16);
+	memcpy(&dev_desc->revision[0], &usb_stor_buf[32], 4);
+	dev_desc->vendor[8] = 0;
+	dev_desc->product[16] = 0;
+	dev_desc->revision[4] = 0;
+#ifdef CONFIG_USB_BIN_FIXUP
+	usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product);
+#endif /* CONFIG_USB_BIN_FIXUP */
+	DEBUG_STORAGE("ISO Vers %X, Response Data %X\r\n", usb_stor_buf[2], usb_stor_buf[3]);
+	if(usb_test_unit_ready(pccb, ss))
+	{
+		DEBUG_STORAGE("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", pccb->sense_buf[2], pccb->sense_buf[12], pccb->sense_buf[13]);
+		printf("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", pccb->sense_buf[2], pccb->sense_buf[12], pccb->sense_buf[13]);
+		if(dev_desc->removable == 1)
+		{
+			dev_desc->type = perq;
+			return 1;
+		}
+		return 0;
+	}
+	pccb->pdata = (unsigned char *)&cap[0];
+	memset(pccb->pdata, 0, 8);
+	if(usb_read_capacity(pccb, ss) != 0)
+	{
+		printf("READ_CAP ERROR\r\n");
+		cap[0] = 2880;
+		cap[1] = 0x200;
+	}
+	DEBUG_STORAGE("Read Capacity returns: 0x%lx, 0x%lx\r\n", cap[0], cap[1]);
+#if 0
+	if(cap[0] > (0x200000 * 10)) /* greater than 10 GByte */
+		cap[0] >>= 16;
+#endif
+	cap[0] = cpu_to_be32(cap[0]);
+	cap[1] = cpu_to_be32(cap[1]);
+	/* this assumes bigendian! */
+	cap[0] += 1;
+	capacity = &cap[0];
+	blksz = &cap[1];
+	DEBUG_STORAGE("Capacity = 0x%lx, blocksz = 0x%lx\r\n", *capacity, *blksz);
+	dev_desc->lba = *capacity;
+	dev_desc->blksz = *blksz;
+	dev_desc->type = perq;
+	DEBUG_STORAGE(" address %d\r\n", dev_desc->target);
+	DEBUG_STORAGE("partype: %d\r\n", dev_desc->part_type);
+	init_part(dev_desc);
+	DEBUG_STORAGE("partype: %d\r\n", dev_desc->part_type);
+	return 1;
+}
+
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI */
diff --git a/usb/store/vars.h b/usb/store/vars.h
new file mode 100644
index 0000000..b6e626b
--- /dev/null
+++ b/usb/store/vars.h
@@ -0,0 +1,83 @@
+/*
+* Modified by David Gálvez 2010.
+*
+* TOS 4.04 Xbios vars for the CT60 board
+*  Didier Mequignon 2002-2005, e-mail: aniplay@wanadoo.fr
+*
+*  This library is free software; you can redistribute it and/or
+*  modify it under the terms of the GNU Lesser General Public
+*  License as published by the Free Software Foundation; either
+*  version 2.1 of the License, or (at your option) any later version.
+*
+*  This library is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+*  Lesser General Public License for more details.
+*
+*  You should have received a copy of the GNU Lesser General Public
+*  License along with this library; if not, write to the Free Software
+*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef	_VARS_H
+#define	_VARS_H
+
+
+#define etv_timer   0x400
+#define etv_critic  0x404
+#define memvalid    0x420
+#define memctrl     0x424
+#define resvalid    0x426
+#define resvector   0x42A
+#define phystop     0x42E
+#define _memtop     0x436
+#define memval2     0x43A
+#define flock       0x43E
+#define _timer_ms   0x442
+#define _bootdev    0x446
+#define sshiftmd    0x44C
+#define _v_bas_ad   0x44E
+#define vblsem      0x452
+#define nvbls       0x454
+#define _vblqueue   0x456
+#define colorptr    0x45A
+#define _vbclock    0x462
+#define _frclock    0x466
+#define hdv_init    0x46A
+#define HDV_BPB     0x472
+#define hdv_bpb    0x472
+#define HDV_RW      0x476
+#define hdv_rw     0x476
+#define hdv_boot    0x47A
+#define HDV_MEDIACH 0x47E
+#define hdv_mediach 0x47E
+#define _cmdload    0x482
+#define conterm     0x484
+#define trp14ret    0x486
+#define __md        0x49E
+#define savptr      0x4A2
+#define _nflops     0x4A6
+#define con_state   0x4A8
+#define save_row    0x4AC
+#define _hz_200     0x4BA
+#define _DRVBITS    0x4C2
+#define _drvbits    0x4C2
+#define DSKBUFP     0x4C6
+#define _dskbufp    0x4C6
+#define _dumpflg    0x4EE
+#define _sysbase    0x4F2
+#define exec_os     0x4FE
+#define dump_vec    0x502
+#define ptr_stat    0x506
+#define ptr_vec     0x50A
+#define aux_sta     0x50E
+#define aux_vec     0x512
+#define PUN_PTR     0x516
+#define memval3     0x51A
+#define proc_type   0x59E
+#define COOKIE      0x5A0
+#define cookie	    0x5A0
+                  
+
+
+#endif
diff --git a/usb/store/xhdi.c b/usb/store/xhdi.c
new file mode 100644
index 0000000..3be2bfa
--- /dev/null
+++ b/usb/store/xhdi.c
@@ -0,0 +1,391 @@
+/***************** NOT READY YET ***********************/
+/**************** ONLY EXPERIMENTAL ********************/ 
+
+/* TOS 4.04 Xbios dispatcher for the CT60/CTPCI boards
+ * and USB-disk / Ram-Disk utility
+ * Didier Mequignon 2005-2009, e-mail: aniplay@wanadoo.fr
+ * 
+ * Translation to C by David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <stdio.h>
+#include <mint/osbind.h>
+
+#include "config.h"
+#include "vars.h"
+#include "xhdi.h"
+#include "debug.h"
+
+long *drvbits = (long *)_DRVBITS;
+
+struct pun_info *old_pun_ptr = (struct pun_info *)0x512;
+struct usb_pun_info pun_ptr_usb;
+
+XBRA xbra_hdv_bpb;
+XBRA xbra_hdv_rw;
+XBRA xbra_hdv_mediach;
+
+extern long usb_1st_disk_drive;
+extern short max_logical_drive;
+
+extern unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer);
+
+void drive_full_usb(void)
+{
+	DEBUG_XHDI("\n");
+}
+
+long __CDECL hdv_bpb_usb(void)
+{
+	unsigned short dev;
+	long r;
+
+	__asm__ volatile	/* get arguments from the stack */
+	(
+		"move.w 12(%%sp),%0\n\t"
+
+		:/*outputs*/ "=m" (dev)
+		:/*inputs*/ 
+	);
+
+	__asm__ volatile	/* call old vector */
+	(
+		"movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t"	/* important to save register */
+		"move.l %1,%%a0\n\t"
+		"move.w #0,-(%%sp)\n\t"
+		"move.w %2,-(%%sp)\n\t"
+		"jsr (%%a0)\n\t"
+		"addq.l #4,%%sp\n\t"
+		"move.l %%d0,%0\n\t"
+		"movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t"
+		:/*outputs*/ "=r" (r)
+		:/*inputs*/ "m" (xbra_hdv_bpb.xb_oldvec), "m" (dev)
+		:"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" /*clobbered regs*/
+	);
+	return r;
+}
+
+long __CDECL hdv_rw_usb(void)
+{	
+	void *buf;
+	short count, recno, dev, mode;
+	long lrecno;
+
+	long r = 0;
+	
+	__asm__ volatile	/* get arguments from the stack */
+	(
+		"move.l 18(%%sp),%0\n\t"
+		"move.w 14(%%sp),%1\n\t"
+		"move.w 12(%%sp),%2\n\t"
+		"move.w 10(%%sp),%3\n\t"
+		"move.l 8(%%sp),%4\n\t"
+		"move.w 4(%%sp),%5\n\t"
+		:/*outputs*/ "=r" (lrecno), "=r" (dev) ,"=r" (recno), "=r" (count), "=r" (buf), "=r" (mode)
+		:/*inputs*/ 
+	);
+	
+	DEBUG_XHDI("lrecno %lx dev %d recno %x count %d mode %x\n",
+			lrecno, dev, recno, count, mode);
+	
+	DEBUG_XHDI("\n");
+	DEBUG_XHDI("rw\n");
+
+	__asm__ volatile	/* call old vector */
+	(
+		"movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t"
+		"move.l %1,%%a0\n\t"
+		"move.l (%%a0),%%d0\n\t"
+		"move.w #0,-(%%sp)\n\t"
+		"move.l %2,-(%%sp)\n\t"
+		"move.w %3,-(%%sp)\n\t"
+		"move.w %4,-(%%sp)\n\t"
+		"move.w %5,-(%%sp)\n\t"
+		"move.l %6,-(%%sp)\n\t"
+		"move.w %7,-(%%sp)\n\t"
+		"move.l %%d0,%%a0\n\t"
+		"jsr (%%a0)\n\t"
+		"addq.l #4,%%sp\n\t"
+		"move.l %%d0,%0\n\t"
+		"movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t"
+		:/*outputs*/ "=r" (r)
+		:/*inputs*/ "r" (xbra_hdv_rw.xb_oldvec), "r" (lrecno), "r" (dev) ,"r" (recno), "r" (count), "r" (buf), "r" (mode)
+		:"d0"/*, "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" clobbered regs*/
+	);
+
+//	r = (*xbra_hdv_rw.xb_oldvec)(mode, buf, num, recno, dev, l);
+	DEBUG_XHDI (" r %lx \n", r);
+
+	return r;
+}
+
+long __CDECL hdv_mediach_usb(void)
+{
+	DEBUG_XHDI("\n");
+	DEBUG_XHDI("mediach\n");
+
+	short dev, dev1, dev2;
+	long r;
+
+	__asm__ volatile	/* get arguments from the stack */
+	(
+		"move.w 2(%%sp),%0\n\t"
+		"move.w 4(%%sp),%1\n\t"
+		"move.w 6(%%sp),%2\n\t"
+		:/*outputs*/ "=r" (dev), "=r" (dev1), "=r" (dev2)
+		:/*inputs*/ 
+	);
+
+	DEBUG_XHDI (" dev(2) %x dev(4) %x dev(6) %x\n", dev, dev1, dev2);
+
+	__asm__ volatile	/* call old vector */
+	(
+		"movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t"
+		"move.l %1,%%a0\n\t"
+		"move.l (%%a0),%%d0\n\t"
+		"move.w #0,-(%%sp)\n\t"
+		"move.w %2,-(%%sp)\n\t"
+		"move.l %%d0,%%a0\n\t"
+		"jsr (%%a0)\n\t"
+		"addq.l #4,%%sp\n\t"
+		"move.l %%d0,%0\n\t"
+		"movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t"
+		:/*outputs*/ "=r" (r)
+		:/*inputs*/ "r" (xbra_hdv_mediach.xb_oldvec), "r" (dev)
+		:"d0"/*, "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" clobbered regs*/
+	);
+//	printf (" r %lx \n", r);
+//	r = (*xbra_hdv_mediach.xb_oldvec)(d);
+//	DEBUG_XHDI("Calling vector: %x\n", xbra_hdv_mediach.xb_oldvec);
+//	r = (*xbra_hdv_mediach.xb_oldvec)(5);
+	DEBUG_XHDI(" r %lx \n", r);
+
+	return r;
+}
+
+void install_xbra(XBRA *xbra_hd, long id, long old_vec, long (*handle)())
+{
+	DEBUG_XHDI("\n");
+#define XBRA_MAGIC	0x58425241L /* "XBRA" */
+#define JMP_OPCODE	0x4EF9
+
+	xbra_hd->xb_magic = XBRA_MAGIC;
+	xbra_hd->xb_id = id;
+	xbra_hd->xb_oldvec = *((Func *)old_vec);
+	xbra_hd->jump = JMP_OPCODE;
+	xbra_hd->handle = (Func) handle;	
+
+	*((Func *)old_vec) = xbra_hd->handle;
+
+	DEBUG_XHDI("id: %x xbra_hd->xb_oldvec %x old_vec %x old_vec (*) %x old_vec (&)  %x\n", 
+			xbra_hd->xb_id, xbra_hd->xb_oldvec, old_vec, *((Func *)old_vec), &old_vec);
+
+	__asm__ volatile	/* clean cache ??? */
+	(
+		"cpusha BC\n\t"
+		:/*outputs*/
+		:/*inputs*/
+	);
+}
+
+void usb_drive_ok(void)
+{
+	DEBUG_XHDI("\n");
+
+}
+
+
+long install_usb_partition(unsigned char drive, int dev_num, unsigned long part_type, 
+			 unsigned long part_offset, unsigned long part_size)
+{
+	DEBUG_XHDI("\n");	
+
+	int *dskbufp = (int *)DSKBUFP; 
+	unsigned short status_register;
+
+	long old_hdv_bpb;
+	long old_hdv_rw;
+	long old_hdv_mediach;
+
+	if (drive < 16) {
+		(pun_ptr_usb.puns)++;
+		pun_ptr_usb.pun[drive] = dev_num | PUN_USB;
+		pun_ptr_usb.pstart[drive] = part_offset;
+		pun_ptr_usb.ptype[drive] = part_type;
+		pun_ptr_usb.psize[drive] = part_size;
+		/* flags B15:swap, B7:change, B0:bootable */
+#define BOOTABLE	0x0001
+#define CHANGE		0x0080
+#define SWAP		0x8000
+		pun_ptr_usb.flags[drive] = CHANGE;
+	}
+
+	if (drive < 16) {
+		old_pun_ptr->puns++;
+		old_pun_ptr->pun[drive] = dev_num | PUN_USB;
+	}
+
+	if (usb_stor_read (dev_num, part_offset, 1, (void *)(*dskbufp)) == 0)
+		return -1;
+
+	if (usb_1st_disk_drive)
+		usb_drive_ok();
+
+	usb_1st_disk_drive = drive;
+
+	long r;
+	r = (long)Getbpb (2);
+	DEBUG_XHDI("Before int. Getbpb return: %x \n", r);
+
+
+	__asm__ volatile	/* mask interrupts */
+	(
+		"move.w %%sr,%%d0\n\t"
+		"move.w %%d0,%0\n\t"
+		"or.l #0x700,%%d0\n\t"
+		"move.w %%d0,%%sr\n\t"
+		:/*outputs*/ "=r" (status_register)
+		:/*inputs*/
+		:"d0" /*clobbered regs*/
+	);
+
+#define _USB		0x5F555342  /* _USB   */
+	long id = _USB;
+	old_hdv_bpb = (long)HDV_BPB;
+
+	DEBUG_XHDI("id: %x old_hdv_bpb %x old_hdv_bpb (*) %x hdv_bpb_usb %x\n", 
+			id, old_hdv_bpb, *((Func *)old_hdv_bpb), hdv_bpb_usb);
+	install_xbra(&xbra_hdv_bpb, id, old_hdv_bpb, hdv_bpb_usb);
+	DEBUG_XHDI("id: %x old_hdv_bpb %x old_hdv_bpb (*) %x hdv_bpb_usb %x\n", 
+			xbra_hdv_bpb.xb_id, xbra_hdv_bpb.xb_oldvec, *((Func *)xbra_hdv_bpb.xb_oldvec), xbra_hdv_bpb.handle);
+#if 0	
+	old_hdv_rw = (long)HDV_RW;
+	DEBUG_XHDI("id: %x old_hdv_rw %x old_hdv_rw (*) %x hdv_rw_usb %x\n", 
+			id, old_hdv_rw, *((Func *)old_hdv_rw), hdv_rw_usb);
+	install_xbra(&xbra_hdv_rw, id, old_hdv_rw, hdv_rw_usb);
+	DEBUG_XHDI("id: %x old_hdv_rw %x old_hdv_rw (*) %x hdv_rw_usb %x\n", 
+			xbra_hdv_rw.xb_id, xbra_hdv_rw.xb_oldvec, *((Func *)xbra_hdv_rw.xb_oldvec), xbra_hdv_rw.handle);
+
+	old_hdv_mediach = (long)HDV_MEDIACH;
+	DEBUG_XHDI("id: %x old_hdv_mediach %x old_hdv_mediach (*) %x hdv_mediach_usb %x\n", 
+			id, old_hdv_mediach, *((Func *)old_hdv_mediach), hdv_mediach_usb);
+	install_xbra(&xbra_hdv_mediach, id, old_hdv_mediach, hdv_mediach_usb);
+	DEBUG_XHDI("id: %x old_hdv_mediach %x old_hdv_mediach (*) %x hdv_mediach_usb %x\n", 
+			xbra_hdv_mediach.xb_id, xbra_hdv_mediach.xb_oldvec, *((Func *)xbra_hdv_mediach.xb_oldvec), xbra_hdv_mediach.handle);
+#endif
+
+	r = (long)Getbpb (4);
+
+	DEBUG_XHDI("Before int. Getbpb return: %x \n", r);
+
+//	Bconin(DEV_CONSOLE);
+	__asm__ volatile	/* restore interrupts */
+	(
+		"move.w %%sr,%%d0\n\t"
+		"and.w %0,%%d0\n\t"
+		"move.w %%d0,%%sr\n\t"
+		:/*outputs*/
+		:/*inputs*/ "r" (status_register)
+		:"d0"
+	);
+	DEBUG_XHDI("after restore interrups\n");
+//	Bconin(DEV_CONSOLE);
+	return 0;
+} 	
+
+unsigned char search_empty_drive(int dev_num, unsigned long part_type, 
+	      unsigned long part_offset, unsigned long part_size)
+{
+	DEBUG_XHDI("\n");	
+	
+	unsigned char drive = 2;	
+
+	DEBUG_XHDI("drvbits: %x\n", *drvbits);
+	while (drive < MAX_LOGICAL_DRIVE) {
+		if (!(*drvbits & (0x00000001 << drive))) {
+			DEBUG_XHDI("drive: %d\n", drive);
+			if (install_usb_partition(drive, dev_num, part_type, part_offset, part_size) == -1) {
+				DEBUG_XHDI("Couldn't install USB partition\n");
+				return -1;
+			}
+			else return drive;
+		}
+		drive++;
+	}
+	printf("all drives already used!\n\r");
+
+	return -1;
+}	
+
+unsigned char add_partition(int dev_num, unsigned long part_type, 
+			    unsigned long part_offset, unsigned long part_size)
+{
+	DEBUG_XHDI("\n");
+
+	unsigned char i;
+	unsigned char drive;
+
+	pun_ptr_usb.puns = 0x0000;
+	pun_ptr_usb.version_num = 0x0300;
+	pun_ptr_usb.max_sect_siz = 0x4000;
+	
+	for (i=0; i<16; i++)
+		pun_ptr_usb.pun[i] = 0xff;
+
+	if ((drive = search_empty_drive(dev_num, part_type, part_offset, part_size)) == -1)
+		return -1;
+	return drive;
+}
+
+int install_usb_stor(int dev_num, unsigned long part_type, 
+		      unsigned long part_offset, unsigned long part_size, 
+		      char *vendor, char *revision, char *product )
+{
+	DEBUG_XHDI("\n");
+	unsigned char part_num;
+
+	if (dev_num <= PUN_DEV) {	/* Max. of 32 USB storage devices */
+		switch (part_type) {	/* Although real limit is 16 of pinfo struct */
+			case GEM:
+				break;
+			case BGM:
+				break;
+			case RAW:
+				break;
+			case FAT16_32MB:
+				break;
+			case FAT16:
+				break;
+			case FAT16_WIN95:
+				break;
+			case FAT32:
+				break;
+			case FAT32_II:
+				break;
+			default:
+				printf("Invalid partition type (0x%08lx)\r\n", part_type);
+				return -1;
+		}
+		if ((part_num = add_partition(dev_num, part_type, part_offset, part_size)) == -1)
+			return -1;
+		else return 0;
+	}
+	printf("Maxim number(%d) of USB storage device reached \n\r", dev_num);
+	return -1;
+}
+
+
diff --git a/usb/store/xhdi.h b/usb/store/xhdi.h
new file mode 100644
index 0000000..d8f20bb
--- /dev/null
+++ b/usb/store/xhdi.h
@@ -0,0 +1,101 @@
+/* 
+ * David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _XHDI_H
+#define _XHDI_H
+
+typedef long __CDECL (*Func)();
+
+//#define old_pun_ptr 	0x516
+
+#undef PUN_PTR
+//#define pun_ptr pun_ptr_usb
+
+#define MAX_LOGICAL_DRIVE	max_logical_drive
+
+/* AHDI */
+
+#define PUN_DEV           0x1F /* device number of HD */
+#define PUN_UNIT          0x07 /* Unit number */
+#define PUN_SCSI          0x08 /* 1=SCSI 0=ACSI */
+#define PUN_IDE           0x10 /* Falcon IDE */
+#define PUN_USB           0x20 /* USB */
+#define PUN_REMOVABLE     0x40 /* Removable media */
+#define PUN_VALID         0x80 /* zero if valid */
+
+#define PINFO_PUNS     0  // 2 bytes
+#define PINFO_PUN      2  // 16 bytes
+#define PINFO_PSTART  18  // 16 x 4 bytes
+#define PINFO_COOKIE  82  // 4 bytes
+#define PINFO_COOKPTR 86  // 4 bytes
+#define PINFO_VERNUM  90  // 2 bytes
+#define PINFO_MAXSIZE  92  // 2 bytes
+#define PINFO_PTYPE   94  // 16 x 4 bytes
+#define PINFO_PSIZE  158  // 16 x 4 bytes
+#define PINFO_FLAGS  222  // 16 x 2 bytes, internal use: B15:swap, B7:change, B0:bootable
+#define PINFO_BPB    256  // 16 x 32 bytes
+#define PINFO_SIZE   768
+
+struct pun_info
+{	
+	short		puns;			/* Number of HD's */
+	char		pun [16];		/* AND with masks below: */
+	long		pstart [16];
+	long		cookie;			/* 'AHDI' if following valid */
+	long		*cook_ptr;		/* Points to 'cookie' */
+	unsigned short	version_num;		/* AHDI version */
+	unsigned short	max_sect_siz;		/* Max logical sec size */
+	long		reserved[16];		/* Reserved */	
+};
+
+struct usb_pun_info
+{	
+	short		puns;			/* Number of HD's */
+	char		pun [16];		/* AND with masks below: */
+	long		pstart [16];
+	long		cookie;			/* 'AHDI' if following valid */
+	long		*cook_ptr;		/* Points to 'cookie' */
+	unsigned short	version_num;		/* AHDI version */
+	unsigned short	max_sect_siz;		/* Max logical sec size */
+	long		reserved[16];		/* Reserved */	
+	long		ptype[16];
+	long		psize[16];
+	unsigned short	flags[16];
+};
+	
+/* PARTITIONS TYPES */
+#define GEM		0x47454D   // GEM up to 16 MB
+#define BGM		0x42474D   // BGM over 16 MB
+#define RAW		0x524157   // RAW
+#define FAT16_32MB	0x4	   // DOS FAT16 up to 32 MB
+#define FAT16		0x6	   // DOS FAT16 over 32 MB
+#define FAT16_WIN95     0xE        // WIN95 FAT16
+#define FAT32           0xB        // FAT32
+#define FAT32_II	0xC	   // FAT32
+
+typedef struct xbra XBRA;
+struct xbra {
+	long  xb_magic;		/* "XBRA" = 0x58425241         */
+	long  xb_id;      	/* ID of four ASCII characters */
+	Func  xb_oldvec;	/* Old value of the vectors    */
+	short jump;
+  	Func  handle;
+};
+
+
+#endif /* _XHDI_H */