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added missing assignments and wrong pins for differential clock

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This commit is contained in:
Markus Fröschle
2014-08-09 17:34:08 +00:00
parent 4ba8ac1426
commit e9f5ee1ed3
1 changed files with 68 additions and 13 deletions
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81
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -378,7 +378,7 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
@@ -389,9 +389,9 @@ set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
set_global_assignment -name AUTO_DSP_RECOGNITION ON
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.5
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS OFF
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
@@ -423,8 +423,8 @@ set_location_assignment PIN_E11 -to DREQ1n
set_location_assignment PIN_A12 -to DACK1n
set_location_assignment PIN_B12 -to DACK0n
set_location_assignment PIN_T22 -to TOUT0n
set_location_assignment PIN_AA17 -to CLK_DDR_OUT
set_location_assignment PIN_AB17 -to CLK_DDR_OUTn
set_location_assignment PIN_AB17 -to CLK_DDR_OUT
set_location_assignment PIN_AA17 -to CLK_DDR_OUTn
set_location_assignment PIN_AB18 -to VCASn
set_location_assignment PIN_T18 -to VCSn
set_location_assignment PIN_W17 -to VRASn
@@ -584,9 +584,9 @@ set_location_assignment PIN_U1 -to SCSI_DRQn
set_location_assignment PIN_H1 -to SCSI_CDn
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
set_global_assignment -name EDA_TEST_BENCH_NAME ddr_ctlr_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ddr_ctlr_tb
@@ -608,9 +608,60 @@ set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:al
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[2]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[3]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[0]"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ns"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns"
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS OFF
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=54" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to CLK_MAIN -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "INTHANDLER:I_INTHANDLER|IRQn[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "INTHANDLER:I_INTHANDLER|IRQn[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "INTHANDLER:I_INTHANDLER|IRQn[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "INTHANDLER:I_INTHANDLER|IRQn[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "INTHANDLER:I_INTHANDLER|IRQn[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "INTHANDLER:I_INTHANDLER|IRQn[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "INTHANDLER:I_INTHANDLER|IRQn[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "INTHANDLER:I_INTHANDLER|IRQn[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "INTHANDLER:I_INTHANDLER|IRQn[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "INTHANDLER:I_INTHANDLER|IRQn[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "INTHANDLER:I_INTHANDLER|IRQn[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "INTHANDLER:I_INTHANDLER|IRQn[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[0] -to "INTHANDLER:I_INTHANDLER|IRQn[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[1] -to "INTHANDLER:I_INTHANDLER|IRQn[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[2] -to "INTHANDLER:I_INTHANDLER|IRQn[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[3] -to "INTHANDLER:I_INTHANDLER|IRQn[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[4] -to "INTHANDLER:I_INTHANDLER|IRQn[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[5] -to "INTHANDLER:I_INTHANDLER|IRQn[7]" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=6" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=6" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=6" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=7" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=32768" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_GAP_RECORD=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_MODE=TRANSITIONAL" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=29898" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=62976" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=32768" -section_id auto_signaltap_0
set_global_assignment -name SDC_FILE firebee.sdc
set_global_assignment -name SOURCE_FILE firebee.qsf
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DDR/DDR_CTRL.vhd
@@ -672,7 +723,11 @@ set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS OFF
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC OFF
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to CLK_DDR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to CLK_DDR_OUTn
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLK_DDR_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to CLK_DDR_OUT
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLK_DDR_OUT
set_global_assignment -name SLD_FILE db/stp_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top