From e96ee4a103d8c5bf98cd5581d6f21edb7dc32924 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 19:50:38 +0000 Subject: [PATCH] added derive_clock_uncertainty --- FPGA_quartus_ori/firebee1.qws | Bin 4717 -> 7010 bytes FPGA_quartus_ori/firebee1.sdc | 1 + 2 files changed, 1 insertion(+) diff --git a/FPGA_quartus_ori/firebee1.qws b/FPGA_quartus_ori/firebee1.qws index c338aba0201bdaba1b064ec006014f596c6b3b80..c422e6822462699cd0e9c3feebdc13054bbe201d 100644 GIT binary patch literal 7010 zcmeI0&ref95XYwlBS%lhg9l=aAtt3QJSe?^6buPQq6NK}ru4PaP$;%lNDS!NgYoJ= zVB$Z(!GFPvSG{;Q{s*G?ndy7{cr*}5lRlvPvb%3)=k3nUerMm#jt_{RZc0V+QkRD0 zWL>IKlVzwicm*jUbd~%=;<7~B3Y<7)38^Y?8OmjOY5Y}s(AEs)D{_UlwY`>ji@xJB zEpu{TCK&kzz2xb&L0yMdJ<9Yp4Yz_ORauo8c}UA+Mwm2N7itD-ih2^s(@77a<&wC} z?gL+TW_Bg!Si@F}Xg)ytj`$E3bLa%doAZ%UY%+ z2JOJrw?ss3+bnCUTyR!Bu#|rnb5s%2 zO=9KrBMwHsfBR}3=@^!xZ|M1_PcfszwBkL5DU)Ei2$~hQG4di$@d)0>tTl-D5oGn> zqj(RKU)x_;Bz5a}G+I9#KTZN5!VRH1u z?GSd3$)^7YJRGJePDqhw{ED`AG!T#cp}0j*o#%*GVVr)#mJ;P8b@L)y%ewbvbPI7; z&wvCFS?vY-Vq8n;49^_!wLeTl8%uVy)ms2d82+DTCG3)>xoIj`Ttc&y-8RGk&nTdA z0f+-fZzA+=O>Y$yQVEthZI6RY34Yq@u-!G-9ilEv_eRXSyz?=D_wA*Q24JSe35VPN DC&rj2 delta 793 zcmZWnO-mb56g_X!iAj}|B8_069a>$*k7RI~b`c1;ks=htRs@TVaTKYT(qt#%s+%rK zg7?7p3B+KcP@4Zd~*aSljg6H{(am8}7XOb*1tn{&?BEYxV1lmFiw5AV38}n2(?b*PBYu;$$4h8XNOu ze+(BsEx;gh`~*12N}jt*&o?>oq$*#TwqSObzKiuXg^m%f6rg5VY|-#Xen89ttozMU z&$QZ@U|eMC4O3s~&(O+@*BF1IA1;yV8HtZ5*Q5Cq<6#5^BQTVjkEHq+2XQIUXSeiw z=2!vNTU-!bC&0#~Fe@CT?r`${nMBra{<<(hx>vl=*QgN%hejmX$Riy$F-iI=UZN_j zw`kwa>)c~Ne4D#I6SNXU3Zvv(CFX7gD+r{(W!koc7O>xn4BpXm!lQmr(?zU1J71`_2Uu+0>#C~<()FFEkm>so J>Pjq}{{T;wq4)p* diff --git a/FPGA_quartus_ori/firebee1.sdc b/FPGA_quartus_ori/firebee1.sdc index b4e2637..49c93c7 100644 --- a/FPGA_quartus_ori/firebee1.sdc +++ b/FPGA_quartus_ori/firebee1.sdc @@ -61,6 +61,7 @@ derive_pll_clocks set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.100 set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.100 +derive_clock_uncertainty #************************************************************** # Set Input Delay