added a little bus toggling to the test bench

vhdl/backend/Altera/Firebee/firebee.qsf

@@ -687,13 +687,13 @@ set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
 set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd
 set_global_assignment -name EDA_TEST_BENCH_NAME firebee_tb -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME firebee_tb -section_id firebee_tb
-set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 s" -section_id firebee_tb
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 ms" -section_id firebee_tb
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME firebee_tb -section_id firebee_tb
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id firebee_tb
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb
 set_location_assignment PIN_T8 -to FB_CS_n[1]
 set_location_assignment PIN_T9 -to FB_CS_n[2]
 set_location_assignment PIN_V6 -to FB_CS_n[3]
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id firebee_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb

vhdl/rtl/vhdl/Video/Video_Top.vhd

@@ -212,7 +212,7 @@ BEGIN
 	clk_pixel <= clk_pixel_i;
 	fifo_clr <= fifo_clr_i;
 		
-	P_CLUT_ST_MC: PROCESS
+	p_clut_st_mc : PROCESS
 		-- This is the dual ported ram FOR the ST colour lookup tables.
 	 	VARIABLE clut_fa_index			: INTEGER;
 		VARIABLE clut_st_index			: INTEGER;
@@ -223,6 +223,7 @@ BEGIN
 		clut_fi_index := TO_INTEGER(UNSIGNED(fb_adr(9 DOWNTO 2)));
 
 		WAIT UNTIL RISING_EDGE(clk_main);
+        
 		IF clut_st_wr(0) = '1' THEN
 			clut_st(clut_st_index)(11 DOWNTO 8) <= fb_ad_in(27 DOWNTO 24);
 		END IF;
@@ -253,9 +254,9 @@ BEGIN
 		clut_st_out <= clut_st(clut_st_index);
 		clut_fa_out <= clut_fa(clut_fa_index);
 		clut_fbee_out <= clut_fi(clut_fi_index);
-	END PROCESS P_CLUT_ST_MC;
+	END PROCESS p_clut_st_mc;
 
-	P_CLUT_ST_PX: PROCESS
+	p_clut_st_px : PROCESS
 		VARIABLE clut_fa_index			: INTEGER;
 		VARIABLE clut_st_index			: INTEGER;
 		VARIABLE clut_fi_index			: INTEGER;
@@ -278,9 +279,9 @@ BEGIN
 		clut_fbee_r <= clut_fi(clut_fi_index)(23 DOWNTO 16);
 		clut_fbee_g <= clut_fi(clut_fi_index)(15 DOWNTO 8);
 		clut_fbee_b <= clut_fi(clut_fi_index)(7 DOWNTO 0);
-	END PROCESS P_CLUT_ST_PX;
+	END PROCESS p_clut_st_px;
 
-	P_VIDEO_OUT: PROCESS
+	p_video_out : PROCESS
 		VARIABLE video_out  : STD_LOGIC_VECTOR(23 DOWNTO 0);
 	BEGIN
 		WAIT UNTIL RISING_EDGE(clk_pixel_i);
@@ -296,7 +297,7 @@ BEGIN
 		red <= video_out(23 DOWNTO 16);
 		green <= video_out(15 DOWNTO 8);
 		blue <= video_out(7 DOWNTO 0);
-	END PROCESS P_VIDEO_OUT;
+	END PROCESS p_video_out;
 
 	P_CC: PROCESS
         VARIABLE cc24_i : STD_LOGIC_VECTOR(31 DOWNTO 0);

vhdl/testbenches/firebee_tb.vhd

@@ -173,11 +173,9 @@ ARCHITECTURE beh OF firebee_tb IS
         );
     END COMPONENT firebee;
     
-    SIGNAL clock            : STD_LOGIC := '0';    -- main clock
+    SIGNAL rsto_mcf_n       : STD_LOGIC := '0';                -- reset SIGNAL from Coldfire
-    
+    SIGNAL clk_33m          : STD_LOGIC := '0';                -- 33 MHz clock
-    SIGNAL rsto_mcf_n       : STD_LOGIC;                -- reset SIGNAL from Coldfire
+    SIGNAL clk_main         : STD_LOGIC := '0';                -- 33 MHz clock
-    SIGNAL clk_33m          : STD_LOGIC;                -- 33 MHz clock
-    SIGNAL clk_main         : STD_LOGIC;                -- 33 MHz clock
     
     SIGNAL clk_24m576       : STD_LOGIC;            -- 
     SIGNAL clk_25m          : STD_LOGIC;
@@ -187,17 +185,17 @@ ARCHITECTURE beh OF firebee_tb IS
     
     SIGNAL fb_ad            : STD_LOGIC_VECTOR (31 DOWNTO 0);
     SIGNAL fb_ale           : STD_LOGIC;
-    SIGNAL fb_burst_n       : STD_LOGIC;
+    SIGNAL fb_burst_n       : STD_LOGIC := '1';
-    SIGNAL fb_cs_n          : STD_LOGIC_VECTOR (3 DOWNTO 1);
+    SIGNAL fb_cs_n          : STD_LOGIC_VECTOR (3 DOWNTO 1) := "111";
-    SIGNAL fb_size          : STD_LOGIC_VECTOR (1 DOWNTO 0);
+    SIGNAL fb_size          : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-    SIGNAL fb_oe_n          : STD_LOGIC;
+    SIGNAL fb_oe_n          : STD_LOGIC := '1';
-    SIGNAL fb_wr_n          : STD_LOGIC;
+    SIGNAL fb_wr_n          : STD_LOGIC := '1';
-    SIGNAL fb_ta_n          : STD_LOGIC;
+    SIGNAL fb_ta_n          : STD_LOGIC := '1';
             
     SIGNAL dack1_n          : STD_LOGIC;
     SIGNAL dreq1_n          : STD_LOGIC;
     
-    SIGNAL master_n         : STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
+    SIGNAL master_n         : STD_LOGIC := '0'; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
     SIGNAL tout0_n          : STD_LOGIC; -- Not used so far.
     
     SIGNAL led_fpga_ok      : STD_LOGIC;
@@ -330,6 +328,8 @@ ARCHITECTURE beh OF firebee_tb IS
     SIGNAL IDE_RDn          : STD_LOGIC;
     SIGNAL IDE_CSn          : STD_LOGIC_VECTOR (1 DOWNTO 0);
     
+    SIGNAL a                : UNSIGNED (31 DOWNTO 0) := (OTHERS => '0');
+
 BEGIN
     I_FIREBEE : firebee
     PORT MAP (
@@ -482,4 +482,26 @@ BEGIN
         dm              => UNSIGNED(vdm (3 DOWNTO 2)),
         dqs             => vd_qs (3 DOWNTO 2)
     );
+    
+    rsto_mcf_n <= '1' AFTER 1 ns;
+    
+    p_main_clk : PROCESS
+    BEGIN
+        WAIT FOR 30.03 ns;
+        clk_main <= NOT clk_main;
+    END PROCESS;
+    
+    stimulate_33mHz_clock : PROCESS
+    BEGIN
+        WAIT FOR 30.3 ns;
+        clk_33m <= NOT clk_33m;
+    END PROCESS;
+    
+    stimulate_bus : PROCESS
+    BEGIN
+        WAIT UNTIL RISING_EDGE(clk_main);
+        fb_ad <= STD_LOGIC_VECTOR (a);      -- put something (rather meaningless) on the FlexBus
+        a <= a + 1;
+        fb_ale <= a(0);                     -- just toggle for now
+    END PROCESS;
 END beh;