added more radeon driver files

2013-12-27 13:15:13 +00:00
parent e5a7d03f64
commit e5cedeba3d
6 changed files with 1444 additions and 144 deletions
--- a/2
+++ b/2
@@ -107,6 +107,8 @@ CSRCS= \
 	video.c \
 	\
 	radeon_base.c \
+	radeon_accel.c \
+	radeon_cursor.c \
 	\
 	basflash.c \
 	basflash_start.c 
--- a/include/pci.h
+++ b/include/pci.h
@@ -22,6 +22,7 @@
 */

 #include <stdint.h>
+#include "util.h" 	/* for swpX() */

 #define	 PCI_MEMORY_OFFSET	(0x80000000)
 #define	 PCI_MEMORY_SIZE	(0x40000000)	/* 1 GByte PCI memory window */
--- a/include/radeonfb.h
+++ b/include/radeonfb.h
@@ -498,14 +498,9 @@ extern uint32_t _swap_int32_t(uint32_t val);
 #define OUTREG(addr,val)	(*((uint32_t *)(rinfo->mmio_base+addr)) = _swap_int32_t(val))

 extern int32_t *tab_funcs_pci;
-
-#define BIOS_IN8(v)  	(Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v))
-#define BIOS_IN16(v) 	((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \
-			  ((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8))
-#define BIOS_IN32(v) 	((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \
-			  ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8) | \
-			  ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+2) << 16) | \
-			  ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+3) << 24))
+#define BIOS_IN8(v)		(* ((uint8_t *) rinfo->bios_seg_phys + v))
+#define BIOS_IN16(v)	(swpw(*(uint16_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))
+#define BIOS_IN32(v)	(swpl(*(uint32_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))

 #define ADDRREG(addr)			((volatile uint32_t *)(rinfo->mmio_base + (addr)))
 #define OUTREGP(addr,val,mask)	_OUTREGP(rinfo, addr, val, mask)
@@ -602,79 +597,73 @@ do {									\
 #define radeonfb_engine_init(rinfo) RADEONEngineInit(rinfo)
 #define radeon_engine_idle() RADEONWaitForIdleMMIO(rinfo)

-static inline int32_t radeonfb_sync(struct fb_info *info)
+static inline int radeonfb_sync(struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
 	radeon_engine_idle();
 	return 0;
 }

-extern void RADEONRestoreAccelStateMMIO(struct fb_info *info);
-extern void RADEONSetupForSolidFillMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask);
-extern void RADEONSubsequentSolidFillRectMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
-extern void RADEONSetupForSolidLineMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask);
-extern void RADEONSubsequentSolidHorVertLineMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);   
-
-extern void RADEONSubsequentSolidTwoPointLineMMIO(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb,
-						int32_t yb, int32_t flags);  
-extern void RADEONSetupForDashedLineMMIO(struct fb_info *info, int32_t fg, int32_t bg,
-							int32_t rop, int32_t planemask, int32_t length, uint8_t *pattern);
-extern void RADEONSubsequentDashedTwoPointLineMMIO(struct fb_info *info,
-            int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);  
-extern void RADEONSetupForScreenToScreenCopyMMIO(struct fb_info *info,
-            int32_t xdir, int32_t ydir, int32_t rop, int32_t planemask, int32_t trans_color);
-extern void RADEONSubsequentScreenToScreenCopyMMIO(struct fb_info *info,
-            int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);   
-extern void RADEONScreenToScreenCopyMMIO(struct fb_info *info,
-            int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
-extern void RADEONSetupForMono8x8PatternFillMMIO(struct fb_info *info,
-            int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, int32_t planemask);
-extern void RADEONSubsequentMono8x8PatternFillRectMMIO(struct fb_info *info,
-            int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
-extern void RADEONSetupForScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info, 
-            int32_t fg, int32_t bg, int32_t rop, int32_t planemask);
-extern void RADEONSubsequentScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info,
-            int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
-extern void RADEONSubsequentScanlineMMIO(struct fb_info *info, uint32_t *buf);
-extern void RADEONSetupForScanlineImageWriteMMIO(struct fb_info *info,
-            int32_t rop, int32_t planemask, int32_t trans_color, int32_t bpp);
-extern void RADEONSubsequentScanlineImageWriteRectMMIO(struct fb_info *info,
-            int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);  
-extern void RADEONSetClippingRectangleMMIO(struct fb_info *info,
-            int32_t xa, int32_t ya, int32_t xb, int32_t yb);
-extern void RADEONDisableClippingMMIO(struct fb_info *info);
-
-#ifndef MCF5445X
-extern int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info, 
-           int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags);
-extern int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info,
-           int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags);
-extern void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info,
-            int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height);
-#else
-static __inline__ int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info, 
- int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags)
-{ return FALSE; }
-static __inline__ int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info,
- int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags)
-{ return FALSE; }
-static __inline__ void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info,
- int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height) { }
-#endif /* MCF5445X */
+extern void radeon_restore_accel_state_mmio(struct fb_info *info);
+extern void radeon_setup_for_solid_fill(struct fb_info *info, int color, int rop, unsigned int planemask);
+extern void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int x, int y, int w, int h);
+extern void radeon_setup_for_solid_line_mmio(struct fb_info *info, int color, int rop, unsigned int planemask);
+extern void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int x, int y, int len, int dir);   
+extern void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info, int xa, int ya, int xb,
+														int yb, int flags);  
+extern void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int fg, int bg,
+												int rop, unsigned int planemask, int length, unsigned char *pattern);
+extern void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info,
+            				int xa, int ya, int xb, int yb, int flags, int phase);  
+extern void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info,
+            				int xdir, int ydir, int rop, unsigned int planemask, int trans_color);
+extern void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info,
+            				int xa, int ya, int xb, int yb, int w, int h);   
+extern void radeon_screen_to_screen_copy_mmio(struct fb_info *info,
+            				int xa, int ya, int xb, int yb, int w, int h, int rop);
+extern void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info,
+            			int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask);
+extern void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info,
+            				int patternx, int patterny, int x, int y, int w, int h);
+extern void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info, 
+            				int fg, int bg, int rop, unsigned int planemask);
+extern void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
+            				int x, int y, int w, int h, int skipleft);
+extern void radeon_subsequent_scanline_mmio(struct fb_info *info, int *buf);
+extern void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info,
+            							int rop, unsigned int planemask, int trans_color, int bpp);
+extern void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info,
+            				int x, int y, int w, int h, int skipleft);  
+extern void radeon_set_clipping_rectangle_mmio(struct fb_info *info,
+            				int xa, int ya, int xb, int yb);
+extern void radeon_disable_clipping_mmio(struct fb_info *info);

+extern int32_t radeon_setup_for_cpu_to_screen_alpha_texture_mmio(struct fb_info *info, 
+           					int op, int red, int green, int blue,
+							int alpha, int maskFormat, int dstFormat,
+							uint8_t *alphaPtr, int alphaPitch,
+							int width, int height, int32_t flags);
+extern int32_t radeon_setup_for_cpu_to_screen_texture_mmio(struct fb_info *info, int32_t op,
+							uint32_t srcFormat, uint32_t dstFormat,
+							uint8_t *texPtr, int32_t texPitch,
+							int32_t width, int32_t height, int32_t flags);
+extern void radeon_subsequent_cpu_to_screen_texture_mmio(struct fb_info *info,
+            				int32_t dstx, int32_t dsty,
+							int32_t srcx, int32_t srcy,
+							int32_t width, int32_t height);
 /* Cursor functions */
-extern void RADEONSetCursorColors(struct fb_info *info, int32_t bg, int32_t fg);
-extern void RADEONSetCursorPosition(struct fb_info *info, int32_t x, int32_t y);
-extern void RADEONLoadCursorImage(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom);
-extern void RADEONHideCursor(struct fb_info *info);
-extern void RADEONShowCursor(struct fb_info *info);
-extern int32_t RADEONCursorInit(struct fb_info *info);
+extern void radeon_set_cursor_colors(struct fb_info *info, int32_t bg, int32_t fg);
+extern void radeon_set_cursor_position(struct fb_info *info, int32_t x, int32_t y);
+extern void radeon_load_cursor_image(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom);
+extern void radeon_hide_cursor(struct fb_info *info);
+extern void radeon_show_corsor(struct fb_info *info);
+extern int32_t radeon_cursor_init(struct fb_info *info);

 /* Other functions */
 extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch);
-extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only);
-int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green,
-    uint32_t blue, uint32_t transp, struct fb_info *info);
+extern void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only);
+int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+    					unsigned blue, unsigned transp, struct fb_info *info);
 extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent);
 extern void radeonfb_pci_unregister(void);

--- a/radeon/radeon_accel.c
+++ b/radeon/radeon_accel.c
--- a/radeon/radeon_base.c
+++ b/radeon/radeon_base.c
@@ -57,6 +57,7 @@
 #include "radeonfb.h"
 #include "edid.h"
 #include "ati_ids.h"
+#include "exceptions.h"		/* for set_ipl() */

 #ifdef DRIVER_IN_ROM
 extern void run_bios(struct radeonfb_info *rinfo);
@@ -894,7 +895,7 @@ int radeonfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  return 0;
 }

-int radeonfb_ioctl(uint32_t cmd, uint32_t arg, struct fb_info *info)
+int radeonfb_ioctl(unsigned int cmd, unsigned long arg, struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
 	uint32_t tmp;
@@ -1067,8 +1068,9 @@ int radeonfb_blank(int blank, struct fb_info *info)
 }

 static int radeon_setcolreg(unsigned regno, unsigned red, unsigned green,
-                            unsigned blue, unsigned transp, struct radeonfb_info *rinfo)
+                            unsigned blue, unsigned transp, struct fb_info *info)
 {
+	struct radeonfb_info *rinfo = info->par;
 	uint32_t pindex;
 	if (regno > 255)
 		return 1;
@@ -1110,8 +1112,8 @@ static int radeon_setcolreg(unsigned regno, unsigned red, unsigned green,
 	return 0;
 }

-int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green,
-    uint32_t blue, uint32_t transp, struct fb_info *info)
+int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+    						unsigned blue, unsigned transp, struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
 	uint32_t dac_cntl2, vclk_cntl = 0;
@@ -1131,7 +1133,7 @@ int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green,
 			OUTREG(DAC_CNTL2, dac_cntl2);
 		}
 	}
-	rc = radeon_setcolreg(regno, red, green, blue, transp, rinfo);
+	rc = radeon_setcolreg(regno, red, green, blue, transp, info);
 	if (!rinfo->asleep && rinfo->is_mobility)
 		OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
 	return rc;
@@ -1260,15 +1262,15 @@ static void radeon_timer_func(void)
 {
 	struct fb_info *info = info_fvdi;
 	struct radeonfb_info *rinfo = info->par;
-	static int32_t start_timer;
 	struct fb_var_screeninfo var;
 	uint32_t x, y;
 	int chg, disp;

+#ifdef FIXME_LATER
+	static int32_t start_timer;
 	/* delayed LVDS panel power up/down */
 	if (rinfo->lvds_timer)
 	{
-#ifdef FIXME_LATER
 		if (!start_timer)
 			start_timer = *_hz_200;

@@ -1278,10 +1280,10 @@ static void radeon_timer_func(void)
 			radeon_engine_idle();
 			OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
 		}
-#endif
 	}
 	else
 		start_timer = 0;
+#endif

 	if (rinfo->RenderCallback != NULL)
 		rinfo->RenderCallback(rinfo);
@@ -1311,25 +1313,14 @@ static void radeon_timer_func(void)
 	if ((info->var.xres_virtual != info->var.xres)
 	 || (info->var.yres_virtual != info->var.yres))
 	{
-#ifdef __mcoldfire__
-		asm volatile (
-			" clr.l -(SP)\n\t"
-			" move.l D0,-(SP)\n\t"
-			" move.w SR,D0\n\t"
-			" move.l D0,4(SP)\n\t"
-			" or.l #0x700,D0\n\t"   /* disable interrupts */
-			" move.w D0,SR\n\t"
-			" move.l (SP)+,D0\n\t" );
-#else
-		asm volatile (
-			" move.w SR,-(SP)\n\t"
-			" or.w #0x700,SR\n\t" ); /* disable interrupts */
-#endif
+		int ipl;
+		ipl = set_ipl(0);
+
 		chg = 0;
 		x = info->var.xoffset;
 		y = info->var.yoffset;
-		if (((x + info->var.xres) < info->var.xres_virtual)
-		 && (rinfo->cursor_x >= (info->var.xres - 8)))
+
+		if (((x + info->var.xres) < info->var.xres_virtual) && (rinfo->cursor_x >= (info->var.xres - 8)))
 		{
 			x += 8;
 			chg = 1;
@@ -1339,8 +1330,7 @@ static void radeon_timer_func(void)
 			x -= 8;
 			chg = 1;
 		}
-		if (((y + info->var.yres) < info->var.yres_virtual)
-		 && (rinfo->cursor_y >= (info->var.yres - 8)))
+		if (((y + info->var.yres) < info->var.yres_virtual) && (rinfo->cursor_y >= (info->var.yres - 8)))
 		{
 			y += 8;
 			chg = 1;
@@ -1350,6 +1340,7 @@ static void radeon_timer_func(void)
 			y -= 8;
 			chg = 1;
 		}
+
 		if (chg)
 		{
 			memcpy(&var, &info->var, sizeof(struct fb_var_screeninfo));
@@ -1357,22 +1348,12 @@ static void radeon_timer_func(void)
 			var.yoffset = y;
 			disp = rinfo->cursor_show;
 			if (disp)
-				RADEONHideCursor(info);
+				info->fbops->HideCursor(info);
 			fb_pan_display(info,&var);
 			if (disp)
-				RADEONShowCursor(info);
+				info->fbops->ShowCursor(info);
 		}
-#ifdef __mcoldfire__
-		asm volatile (
-			" move.l D0,-(SP)\n\t"
-			" move.l 4(SP),D0\n\t"
-			" move.w D0,SR\n\t"
-			" move.l (SP)+,D0\n\t"
-			" addq.l #4,SP\n\t" );		
-#else
-			asm volatile (
-				" move.w (SP)+,SR\n\r" );
-#endif
+		set_ipl(ipl);
 	}
 }

@@ -1553,14 +1534,20 @@ int radeonfb_set_par(struct fb_info *info)
 	struct radeonfb_info *rinfo = info->par;
 	struct fb_var_screeninfo *mode = &info->var;
 	struct radeon_regs *newmode;
-	int hTotal, vTotal, hSyncStart, hSyncEnd, hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
+	int hTotal, vTotal, hSyncStart, hSyncEnd, vSyncStart, vSyncEnd;
+	// FIXME: int hSyncPol; this is not used anywhere
+	// FIXME: int vSyncPol; this is not used anywhere
+	// FIXME: int cSync;	this is not used anywhere
 	static uint8_t hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
 	static uint8_t hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
 	uint32_t sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
 	int i, freq;
 	int format = 0;
 	int nopllcalc = 0;
-	int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
+	int hsync_start;
+	int hsync_fudge;
+	// int bytpp; FIXME: this doesn't seem to be used anywhere
+	int hsync_wid, vsync_wid;
 	int primary_mon = PRIMARY_MONITOR(rinfo);
 	int depth = var_to_depth(mode);
 	int use_rmx = 0;
@@ -1632,17 +1619,20 @@ int radeonfb_set_par(struct fb_info *info)
 		vsync_wid = 1;
 	else if (vsync_wid > 0x1f)	/* max */
 		vsync_wid = 0x1f;
-	hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
-	vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
-	cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
+	// FIXME: this doesn't seem to be used anywhere hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
+	// FIXME: this doesn't seem to be used anywhere vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
+	// FIXME: this doesn't seem to be used anywhere cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
 	format = radeon_get_dstbpp(depth);
-	bytpp = mode->bits_per_pixel >> 3;
+	// FIXME: this doesn't seem to be used anywhere bytpp = mode->bits_per_pixel >> 3;
+
 	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
 		hsync_fudge = hsync_fudge_fp[format-1];
 	else
 		hsync_fudge = hsync_adj_tab[format-1];
+
 	if (mode->vmode & FB_VMODE_DOUBLE)
 		hsync_fudge = 0; /* todo: need adjust */		
+
 	hsync_start = hSyncStart - 8 + hsync_fudge;
 	newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | (format << 8);
 	if (mode->vmode & FB_VMODE_DOUBLE)
@@ -1815,47 +1805,47 @@ static void radeonfb_check_modes(struct fb_info *info, struct mode_option *resol
 static struct fb_ops radeonfb_ops =
 {
 	.fb_check_var = radeonfb_check_var,
-	.fb_setcolreg = radeonfb_setcolreg,
 	.fb_set_par = radeonfb_set_par,
+	.fb_setcolreg = radeonfb_setcolreg,
 	.fb_pan_display = radeonfb_pan_display,
 	.fb_blank = radeonfb_blank,
 	.fb_sync = radeonfb_sync,
 	.fb_ioctl = radeonfb_ioctl,
 	.fb_check_modes = radeonfb_check_modes,
-	.SetupForSolidFill = RADEONSetupForSolidFillMMIO,
-	.SubsequentSolidFillRect = RADEONSubsequentSolidFillRectMMIO,
-	.SetupForSolidLine = RADEONSetupForSolidLineMMIO,
-	.SubsequentSolidHorVertLine = RADEONSubsequentSolidHorVertLineMMIO,
-	.SubsequentSolidTwoPointLine = RADEONSubsequentSolidTwoPointLineMMIO,
-	.SetupForDashedLine = RADEONSetupForDashedLineMMIO,
-	.SubsequentDashedTwoPointLine = RADEONSubsequentDashedTwoPointLineMMIO,
-	.SetupForScreenToScreenCopy = RADEONSetupForScreenToScreenCopyMMIO,
-	.SubsequentScreenToScreenCopy = RADEONSubsequentScreenToScreenCopyMMIO,
-	.ScreenToScreenCopy = RADEONScreenToScreenCopyMMIO,
-	.SetupForMono8x8PatternFill = RADEONSetupForMono8x8PatternFillMMIO,
-	.SubsequentMono8x8PatternFillRect = RADEONSubsequentMono8x8PatternFillRectMMIO,
-	.SetupForScanlineCPUToScreenColorExpandFill = RADEONSetupForScanlineCPUToScreenColorExpandFillMMIO,
-	.SubsequentScanlineCPUToScreenColorExpandFill = RADEONSubsequentScanlineCPUToScreenColorExpandFillMMIO,
-	.SubsequentScanline = RADEONSubsequentScanlineMMIO,	
-	.SetupForScanlineImageWrite = RADEONSetupForScanlineImageWriteMMIO,
-	.SubsequentScanlineImageWriteRect = RADEONSubsequentScanlineImageWriteRectMMIO,
-	.SetClippingRectangle = RADEONSetClippingRectangleMMIO,
-	.DisableClipping = RADEONDisableClippingMMIO,
+	.SetupForSolidFill = radeon_setup_for_solid_fill,
+	.SubsequentSolidFillRect = radeon_subsequent_solid_fill_rect_mmio,
+	.SetupForSolidLine = radeon_setup_for_solid_line_mmio,
+	.SubsequentSolidHorVertLine = radeon_subsequent_solid_hor_vert_line_mmio,
+	.SubsequentSolidTwoPointLine = radeon_subsequent_solid_two_point_line_mmio,
+	.SetupForDashedLine = radeon_setup_for_dashed_line_mmio,
+	.SubsequentDashedTwoPointLine = radeon_subsequent_dashed_two_point_line_mmio,
+	.SetupForScreenToScreenCopy = radeon_setup_for_screen_to_screen_copy_mmio,
+	.SubsequentScreenToScreenCopy = radeon_subsequent_screen_to_screen_copy_mmio,
+	.ScreenToScreenCopy = radeon_screen_to_screen_copy_mmio,
+	.SetupForMono8x8PatternFill = radeon_setup_for_mono_8x8_pattern_fill_mmio,
+	.SubsequentMono8x8PatternFillRect = radeon_subsequent_mono_8x8_pattern_fill_rect_mmio,
+	.SetupForScanlineCPUToScreenColorExpandFill = radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio,
+	.SubsequentScanlineCPUToScreenColorExpandFill = radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio,
+	.SubsequentScanline = radeon_subsequent_scanline_mmio,
+	.SetupForScanlineImageWrite = radeon_setup_for_scanline_image_write_mmio,
+	.SubsequentScanlineImageWriteRect = radeon_subsequent_scanline_image_write_rect_mmio,
+	.SetClippingRectangle = radeon_set_clipping_rectangle_mmio,
+	.DisableClipping = radeon_disable_clipping_mmio,
 #ifdef RADEON_RENDER
-	.SetupForCPUToScreenAlphaTexture = RADEONSetupForCPUToScreenAlphaTextureMMIO,
-	.SetupForCPUToScreenTexture = RADEONSetupForCPUToScreenTextureMMIO,
-	.SubsequentCPUToScreenTexture = RADEONSubsequentCPUToScreenTextureMMIO,
+	.SetupForCPUToScreenAlphaTexture = radeon_setup_for_cpu_to_screen_alpha_texture_mmio,
+	.SetupForCPUToScreenTexture = radeon_setup_for_cpu_to_screen_texture_mmio,
+	.SubsequentCPUToScreenTexture = radeon_subsequent_cpu_to_screen_texture_mmio,
 #else
 	.SetupForCPUToScreenAlphaTexture = NULL,
 	.SetupForCPUToScreenTexture = NULL,
 	.SubsequentCPUToScreenTexture = NULL,
 #endif /* RADEON_RENDER */
-	.SetCursorColors = RADEONSetCursorColors,
-	.SetCursorPosition = RADEONSetCursorPosition,
-	.LoadCursorImage = RADEONLoadCursorImage,
-	.HideCursor = RADEONHideCursor,
-	.ShowCursor = RADEONShowCursor,
-	.CursorInit = RADEONCursorInit,
+	.SetCursorColors = radeon_set_cursor_colors,
+	.SetCursorPosition = radeon_set_cursor_position,
+	.LoadCursorImage = radeon_load_cursor_image,
+	.HideCursor = radeon_hide_cursor,
+	.ShowCursor = radeon_show_cursor,
+	.CursorInit = radeon_cursor_init,
 	.WaitVbl = radeon_wait_vbl,
 };

--- a/radeon/radeon_cursor.c
+++ b/radeon/radeon_cursor.c
@@ -0,0 +1,312 @@
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c,v 1.26 2003/11/10 18:41:22 tsi Exp $ */
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ *                VA Linux Systems Inc., Fremont, California.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation on the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
+ * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Authors:
+ *   Kevin E. Martin <martin@xfree86.org>
+ *   Rickard E. Faith <faith@valinux.com>
+ *
+ * References:
+ *
+ * !!!! FIXME !!!!
+ *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
+ *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
+ *   1999.
+ *
+ *   RAGE 128 Software Development Manual (Technical Reference Manual P/N
+ *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
+ *
+ */
+
+#include "radeonfb.h"
+
+#define CURSOR_WIDTH	64
+#define CURSOR_HEIGHT	64
+
+/*
+ * The cursor bits are always 32bpp.  On MSBFirst buses,
+ * configure byte swapping to swap 32 bit units when writing
+ * the cursor image.  Byte swapping must always be returned
+ * to its previous value before returning.
+ */
+#define CURSOR_SWAPPING_DECL_MMIO
+#define CURSOR_SWAPPING_DECL	    unsigned long  __surface_cntl=0;
+#define CURSOR_SWAPPING_START() \
+	if(rinfo->big_endian) \
+    OUTREG(SURFACE_CNTL, \
+	   ((__surface_cntl = INREG(SURFACE_CNTL)) | \
+	    NONSURF_AP0_SWP_32BPP) & \
+	   ~NONSURF_AP0_SWP_16BPP);
+#define CURSOR_SWAPPING_END() \
+	if(rinfo->big_endian) \
+	(OUTREG(SURFACE_CNTL, __surface_cntl));
+
+/* Set cursor foreground and background colors */
+void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
+{
+	struct radeonfb_info *rinfo = info->par;
+	unsigned long *pixels = (unsigned long *)(pointer)((unsigned long)rinfo->fb_base+rinfo->cursor_start);
+	int pixel, i;
+	CURSOR_SWAPPING_DECL_MMIO
+	CURSOR_SWAPPING_DECL
+//	DPRINTVALHEX("radeonfb: RADEONSetCursorColors: cursor_start ",rinfo->cursor_start);
+//	DPRINT("\r\n");
+	fg |= 0xff000000;
+	bg |= 0xff000000;
+	/* Don't recolour the image if we don't have to. */
+	if(fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
+		return;
+	CURSOR_SWAPPING_START();
+	/* Note: We assume that the pixels are either fully opaque or fully
+	 * transparent, so we won't premultiply them, and we can just
+	 * check for non-zero pixel values; those are either fg or bg
+	 */
+	for(i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
+		if((pixel = *pixels))
+			*pixels = (pixel == rinfo->cursor_fg) ? fg : bg;
+	CURSOR_SWAPPING_END();
+	rinfo->cursor_fg = fg;
+	rinfo->cursor_bg = bg;
+}
+
+/* Set cursor position to (x,y) with offset into cursor bitmap at
+ * (xorigin,yorigin)
+ */
+void radeon_set_cursor_position(struct fb_info *info, int x, int y)
+{
+	struct radeonfb_info *rinfo = info->par;
+	struct fb_var_screeninfo *mode = &info->var;
+	int xorigin = 0;
+	int yorigin = 0;
+	if(mode->vmode & FB_VMODE_DOUBLE)
+		y <<= 1;
+	if(x < 0)
+		xorigin = 1 - x;
+	if(y < 0)
+	  yorigin = 1 - y;
+//	DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start);
+//	DPRINTVAL(" x ",x);
+//	DPRINTVAL(" y ",y);
+//	DPRINT("\r\n");
+	OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK  | (xorigin << 16) | yorigin));
+	OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
+	OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256);
+	rinfo->cursor_x = (unsigned long)x;
+	if(mode->vmode & FB_VMODE_DOUBLE)
+		rinfo->cursor_y = (unsigned long)y >> 1;
+	else
+		rinfo->cursor_y = (unsigned long)y;
+}
+
+/* Copy cursor image from `image' to video memory.  RADEONSetCursorPosition
+ * will be called after this, so we can ignore xorigin and yorigin.
+ */
+void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom)
+{
+	struct radeonfb_info *rinfo = info->par;
+	unsigned long *d = (unsigned long *)(pointer)((unsigned long)rinfo->fb_base+rinfo->cursor_start);
+	unsigned long save = 0;
+	unsigned short chunk, mchunk;
+	unsigned long i, j, k;
+	CURSOR_SWAPPING_DECL
+//	DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start);
+//	DPRINT("\r\n");	
+	save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20);
+	save |= (unsigned long) (2 << 20);
+	OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN);
+	/*
+	 * Convert the bitmap to ARGB32.
+	 */
+	CURSOR_SWAPPING_START();
+#define ARGB_PER_CHUNK	(8 * sizeof (chunk))
+	switch(zoom)
+	{
+	case 1:
+	default:
+		for(i = 0; i < CURSOR_HEIGHT; i++)
+		{
+			if(i < 16)
+			{
+				mchunk = *mask++;
+				chunk = *data++;
+			}
+			else
+				mchunk = chunk = 0;
+			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
+			{
+				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+				{
+					if(mchunk & 0x8000)
+					{
+						if(chunk & 0x8000)
+							*d++ = 0xff000000; /* Black, fully opaque. */				
+						else
+							*d++ = 0xffffffff; /* White, fully opaque. */
+					}			
+					else
+						*d++ = 0x00000000; /* White/Black, fully transparent. */			
+				}
+			}
+		}
+		break;
+	case 2:
+		for(i = 0; i < CURSOR_HEIGHT; i++)
+		{
+			if(i < 16*2)
+			{
+				mchunk = *mask;
+				chunk = *data;
+				if((i & 1) == 1)
+				{
+					mask++;
+					data++;
+				}		
+			}
+			else
+				mchunk = chunk = 0;
+			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
+			{
+				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+				{
+					if(mchunk & 0x8000)
+					{
+						if(chunk & 0x8000)
+						{
+							*d++ = 0xff000000; /* Black, fully opaque. */				
+							*d++ = 0xff000000; 
+						}
+						else
+						{
+							*d++ = 0xffffffff; /* White, fully opaque. */
+							*d++ = 0xffffffff;							
+						}
+					}			
+					else
+					{
+						*d++ = 0x00000000; /* White/Black, fully transparent. */			
+						*d++ = 0x00000000;
+					}
+				}
+			}
+		}
+		break;
+	case 4:
+		for(i = 0; i < CURSOR_HEIGHT; i++)
+		{
+			if(i < 16*4)
+			{
+				mchunk = *mask;
+				chunk = *data;
+				if((i & 3) == 3)
+				{
+					mask++;
+					data++;
+				}		
+			}
+			else
+				mchunk = chunk = 0;
+			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
+			{
+				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+				{
+					if(mchunk & 0x8000)
+					{
+						if(chunk & 0x8000)
+						{
+							*d++ = 0xff000000; /* Black, fully opaque. */				
+							*d++ = 0xff000000; 
+							*d++ = 0xff000000;
+							*d++ = 0xff000000;
+						}
+						else
+						{
+							*d++ = 0xffffffff; /* White, fully opaque. */
+							*d++ = 0xffffffff;							
+							*d++ = 0xffffffff;
+							*d++ = 0xffffffff;				
+						}
+					}			
+					else
+					{
+						*d++ = 0x00000000; /* White/Black, fully transparent. */			
+						*d++ = 0x00000000;
+						*d++ = 0x00000000;
+						*d++ = 0x00000000;
+					}
+				}
+			}
+		}
+		break;
+	}
+	CURSOR_SWAPPING_END();
+	rinfo->cursor_bg = 0xffffffff; /* White, fully opaque. */
+	rinfo->cursor_fg = 0xff000000; /* Black, fully opaque. */		
+	OUTREG(CRTC_GEN_CNTL, save);
+}
+
+/* Hide hardware cursor. */
+void radeon_hide_cursor(struct fb_info *info)
+{
+	struct radeonfb_info *rinfo = info->par;
+//	DPRINT("radeonfb: RADEONHideCursor\r\n");
+	OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
+	rinfo->cursor_show = 0;
+}
+
+/* Show hardware cursor. */
+void radeon_show_cursor(struct fb_info *info)
+{
+	struct radeonfb_info *rinfo = info->par;
+//	DPRINT("radeonfb: RADEONShowCursor\r\n");
+	OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN);
+	rinfo->cursor_show = 1;
+}
+
+/* Initialize hardware cursor support. */
+long radeon_cursor_init(struct fb_info *info)
+{
+	struct radeonfb_info *rinfo = info->par;
+	int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
+	unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes+256);
+//	DPRINTVALHEX("radeonfb: RADEONCursorInit: fbarea ",fbarea);
+	if(!fbarea)
+		rinfo->cursor_start = 0;
+	else
+	{
+		unsigned short data[16], mask[16];
+		memset(data, 0, sizeof(data));
+		memset(mask, 0, sizeof(data));		
+		rinfo->cursor_start = RADEON_ALIGN(fbarea - (unsigned long)rinfo->fb_base, 256);
+		rinfo->cursor_end = rinfo->cursor_start + size_bytes;
+		RADEONLoadCursorImage(info, mask, data, 1);
+	}
+//	DPRINTVALHEX(" cursor_start ",rinfo->cursor_start);
+//	DPRINT("\r\n");
+	return(rinfo->cursor_start ? fbarea : 0);
+}