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cleaned up. X86emu does not work with debug trace on currently.

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This commit is contained in:
Markus Fröschle
2014-01-03 21:03:35 +00:00
parent 85fc19e998
commit e5c9d63059
28 changed files with 1254 additions and 1227 deletions
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344
x86emu/x86pcibios.c
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@@ -2,6 +2,7 @@
#include "pci.h"
#include "x86emu.h"
#include "x86pcibios.h"
#include "x86debug.h"
extern unsigned short offset_port;
@@ -11,232 +12,147 @@ int x86_pcibios_emulator()
unsigned long dev;
switch (X86_AX) {
case PCI_BIOS_PRESENT:
#ifdef DEBUG_X86EMU_PCI
DPRINT("PCI_BIOS_PRESENT\r\n");
#endif
X86_AH = 0x00; /* no config space/special cycle support */
X86_AL = 0x01; /* config mechanism 1 */
X86_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24;
X86_EBX = 0x0210; /* Version 2.10 */
X86_ECX = 0xFF00; /* FixME: Max bus number */
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case FIND_PCI_DEVICE:
/* FixME: support SI != 0 */
// vendor, device
#ifdef DEBUG_X86EMU_PCI
DPRINTVALHEX("FIND_PCI_DEVICE vendor ", X86_DX);
DPRINTVALHEX(" device ", X86_CX);
#endif
dev = pci_find_device((unsigned long) X86_DX, ((unsigned long)X86_CX), 0);
case PCI_BIOS_PRESENT:
dbg("%s: PCI_BIOS_PRESENT\r\n", __FUNCTION__);
X86_AH = 0x00; /* no config space/special cycle support */
X86_AL = 0x01; /* config mechanism 1 */
X86_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24;
X86_EBX = 0x0210; /* Version 2.10 */
X86_ECX = 0xFF00; /* FixME: Max bus number */
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
if (dev != 0) {
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... OK\r\n");
#endif
X86_BH = PCI_BUS_FROM_HANDLE(dev);
//X86_BH = (char)(dev >> 16) / PCI_MAX_FUNCTION); // dev->bus->secondary;
X86_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev);
//X86_BL = (char)dev; // dev->path.u.pci.devfn;
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
} else {
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... error\r\n");
#endif
X86_AH = DEVICE_NOT_FOUND;
X86_EFLAGS |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case FIND_PCI_CLASS_CODE:
/* FixME: support SI != 0 */
#ifdef DEBUG_X86EMU_PCI
DPRINTVALHEX("FIND_PCI_CLASS_CODE ", X86_ECX);
#endif
dev = pci_find_classcode(X86_ECX, 0);
if (dev != 0) {
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... OK\r\n");
#endif
X86_BH = PCI_BUS_FROM_HANDLE(dev);
X86_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
} else {
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... error\r\n");
#endif
X86_AH = DEVICE_NOT_FOUND;
X86_EFLAGS |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case READ_CONFIG_BYTE:
// bus, devfn
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL("READ_CONFIG_BYTE bus ", X86_BH);
DPRINTVAL(" devfn ", X86_BL);
DPRINTVALHEX(" reg ", X86_DI);
#endif
X86_CL = pci_read_config_byte(dev, X86_DI);
#ifdef DEBUG_X86EMU_PCI
DPRINTVALHEX(" value ", X86_CL);
DPRINT("\r\n");
#endif
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case READ_CONFIG_WORD:
// bus, devfn
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL("READ_CONFIG_WORD bus ", X86_BH);
DPRINTVAL(" devfn ", X86_BL);
DPRINTVALHEX(" reg ", X86_DI);
#endif
if(X86_DI == PCIBAR1)
X86_CX = offset_port + 1;
else
X86_CX = pci_read_config_word(dev, X86_DI);
#ifdef DEBUG_X86EMU_PCI
DPRINTVALHEX(" value ", X86_CX);
DPRINT("\r\n");
#endif
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case READ_CONFIG_DWORD:
// bus, devfn
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL("READ_CONFIG_DWORD bus ", X86_BH);
DPRINTVAL(" devfn ", X86_BL);
DPRINTVALHEX(" reg ", X86_DI);
#endif
if(X86_DI == PCIBAR1)
X86_CX = (unsigned long)offset_port+1;
else
X86_ECX = pci_read_config_longword(dev, X86_DI);
#ifdef DEBUG_X86EMU_PCI
DPRINTVALHEX(" value ", X86_ECX);
DPRINT("\r\n");
#endif
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case WRITE_CONFIG_BYTE:
// bus, devfn
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL("READ_CONFIG_BYTE bus ", X86_BH);
DPRINTVAL(" devfn ", X86_BL);
DPRINTVALHEX(" reg ", X86_DI);
DPRINTVALHEX(" value ", X86_CL);
#endif
if ((ret = pci_write_config_byte(dev, X86_DI, X86_CL)) == 0)
{
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... OK\r\n");
#endif
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
} else {
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL(" ... error ", ret);
DPRINT("\r\n");
#endif
X86_AH = DEVICE_NOT_FOUND;
X86_EFLAGS |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case WRITE_CONFIG_WORD:
// bus, devfn
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL("WRITE_CONFIG_WORD bus ", X86_BH);
DPRINTVAL(" devfn ", X86_BL);
DPRINTVALHEX(" reg ", X86_DI);
DPRINTVALHEX(" value ", X86_CX);
#endif
if(X86_DI == PCIBAR1) {
offset_port = X86_CX;
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... OK\r\n");
#endif
case FIND_PCI_DEVICE:
/* FixME: support SI != 0 */
// vendor, device
dbg("%s: FIND_PCI_DEVICE vendor = %04x, device = %04x\r\n", __FUNCTION__, X86_DX, X86_CX);
dev = pci_find_device((unsigned long) X86_DX, ((unsigned long) X86_CX), 0);
if (dev != 0)
{
dbg("%s: ... OK\r\n", __FUNCTION__);
X86_BH = PCI_BUS_FROM_HANDLE(dev);
//X86_BH = (char)(dev >> 16) / PCI_MAX_FUNCTION); // dev->bus->secondary;
X86_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev);
//X86_BL = (char)dev; // dev->path.u.pci.devfn;
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
} else {
dbg("%s: ... error\r\n", __FUNCTION__);
X86_AH = DEVICE_NOT_FOUND;
X86_EFLAGS |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case FIND_PCI_CLASS_CODE:
/* FixME: support SI != 0 */
dbg("%s: FIND_PCI_CLASS_CODE %x\r\n", __FUNCTION__, X86_ECX);
dev = pci_find_classcode(X86_ECX, 0);
if (dev != 0) {
dbg("%s: ... OK\r\n", __FUNCTION__);
X86_BH = PCI_BUS_FROM_HANDLE(dev);
X86_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
}
else
{
dbg("%s: ... error\r\n", __FUNCTION__);
X86_AH = DEVICE_NOT_FOUND;
X86_EFLAGS |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case READ_CONFIG_BYTE:
// bus, devfn
dbg("%s: READ_CONFIG_BYTE bus = %x, devfn = %x, reg = %x\r\n", __FUNCTION__, X86_BH, X86_BL, X86_DI);
X86_CL = pci_read_config_byte(dev, X86_DI);
dbg("%s: value = %x\r\n", __FUNCTION__, X86_CL);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
}
if ((ret = pci_write_config_word(dev, X86_DI, X86_CX)) == 0)
{
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... OK\r\n");
#endif
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
} else {
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL(" ... error ", ret);
DPRINT("\r\n");
#endif
X86_AH = DEVICE_NOT_FOUND;
X86_EFLAGS |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case WRITE_CONFIG_DWORD:
// bus, devfn
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL("WRITE_CONFIG_DWORD bus ", X86_BH);
DPRINTVAL(" devfn ", X86_BL);
DPRINTVALHEX(" reg ", X86_DI);
DPRINTVALHEX(" value ", X86_ECX);
#endif
if(X86_DI == PCIBAR1) {
offset_port = (unsigned short)X86_ECX & 0xFFFC;
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... OK\r\n");
#endif
case READ_CONFIG_WORD:
// bus, devfn
dbg("%s: READ_CONFIG_WORD bus = %x, devfn = %x, reg = %x\r\n", __FUNCTION__, X86_BH, X86_BL, X86_DI);
if(X86_DI == PCIBAR1)
X86_CX = offset_port + 1;
else
X86_CX = pci_read_config_word(dev, X86_DI);
dbg("%s: value = %x\r\n", __FUNCTION__, X86_CX);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
}
if ((ret = pci_write_config_longword(dev, X86_DI, X86_ECX)) == 0)
{
#ifdef DEBUG_X86EMU_PCI
DPRINT(" ... OK\r\n");
#endif
case READ_CONFIG_DWORD:
// bus, devfn
dbg("%s: READ_CONFIG_DWORD bus = %x, devfn = %x, reg = %x\r\n", __FUNCTION__, X86_BH, X86_BL, X86_DI);
if (X86_DI == PCIBAR1)
X86_CX = (unsigned long) offset_port + 1;
else
X86_ECX = pci_read_config_longword(dev, X86_DI);
dbg("%s: value = %x\r\n", __FUNCTION__, X86_ECX);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
}
else
{
#ifdef DEBUG_X86EMU_PCI
DPRINTVAL(" ... error ", ret);
DPRINT("\r\n");
#endif
X86_AH = DEVICE_NOT_FOUND;
X86_EFLAGS |= FB_CF; /* set carry flag */
ret = 0;
}
break;
default:
#ifdef DEBUG_X86EMU_PCI
DPRINT("PCI_BIOS FUNC_NOT_SUPPORTED\r\n");
#endif
X86_AH = FUNC_NOT_SUPPORTED;
X86_EFLAGS |= FB_CF;
break;
break;
case WRITE_CONFIG_BYTE:
// bus, devfn
dbg("%s: READ_CONFIG_BYTE bus = %x, devfn = %x, reg = %x\r\n", __FUNCTION__, X86_BH, X86_BL, X86_CL);
pci_write_config_byte(dev, X86_DI, X86_CL);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case WRITE_CONFIG_WORD:
// bus, devfn
dbg("%s: WRITE_CONFIG_WORD bus = %x, devfn = %x, reg = %x, value = %x\r\n", X86_BH, X86_BL, X86_DI, X86_CX);
if (X86_DI == PCIBAR1)
{
offset_port = X86_CX;
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
}
pci_write_config_word(dev, X86_DI, X86_CX);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case WRITE_CONFIG_DWORD:
// bus, devfn
dbg("%s: WRITE_CONFIG_DWORD bus = %x, devfn = %x, value = %x\r\n", __FUNCTION__,
X86_BH, X86_BL, X86_DI, X86_ECX);
if (X86_DI == PCIBAR1)
{
offset_port = (unsigned short) X86_ECX & 0xFFFC;
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
}
pci_write_config_longword(dev, X86_DI, X86_ECX);
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
default:
dbg("%s: PCI_BIOS FUNC_NOT_SUPPORTED\r\n", __FUNCTION__);
X86_AH = FUNC_NOT_SUPPORTED;
X86_EFLAGS |= FB_CF;
break;
}
return ret;