diff --git a/FPGA_quartus_ori/DSP/DSP.vhd.bak b/FPGA_quartus_ori/DSP/DSP.vhd.bak deleted file mode 100644 index 2d4811a..0000000 --- a/FPGA_quartus_ori/DSP/DSP.vhd.bak +++ /dev/null @@ -1,79 +0,0 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:57 2009 - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - - --- Entity Declaration - -ENTITY DSP IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT - ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nRSTO : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nSRCS : OUT STD_LOGIC; - nSRBLE : OUT STD_LOGIC; - nSRBHE : OUT STD_LOGIC; - nSRWE : OUT STD_LOGIC; - nSROE : OUT STD_LOGIC; - DSP_INT : OUT STD_LOGIC; - DSP_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - IO : INOUT STD_LOGIC_VECTOR(17 downto 0); - SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) - ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END DSP; - - --- Architecture Body - -ARCHITECTURE DSP_architecture OF DSP IS - - -BEGIN - nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; - nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; - nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; - nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; - nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; - DSP_INT <= '0'; - DSP_TA <= '0'; - IO(17 downto 0) <= FB_ADR(18 downto 1); - SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - - -END DSP_architecture; diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak deleted file mode 100644 index a339eda..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak +++ /dev/null @@ -1,971 +0,0 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:20 2009 - -library work; -use work.FalconIO_SDCard_IDE_CF_pkg.all; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - --- Entity Declaration - - --- Entity Declaration - -ENTITY FalconIO_SDCard_IDE_CF IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT - ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - CLK2M : IN STD_LOGIC; - CLK500k : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - LP_BUSY : IN STD_LOGIC; - nACSI_DRQ : IN STD_LOGIC; - nACSI_INT : IN STD_LOGIC; - nSCSI_DRQ : IN STD_LOGIC; - nSCSI_MSG : IN STD_LOGIC; - MIDI_IN : IN STD_LOGIC; - RxD : IN STD_LOGIC; - CTS : IN STD_LOGIC; - RI : IN STD_LOGIC; - DCD : IN STD_LOGIC; - AMKB_RX : IN STD_LOGIC; - PIC_AMKB_RX : IN STD_LOGIC; - IDE_RDY : IN STD_LOGIC; - IDE_INT : IN STD_LOGIC; - WP_CS_CARD : IN STD_LOGIC; - nINDEX : IN STD_LOGIC; - TRACK00 : IN STD_LOGIC; - nRD_DATA : IN STD_LOGIC; - nDCHG : IN STD_LOGIC; - SD_DATA0 : IN STD_LOGIC; - SD_DATA1 : IN STD_LOGIC; - SD_DATA2 : IN STD_LOGIC; - SD_CARD_DEDECT : IN STD_LOGIC; - SD_WP : IN STD_LOGIC; - nDACK0 : IN STD_LOGIC; - nFB_WR : INOUT STD_LOGIC; - WP_CF_CARD : IN STD_LOGIC; - nWP : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - HD_DD : IN STD_LOGIC; - nSCSI_C_D : IN STD_LOGIC; - nSCSI_I_O : IN STD_LOGIC; - CLK2M4576 : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - VSYNC : IN STD_LOGIC; - HSYNC : IN STD_LOGIC; - DSP_INT : IN STD_LOGIC; - nBLANK : IN STD_LOGIC; - FDC_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); - nIDE_CS1 : OUT STD_LOGIC; - nIDE_CS0 : OUT STD_LOGIC; - LP_STR : OUT STD_LOGIC; - LP_DIR : OUT STD_LOGIC; - nACSI_ACK : OUT STD_LOGIC; - nACSI_RESET : OUT STD_LOGIC; - nACSI_CS : OUT STD_LOGIC; - ACSI_DIR : OUT STD_LOGIC; - ACSI_A1 : OUT STD_LOGIC; - nSCSI_ACK : OUT STD_LOGIC; - nSCSI_ATN : OUT STD_LOGIC; - SCSI_DIR : OUT STD_LOGIC; - SD_CLK : OUT STD_LOGIC; - YM_QA : OUT STD_LOGIC; - YM_QC : OUT STD_LOGIC; - YM_QB : OUT STD_LOGIC; - nSDSEL : OUT STD_LOGIC; - STEP : OUT STD_LOGIC; - MOT_ON : OUT STD_LOGIC; - nRP_LDS : OUT STD_LOGIC; - nRP_UDS : OUT STD_LOGIC; - nROM4 : OUT STD_LOGIC; - nROM3 : OUT STD_LOGIC; - nCF_CS1 : OUT STD_LOGIC; - nCF_CS0 : OUT STD_LOGIC; - nIDE_RD : INOUT STD_LOGIC; - nIDE_WR : INOUT STD_LOGIC; - AMKB_TX : OUT STD_LOGIC; - IDE_RES : OUT STD_LOGIC; - DTR : OUT STD_LOGIC; - RTS : OUT STD_LOGIC; - TxD : OUT STD_LOGIC; - MIDI_OLR : OUT STD_LOGIC; - MIDI_TLR : OUT STD_LOGIC; - nDREQ0 : OUT STD_LOGIC; - DSA_D : OUT STD_LOGIC; - nMFP_INT : OUT STD_LOGIC; - FALCON_IO_TA : OUT STD_LOGIC; - STEP_DIR : OUT STD_LOGIC; - WR_DATA : OUT STD_LOGIC; - WR_GATE : OUT STD_LOGIC; - DMA_DRQ : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_PAR : INOUT STD_LOGIC; - nSCSI_SEL : INOUT STD_LOGIC; - nSCSI_BUSY : INOUT STD_LOGIC; - nSCSI_RST : INOUT STD_LOGIC; - SD_CD_DATA3 : INOUT STD_LOGIC; - SD_CDM_D1 : INOUT STD_LOGIC - ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END FalconIO_SDCard_IDE_CF; - - --- Architecture Body - -ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS --- system -signal SYS_CLK : STD_LOGIC; -signal RESETn : STD_LOGIC; -signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS -signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS -signal BYT : STD_LOGIC; -- WENN BYT -> 1 -signal LONG : STD_LOGIC; -- WENN -> 1 --- KEYBOARD MIDI -signal ACIA_CS_I : STD_LOGIC; -signal IRQ_KEYBDn : STD_LOGIC; -signal IRQ_MIDIn : STD_LOGIC; -signal KEYB_RxD : STD_LOGIC; -signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); -signal MIDI_OUT : STD_LOGIC; -signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); -signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); --- MFP -signal MFP_CS : STD_LOGIC; -signal MFP_INTACK : STD_LOGIC; -signal LDS : STD_LOGIC; -signal DTACK_OUT_MFPn : STD_LOGIC; -signal IRQ_ACIAn : STD_LOGIC; -signal DINTn : STD_LOGIC; -signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); -signal TDO : STD_LOGIC; --- SOUND -signal SNDCS : STD_LOGIC; -signal SNDCS_I : STD_LOGIC; -signal SNDIR_I : STD_LOGIC; -signal LP_DIR_X : STD_LOGIC; -signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); -signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); --- DIV -signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE -signal ROM_CS : STD_LOGIC; --- DMA UND FLOPPY -signal DMA_DATEN_CS : STD_LOGIC; -signal DMA_MODUS_CS : STD_LOGIC; -signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); -signal WDC_BSL_CS : STD_LOGIC; -signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); -signal HD_DD_OUT : STD_LOGIC; -signal FDCS_In : STD_LOGIC; -signal CA0 : STD_LOGIC; -signal CA1 : STD_LOGIC; -signal CA2 : STD_LOGIC; -signal FDINT : STD_LOGIC; -signal FDRQ : STD_LOGIC; -signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_TOP_CS : STD_LOGIC; -signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_HIGH_CS : STD_LOGIC; -signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_MID_CS : STD_LOGIC; -signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_LOW_CS : STD_LOGIC; -signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_DIRM_CS : STD_LOGIC; -signal DMA_ADR_CS : STD_LOGIC; -signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); -signal DMA_DIR_OLD : STD_LOGIC; -signal DMA_BYT_CNT_CS : STD_LOGIC; -signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); -signal CLR_FIFO : STD_LOGIC; -signal DMA_DRQ_I : STD_LOGIC; -signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); -signal DMA_DRQQ : STD_LOGIC; -signal DMA_DRQ_Q : STD_LOGIC; -signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); -signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal RDF_RDE : STD_LOGIC; -signal RDF_WRE : STD_LOGIC; -signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal WRF_RDE : STD_LOGIC; -signal WRF_WRE : STD_LOGIC; -signal nFDC_WR : STD_LOGIC; -type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); -signal FCF_STATE : FCF_STATES; -signal NEXT_FCF_STATE : FCF_STATES; -signal DMA_REQ : STD_LOGIC; -signal FDC_CS : STD_LOGIC; -signal FCF_CS : STD_LOGIC; -signal FCF_APH : STD_LOGIC; -signal DMA_AZ_CS : STD_LOGIC; -signal DMA_ACTIV : STD_LOGIC; -signal DMA_ACTIV_NEW : STD_LOGIC; -signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); --- SCSI -signal SCSI_CS : STD_LOGIC; -signal SCSI_CSn : STD_LOGIC; -signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal nSCSI_DACK : STD_LOGIC; -signal SCSI_DRQ : STD_LOGIC; -signal SCSI_INT : STD_LOGIC; -signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); -signal DB_EN : STD_LOGIC; -signal DBP_OUTn : STD_LOGIC; -signal DBP_EN : STD_LOGIC; -signal RST_OUTn : STD_LOGIC; -signal RST_EN : STD_LOGIC; -signal BSY_OUTn : STD_LOGIC; -signal BSY_EN : STD_LOGIC; -signal SEL_OUTn : STD_LOGIC; -signal SEL_EN : STD_LOGIC; --- IDE -signal nnIDE_RES : STD_LOGIC; -signal IDE_CF_CS : STD_LOGIC; -signal IDE_CF_TA : STD_LOGIC; -signal NEXT_nIDE_RD : STD_LOGIC; -signal NEXT_nIDE_WR : STD_LOGIC; -type CMD_STATES is( IDLE, T1, T6, T7); -signal CMD_STATE : CMD_STATES; -signal NEXT_CMD_STATE : CMD_STATES; - - -BEGIN -LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; -BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; -FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; -FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; - -FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' - or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; -SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE - '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE - '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; -nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; -nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; -nDREQ0 <= '0'; ----------------------------------------------------------------------------- --- SD ----------------------------------------------------------------------------- -SD_CLK <= 'Z'; -SD_CD_DATA3 <= 'Z'; -SD_CDM_D1 <= 'Z'; ----------------------------------------------------------------------------- --- IDE ----------------------------------------------------------------------------- -CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) - begin - if nRSTO = '0' then - CMD_STATE <= IDLE; - elsif rising_edge(MAIN_CLK) then - CMD_STATE <= NEXT_CMD_STATE; -- go to next - nIDE_RD <= NEXT_nIDE_RD; -- go to next - nIDE_WR <= NEXT_nIDE_WR; -- go to next - else - CMD_STATE <= CMD_STATE; -- halten - nIDE_RD <= nIDE_RD; -- halten - nIDE_WR <= nIDE_WR; -- halten - end if; - end process CMD_REG; - - CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) - begin - case CMD_STATE is - when IDLE => - IDE_CF_TA <= '0'; - if IDE_CF_CS = '1' then - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T1; - else - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= IDLE; - end if; - when T1 => - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T6; - when T6 => - IF IDE_RDY = '1' then - IDE_CF_TA <= '1'; - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= T7; - else - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T6; - end if; - when T7 => - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= IDLE; - end case; - end process CMD_DECODER; - -IDE_RES <= not nnIDE_RES and nRSTO; -IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 -nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F -nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F -nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F -nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F ------------------------------------------------------------------------------------------------------------------------------------------ --- ACSI, SCSI UND FLOPPY WD1772 -------------------------------------------------------------------------------------------------------------------------------------------- --- daten read fifo - RDF: dcfifo0 - port map( - aclr => CLR_FIFO, - data => RDF_DIN, - rdclk => MAIN_CLK, - rdreq => RDF_RDE, - wrclk => FDC_CLK, - wrreq => RDF_WRE, - q => RDF_DOUT, - wrusedw => RDF_AZ - ); -FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY -FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY -RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE -FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; --- daten write fifo - WRF: dcfifo1 - port map( - aclr => CLR_FIFO, - data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), - rdclk => FDC_CLK, - rdreq => WRF_RDE, - wrclk => MAIN_CLK, - wrreq => WRF_WRE, - q => WRF_DOUT, - rdusedw => WRF_AZ - ); -CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB -DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG -FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- - process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) - begin - if nRSTO = '0' THEN - WRF_WRE <= '0'; - elsif rising_edge(MAIN_CLK) then - IF FCF_APH = '1' and nFB_WR = '0' then - WRF_WRE <= '1'; - else - WRF_WRE <= '0'; - end if; - else - WRF_WRE <= WRF_WRE; - end if; - END PROCESS; - -FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) - begin - if nRSTO = '0' then - FCF_STATE <= FCF_IDLE; - DMA_ACTIV <= '0'; - elsif rising_edge(FDC_CLK) then - FCF_STATE <= NEXT_FCF_STATE; -- go to next - DMA_ACTIV <= DMA_ACTIV_NEW; - else - FCF_STATE <= FCF_STATE; -- halten - DMA_ACTIV <= DMA_ACTIV; - end if; - end process FCF_REG; - -FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) - begin - if nRSTO = '0' then - FDC_OUT <= x"00"; - elsif rising_edge(FDC_CLK) and FDCS_In = '0' then - FDC_OUT <= CD_OUT_FDC; -- set - else - FDC_OUT <= FDC_OUT; -- halten - end if; - end process FDC_REG; - -DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; -FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; -SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; - - FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) - begin - case FCF_STATE is - when FCF_IDLE => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - WRF_RDE <= '0'; - nSCSI_DACK <= '1'; - if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then - DMA_ACTIV_NEW <= DMA_REQ; - NEXT_FCF_STATE <= FCF_T0; - else - DMA_ACTIV_NEW <= '0'; - NEXT_FCF_STATE <= FCF_IDLE; - end if; - when FCF_T0 => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - nSCSI_DACK <= '1'; - DMA_ACTIV_NEW <= DMA_REQ; - WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO - if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? - NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start - else - NEXT_FCF_STATE <= FCF_T1; - end if; - when FCF_T1 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T2; - when FCF_T2 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T3; - when FCF_T3 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T6; - when FCF_T6 => - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO - NEXT_FCF_STATE <= FCF_T7; - when FCF_T7 => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - WRF_RDE <= '0'; - nSCSI_DACK <= '1'; - DMA_ACTIV_NEW <= '0'; - if FDC_CS = '1' and DMA_REQ = '0' then - NEXT_FCF_STATE <= FCF_T7; - else - NEXT_FCF_STATE <= FCF_IDLE; - end if; - end case; - end process FCF_DECODER; - - I_FDC: WF1772IP_TOP_SOC - port map( - CLK => FDC_CLK, - RESETn => nRSTO, - CSn => FDCS_In, - RWn => nFDC_WR, - A1 => CA2, - A0 => CA1, - DATA_IN => CD_IN_FDC, - DATA_OUT => CD_OUT_FDC, --- DATA_EN => CD_EN_FDC, - RDn => nRD_DATA, - TR00n => TRACK00, - IPn => nINDEX, - WPRTn => nWP, - DDEn => '0', -- Fixed to MFM. - HDTYPE => HD_DD_OUT, - MO => MOT_ON, - WG => WR_GATE, - WD => WR_DATA, - STEP => STEP, - DIRC => STEP_DIR, - DRQ => DMA_DRQ_I, - INTRQ => FDINT - ); -DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 -DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 -WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 -HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); -nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; -CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); -CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); -CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); -FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else - SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else - DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ---- WDC BSL REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN - WDC_BSL <= "00"; - elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then - IF FB_B0 = '1' THEN - WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); - else - WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); - end if; - end if; - END PROCESS; ---- DMA MODUS REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN - DMA_MODUS <= x"0000"; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then - IF FB_B0 = '1' THEN - DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); - else - DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); - end if; - IF FB_B1 = '1' THEN - DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); - else - DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); - end if; - else - DMA_MODUS <= DMA_MODUS; - end if; - END PROCESS; --- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) - begin - if nRSTO = '0' or CLR_FIFO = '1' THEN - DMA_BYT_CNT <= x"00000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then - DMA_BYT_CNT(31 downto 17) <= "000000000000000"; - DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); - DMA_BYT_CNT(8 downto 0) <= "000000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then - DMA_BYT_CNT <= FB_AD; - else - DMA_BYT_CNT <= DMA_BYT_CNT; - end if; - END PROCESS; --------------------------------------------------------------------- -FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -DMA_STATUS(0) <= '1'; -- DMA OK -DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS -DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; -DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else - '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; -DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ - process(FDC_CLK, nRSTO, DMA_DRQ_REG) - begin - if nRSTO = '0' THEN - DMA_DRQ_REG <= "00"; - elsif rising_edge(FDC_CLK) then - DMA_DRQ_REG(0) <= DMA_DRQQ; - DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; - else - DMA_DRQ_REG <= DMA_DRQ_REG; - end if; - END PROCESS; --- DMA ADRESSE ------------------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN - DMA_TOP <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then - DMA_TOP <= FB_AD(31 downto 24); - else - DMA_TOP <= DMA_TOP; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN - DMA_HIGH <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then - DMA_HIGH <= FB_AD(23 downto 16); - else - DMA_HIGH <= DMA_HIGH; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) - begin - DMA_MID <= DMA_MID; - if nRSTO = '0' THEN - DMA_MID <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_MID_CS = '1' then - DMA_MID <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_MID <= FB_AD(15 downto 8); - end if; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) - begin - DMA_LOW <= DMA_LOW; - if nRSTO = '0' THEN - DMA_LOW <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_LOW_CS = '1'then - DMA_LOW <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_LOW <= FB_AD(7 downto 0); - end if; - end if; - END PROCESS; --------------------------------------------------------------------------------------------- -DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 -DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 -DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 -DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 -FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- DIRECTZUGRIFF -DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD -DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG -DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG -FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; --- DMA RW TOGGLE ------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) - begin - if nRSTO = '0' THEN - DMA_DIR_OLD <= '0'; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then - DMA_DIR_OLD <= DMA_MODUS(8); - else - DMA_DIR_OLD <= DMA_DIR_OLD; - end if; - END PROCESS; -CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; --- SCSI ---------------------------------------------------------------------------------- - I_SCSI: WF5380_TOP_SOC - port map( - CLK => FDC_CLK, - RESETn => nRSTO, - ADR => CA2 & CA1 & CA0, - DATA_IN => CD_IN_FDC, - DATA_OUT => SCSI_DOUT, - --DATA_EN : out bit; - -- Bus and DMA controls: - CSn => '1', --SCSI_CSn, ABGESCHALTET - RDn => (not nFDC_WR) or (not SCSI_CS), - WRn => nFDC_WR or (not SCSI_CS), - EOPn => '1', - DACKn => nSCSI_DACK, - DRQ => SCSI_DRQ, - INT => SCSI_INT, --- READY => - -- SCSI bus: - DB_INn => SCSI_D, - DB_OUTn => DB_OUTn, - DB_EN => DB_EN, - DBP_INn => SCSI_PAR, - DBP_OUTn => DBP_OUTn, - DBP_EN => DBP_EN, -- wenn 1 dann output - RST_INn => nSCSI_RST, - RST_OUTn => RST_OUTn, - RST_EN => RST_EN, - BSY_INn => nSCSI_BUSY, - BSY_OUTn => BSY_OUTn, - BSY_EN => BSY_EN, - SEL_INn => nSCSI_SEL, - SEL_OUTn => SEL_OUTn, - SEL_EN => SEL_EN, - ACK_INn => '1', - ACK_OUTn => nSCSI_ACK, --- ACK_EN => ACK_EN, - ATN_INn => '1', - ATN_OUTn => nSCSI_ATN, --- ATN_EN => ATN_EN, - REQ_INn => nSCSI_DRQ, --- REQ_OUTn => REQ_OUTn, --- REQ_EN => REQ_EN, - IOn_IN => nSCSI_I_O, --- IOn_OUT => IOn_OUT, --- IO_EN => IO_EN, - CDn_IN => nSCSI_C_D, --- CDn_OUT => CDn_OUT, --- CD_EN => CD_EN, - MSG_INn => nSCSI_MSG --- MSG_OUTn => MSG_OUTn, --- MSG_EN => MSG_EN - ); --- SCSI ACSI --------------------------------------------------------------- -SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; -SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET -SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; -nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; -nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; -nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; -ACSI_DIR <= '0'; -ACSI_D <= "ZZZZZZZZ"; -nACSI_CS <= '1'; -ACSI_A1 <= CA1; -nACSI_RESET <= nRSTO; -nACSI_ACK <= '1'; ----------------------------------------------------------------------------- --- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns ----------------------------------------------------------------------------- -ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 -nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; -nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; ----------------------------------------------------------------------------- --- ACIA KEYBOARD ----------------------------------------------------------------------------- - I_ACIA_KEYBOARD: WF6850IP_TOP_SOC - port map( - CLK => MAIN_CLK, - RESETn => nRSTO, - - CS2n => FB_ADR(2), - CS1 => '1', - CS0 => ACIA_CS_I, - E => ACIA_CS_I, - RWn => nFB_WR, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_I, --- DATA_EN => DATA_EN_ACIA_I, - - TXCLK => CLK500k, - RXCLK => CLK500k, - RXDATA => KEYB_RxD, - - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_KEYBDn, - TXDATA => AMKB_TX - --RTSn => -- Not used. - ); -ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 -KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL -FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; --- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ - process(CLK2M, AMKB_RX, AMKB_REG) - begin - if rising_edge(CLK2M) then - IF AMKB_RX = '0' THEN - IF AMKB_REG < 16 THEN - AMKB_REG <= "00000"; - ELSE - AMKB_REG <= AMKB_REG - 1; - END IF; - ELSE - IF AMKB_REG > 15 THEN - AMKB_REG <= "11111"; - ELSE - AMKB_REG <= AMKB_REG + 1; - END IF; - END IF; - ELSE - AMKB_REG <= AMKB_REG; - end if; - END PROCESS; ----------------------------------------------------------------------------- --- ACIA MIDI ----------------------------------------------------------------------------- - I_ACIA_MIDI: WF6850IP_TOP_SOC - port map( - CLK => MAIN_CLK, - RESETn => nRSTO, - - CS2n => '0', - CS1 => FB_ADR(2), - CS0 => ACIA_CS_I, - E => ACIA_CS_I, - RWn => nFB_WR, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_II, --- DATA_EN => DATA_EN_ACIA_II, - - TXCLK => CLK500k, - RXCLK => CLK500k, - RXDATA => MIDI_IN, - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_MIDIn, - TXDATA => MIDI_OUT - --RTSn => -- Not used. - ); -MIDI_TLR <= MIDI_OUT; -MIDI_OLR <= MIDI_OUT; -FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ----------------------------------------------------------------------------- --- MFP ----------------------------------------------------------------------------- - I_MFP: WF68901IP_TOP_SOC - port map( - -- System control: - CLK => MAIN_CLK, - RESETn => nRSTO, - -- Asynchronous bus control: - DSn => not LDS, - CSn => not MFP_CS, - RWn => nFB_WR, - DTACKn => DTACK_OUT_MFPn, - -- Data and Adresses: - RS => FB_ADR(5 downto 1), - DATA_IN => FB_AD(23 downto 16), - DATA_OUT => DATA_OUT_MFP, --- DATA_EN => DATA_EN_MFP, - GPIP_IN(7) => not DMA_DRQ_Q, - GPIP_IN(6) => not RI, - GPIP_IN(5) => DINTn, - GPIP_IN(4) => IRQ_ACIAn, - GPIP_IN(3) => DSP_INT, - GPIP_IN(2) => not CTS, - GPIP_IN(1) => not DCD, - GPIP_IN(0) => LP_BUSY, - -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. - -- GPIP_EN =>, -- Not used; all GPIPs are direction input. - -- Interrupt control: - IACKn => not MFP_INTACK, - IEIn => '0', - -- IEOn =>, -- Not used. - IRQn => nMFP_INT, - -- Timers and timer control: - XTAL1 => CLK2M4576, - TAI => '0', - TBI => nBLANK, - -- TAO =>, - -- TBO =>, - -- TCO =>, - TDO => TDO, - -- Serial I/O control: - RC => TDO, - TC => TDO, - SI => RxD, - SO => TxD - -- SO_EN => MFP_SO_EN - -- DMA control: - -- RRn =>, - -- TRn => - ); - -MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 -MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 -LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; -FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; -DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else - '0' when FDINT = '1' else - '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1'; --- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ - process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) - begin - if nRSTO = '0' THEN - IRQ_ACIAn <= '1'; - elsif rising_edge(MAIN_CLK) then - IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; - else - IRQ_ACIAn <= IRQ_ACIAn; - end if; - END PROCESS; ----------------------------------------------------------------------------- --- Sound ----------------------------------------------------------------------------- - I_SOUND: WF2149IP_TOP_SOC - port map( - SYS_CLK => MAIN_CLK, - RESETn => nRSTO, - - WAV_CLK => CLK2M, - SELn => '1', - - BDIR => SNDIR_I, - BC2 => '1', - BC1 => SNDCS_I, - - A9n => '0', - A8 => '1', - DA_IN => FB_AD(31 downto 24), - DA_OUT => DA_OUT_X, - - IO_A_IN => x"00", -- All port pins are dedicated outputs. - IO_A_OUT(7) => nnIDE_RES, - IO_A_OUT(6) => LP_DIR_X, - IO_A_OUT(5) => LP_STR, - IO_A_OUT(4) => DTR, - IO_A_OUT(3) => RTS, --- IO_A_OUT(2) => FDD_D1SEL, - IO_A_OUT(1) => DSA_D, - IO_A_OUT(0) => nSDSEL, - -- IO_A_EN =>, -- Not required. - IO_B_IN => LP_D, - IO_B_OUT => LP_D_X, - -- IO_B_EN => IO_B_EN, - - OUT_A => YM_QA, - OUT_B => YM_QB, - OUT_C => YM_QC - ); - -SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 -SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; -SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; -FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; -LP_DIR <= LP_DIR_X; - -END FalconIO_SDCard_IDE_CF_architecture; diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak deleted file mode 100644 index 4f42cf2..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak +++ /dev/null @@ -1,406 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Atari Coldfire IP Core ---- ----- ---- ----- This file is part of the Atari Coldfire project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- ---- ----- ---- ----- ---- ----- ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2009 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- 1.0 Initial Release, 20090925. --- - -library ieee; -use ieee.std_logic_1164.all; - -package FalconIO_SDCard_IDE_CF_PKG is - component WF25915IP_TOP_V1_SOC -- GLUE. - port ( - -- Clock system: - GL_CLK : in std_logic; -- Originally 8MHz. - GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK. - - -- Core address select: - GL_ROMSEL_FC_E0n : in std_logic; - EN_RAM_14MB : in std_logic; - -- Adress decoder outputs: - GL_ROM_6n : out std_logic; -- STE. - GL_ROM_5n : out std_logic; -- STE. - GL_ROM_4n : out std_logic; -- ST. - GL_ROM_3n : out std_logic; -- ST. - GL_ROM_2n : out std_logic; - GL_ROM_1n : out std_logic; - GL_ROM_0n : out std_logic; - - GL_ACIACS : out std_logic; - GL_MFPCSn : out std_logic; - GL_SNDCSn : out std_logic; - GL_FCSn : out std_logic; - - GL_STE_SNDCS : out std_logic; -- STE: Sound chip select. - GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control. - - GL_STE_RTCCSn : out std_logic; --STE only. - GL_STE_RTC_WRn : out std_logic; --STE only. - GL_STE_RTC_RDn : out std_logic; --STE only. - - -- 6800 peripheral control, - GL_VPAn : out std_logic; - GL_VMAn : in std_logic; - - GL_DMA_SYNC : in std_logic; - GL_DEVn : out std_logic; - GL_RAMn : out std_logic; - GL_DMAn : out std_logic; - - -- Interrupt system: - -- Comment out GL_AVECn for CPUs which do not provide the VMAn signal. - GL_AVECn : out std_logic; - GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only. - GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only. - GL_MFPINTn : in std_logic; -- ST. - GL_STE_EINT3n : in std_logic; --STE only. - GL_STE_EINT5n : in std_logic; --STE only. - GL_STE_EINT7n : in std_logic; --STE only. - GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only. - GL_IACKn : out std_logic; -- ST. - GL_STE_IPL2n : out std_logic; --STE only. - GL_STE_IPL1n : out std_logic; --STE only. - GL_STE_IPL0n : out std_logic; --STE only. - - -- Video timing: - GL_BLANKn : out std_logic; - GL_DE : out std_logic; - GL_MULTISYNC : in std_logic_vector(3 downto 2); - GL_VIDEO_HIMODE : out std_logic; - GL_HSYNC_INn : in std_logic; - GL_HSYNC_OUTn : out std_logic; - GL_VSYNC_INn : in std_logic; - GL_VSYNC_OUTn : out std_logic; - GL_SYNC_OUT_EN : out std_logic; - - -- Bus arstd_logicration control: - GL_RDY_INn : in std_logic; - GL_RDY_OUTn : out std_logic; - GL_BRn : out std_logic; - GL_BGIn : in std_logic; - GL_BGOn : out std_logic; - GL_BGACK_INn : in std_logic; - GL_BGACK_OUTn : out std_logic; - - -- Adress and data bus: - GL_ADDRESS : in std_logic_vector(23 downto 1); - -- ST: put the data bus to 1 downto 0. - -- STE: put the data out bus to 15 downto 0. - GL_DATA_IN : in std_logic_vector(7 downto 0); - GL_DATA_OUT : out std_logic_vector(15 downto 0); - GL_DATA_EN : out std_logic; - - -- Asynchronous bus control: - GL_RWn_IN : in std_logic; - GL_RWn_OUT : out std_logic; - GL_AS_INn : in std_logic; - GL_AS_OUTn : out std_logic; - GL_UDS_INn : in std_logic; - GL_UDS_OUTn : out std_logic; - GL_LDS_INn : in std_logic; - GL_LDS_OUTn : out std_logic; - GL_DTACK_INn : in std_logic; - GL_DTACK_OUTn : out std_logic; - GL_CTRL_EN : out std_logic; - - -- System control: - GL_RESETn : in std_logic; - GL_BERRn : out std_logic; - - -- Processor function codes: - GL_FC : in std_logic_vector(2 downto 0); - - -- STE enhancements: - GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD). - GL_STE_FCCLK : out std_logic; -- Floppy controller clock select. - GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte. - GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte. - GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte. - GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable. - GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte. - GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X. - GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y. - GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X. - GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y. - GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset. - GL_STE_PENn : in std_logic; -- Input of the light pen. - GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip. - GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor. - ); - end component WF25915IP_TOP_V1_SOC; - - component WF5380_TOP_SOC - port ( - CLK : in std_logic; - RESETn : in std_logic; - ADR : in std_logic_vector(2 downto 0); - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - CSn : in std_logic; - RDn : in std_logic; - WRn : in std_logic; - EOPn : in std_logic; - DACKn : in std_logic; - DRQ : out std_logic; - INT : out std_logic; - READY : out std_logic; - DB_INn : in std_logic_vector(7 downto 0); - DB_OUTn : out std_logic_vector(7 downto 0); - DB_EN : out std_logic; - DBP_INn : in std_logic; - DBP_OUTn : out std_logic; - DBP_EN : out std_logic; - RST_INn : in std_logic; - RST_OUTn : out std_logic; - RST_EN : out std_logic; - BSY_INn : in std_logic; - BSY_OUTn : out std_logic; - BSY_EN : out std_logic; - SEL_INn : in std_logic; - SEL_OUTn : out std_logic; - SEL_EN : out std_logic; - ACK_INn : in std_logic; - ACK_OUTn : out std_logic; - ACK_EN : out std_logic; - ATN_INn : in std_logic; - ATN_OUTn : out std_logic; - ATN_EN : out std_logic; - REQ_INn : in std_logic; - REQ_OUTn : out std_logic; - REQ_EN : out std_logic; - IOn_IN : in std_logic; - IOn_OUT : out std_logic; - IO_EN : out std_logic; - CDn_IN : in std_logic; - CDn_OUT : out std_logic; - CD_EN : out std_logic; - MSG_INn : in std_logic; - MSG_OUTn : out std_logic; - MSG_EN : out std_logic - ); - end component WF5380_TOP_SOC; - - component WF1772IP_TOP_SOC -- FDC. - port ( - CLK : in std_logic; -- 16MHz clock! - RESETn : in std_logic; - CSn : in std_logic; - RWn : in std_logic; - A1, A0 : in std_logic; - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - RDn : in std_logic; - TR00n : in std_logic; - IPn : in std_logic; - WPRTn : in std_logic; - DDEn : in std_logic; - HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks. - MO : out std_logic; - WG : out std_logic; - WD : out std_logic; - STEP : out std_logic; - DIRC : out std_logic; - DRQ : out std_logic; - INTRQ : out std_logic - ); - end component WF1772IP_TOP_SOC; - - component WF68901IP_TOP_SOC -- MFP. - port ( -- System control: - CLK : in std_logic; - RESETn : in std_logic; - - -- Asynchronous bus control: - DSn : in std_logic; - CSn : in std_logic; - RWn : in std_logic; - DTACKn : out std_logic; - - -- Data and Adresses: - RS : in std_logic_vector(5 downto 1); - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - GPIP_IN : in std_logic_vector(7 downto 0); - GPIP_OUT : out std_logic_vector(7 downto 0); - GPIP_EN : out std_logic_vector(7 downto 0); - - -- Interrupt control: - IACKn : in std_logic; - IEIn : in std_logic; - IEOn : out std_logic; - IRQn : out std_logic; - - -- Timers and timer control: - XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. - TAI : in std_logic; - TBI : in std_logic; - TAO : out std_logic; - TBO : out std_logic; - TCO : out std_logic; - TDO : out std_logic; - - -- Serial I/O control: - RC : in std_logic; - TC : in std_logic; - SI : in std_logic; - SO : out std_logic; - SO_EN : out std_logic; - - -- DMA control: - RRn : out std_logic; - TRn : out std_logic - ); - end component WF68901IP_TOP_SOC; - - component WF2149IP_TOP_SOC -- Sound. - port( - - SYS_CLK : in std_logic; -- Read the inforation in the header! - RESETn : in std_logic; - - WAV_CLK : in std_logic; -- Read the inforation in the header! - SELn : in std_logic; - - BDIR : in std_logic; - BC2, BC1 : in std_logic; - - A9n, A8 : in std_logic; - DA_IN : in std_logic_vector(7 downto 0); - DA_OUT : out std_logic_vector(7 downto 0); - DA_EN : out std_logic; - - IO_A_IN : in std_logic_vector(7 downto 0); - IO_A_OUT : out std_logic_vector(7 downto 0); - IO_A_EN : out std_logic; - IO_B_IN : in std_logic_vector(7 downto 0); - IO_B_OUT : out std_logic_vector(7 downto 0); - IO_B_EN : out std_logic; - - OUT_A : out std_logic; -- Analog (PWM) outputs. - OUT_B : out std_logic; - OUT_C : out std_logic - ); - end component WF2149IP_TOP_SOC; - - component WF6850IP_TOP_SOC -- ACIA. - port ( - CLK : in std_logic; - RESETn : in std_logic; - - CS2n, CS1, CS0 : in std_logic; - E : in std_logic; - RWn : in std_logic; - RS : in std_logic; - - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - - TXCLK : in std_logic; - RXCLK : in std_logic; - RXDATA : in std_logic; - CTSn : in std_logic; - DCDn : in std_logic; - - IRQn : out std_logic; - TXDATA : out std_logic; - RTSn : out std_logic - ); - end component WF6850IP_TOP_SOC; - - component WF_SD_CARD - port ( - RESETn : in std_logic; - CLK : in std_logic; - ACSI_A1 : in std_logic; - ACSI_CSn : in std_logic; - ACSI_ACKn : in std_logic; - ACSI_INTn : out std_logic; - ACSI_DRQn : out std_logic; - ACSI_D_IN : in std_logic_vector(7 downto 0); - ACSI_D_OUT : out std_logic_vector(7 downto 0); - ACSI_D_EN : out std_logic; - MC_DO : in std_logic; - MC_PIO_DMAn : in std_logic; - MC_RWn : in std_logic; - MC_CLR_CMD : in std_logic; - MC_DONE : out std_logic; - MC_GOT_CMD : out std_logic; - MC_D_IN : in std_logic_vector(7 downto 0); - MC_D_OUT : out std_logic_vector(7 downto 0); - MC_D_EN : out std_logic - ); - end component WF_SD_CARD; - - component dcfifo0 - PORT ( - aclr : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); - wrusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) - ); - end component dcfifo0; - - component dcfifo1 - PORT ( - aclr : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) - ); - end component; - - -end FalconIO_SDCard_IDE_CF_PKG; diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak deleted file mode 100644 index 0200dea..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak +++ /dev/null @@ -1,239 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- ATARI IP Core peripheral Add-On ---- ----- ---- ----- This file is part of the FPGA-ATARI project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- This hardware provides an interface to connect to a SD-Card. ---- ----- ---- ----- This interface is based on the project 'SatanDisk' of ---- ----- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- ----- the original code, written in VERILOG. It is provided for ---- ----- the use in a system on programmable chips (SOPC). ---- ----- ---- ----- Timing: Use a clock frequency of 16MHz for this component. ---- ----- Use the same clock frequency for the connected AVR ---- ----- microcontroller. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2007 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- ----- This hardware works with the original ATARI ---- ----- hard dik driver. ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K7A 2007/01/05 WF --- Initial Release. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF_SD_CARD is - port ( - -- System: - RESETn : in bit; - CLK : in bit; -- 16MHz, see above. - - -- ACSI section: - ACSI_A1 : in bit; - ACSI_CSn : in bit; - ACSI_ACKn : in bit; - ACSI_INTn : out bit; - ACSI_DRQn : out bit; - ACSI_D_IN : in std_logic_vector(7 downto 0); - ACSI_D_OUT : out std_logic_vector(7 downto 0); - ACSI_D_EN : out bit; - - -- Microcontroller interface: - MC_DO : in bit; - MC_PIO_DMAn : in bit; - MC_RWn : in bit; - MC_CLR_CMD : in bit; - MC_DONE : out bit; - MC_GOT_CMD : out bit; - MC_D_IN : in std_logic_vector(7 downto 0); - MC_D_OUT : out std_logic_vector(7 downto 0); - MC_D_EN : out bit - ); -end WF_SD_CARD; - -architecture BEHAVIOR of WF_SD_CARD is -signal DATA_REG : std_logic_vector(7 downto 0); -signal D0_REG : bit; -signal INT_REG : bit; -signal DRQ_REG : bit; -signal DONE_REG : bit; -signal GOT_CMD_REG : bit; -signal HOLD : bit; -signal PREV_CSn : bit; -signal PREV_ACKn : bit; -begin - MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0'); - MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0'; - ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0'); --- ???: ---ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0'; -ACSI_D_EN <= '0'; - ACSI_INTn <= INT_REG; - ACSI_DRQn <= DRQ_REG; - MC_DONE <= DONE_REG; - MC_GOT_CMD <= GOT_CMD_REG; - - P_DATA: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= (others => '0'); - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then - DATA_REG <= MC_D_IN; -- Read from AVR to ACSI. - end if; - -- - if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then - DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. - elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then - DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. - end if; - end if; - end process P_DATA; - - P_SYNC: process - begin - wait until CLK = '1' and CLK' event; - PREV_CSn <= ACSI_CSn; - PREV_ACKn <= ACSI_ACKn; - end process P_SYNC; - - P_INT_DRQ: process(RESETn, CLK) - begin - if RESETn = '0' then - INT_REG <= '1'; -- No interrupt. - DRQ_REG <= '1'; -- No data request. - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. - INT_REG <= '0'; -- Release an interrupt. - DRQ_REG <= '1'; - elsif D0_REG = '0' and MC_DO = '1' then - INT_REG <= '1'; - DRQ_REG <= '0'; -- Release a data request. - end if; - -- - if MC_CLR_CMD = '1' then -- Clear done. - INT_REG <= '1'; -- Restore INT_REG. - DRQ_REG <= '1'; -- Restore DRQ_REG. - end if; - -- - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - if ACSI_CSn = '0' then - INT_REG <= '1'; - end if; - -- - if ACSI_ACKn = '0' then - DRQ_REG <= '1'; - end if; - end if; - end if; - end process P_INT_DRQ; - - P_HOLD: process(RESETn, CLK) - begin - if RESETn = '0' then - HOLD <= '0'; - elsif CLK = '1' and CLK' event then - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - HOLD <= '1'; - elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. - HOLD <= '0'; - elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. - HOLD <= '0'; - elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. - HOLD <= '1'; - elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. - HOLD <= '1'; - elsif MC_CLR_CMD = '1' then -- Clear done. - HOLD <= '0'; - end if; - end if; - end process P_HOLD; - - P_DONE: process(RESETn, CLK) - begin - if RESETn = '0' then - DONE_REG <= '0'; - elsif CLK = '1' and CLK' event then - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - DONE_REG <= '1'; - elsif MC_CLR_CMD = '1' then -- Clear done. - DONE_REG <= '0'; - elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. - DONE_REG <= '0'; - elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. - DONE_REG <= '0'; - end if; - end if; - end process P_DONE; - - P_DO_REG: process(RESETn, CLK) - begin - if RESETn = '0' then - D0_REG <= '0'; - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. - D0_REG <= MC_DO; - elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. - D0_REG <= MC_DO; - end if; - end if; - end process P_DO_REG; - - P_GOT_CMD: process(RESETn, CLK) - begin - if RESETn = '0' then - GOT_CMD_REG <= '0'; - elsif CLK = '1' and CLK' event then --- ?? ACSI_CSn doppelt! ---if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then - GOT_CMD_REG <= '1'; -- If command was received. - elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then - GOT_CMD_REG <= '1'; -- If command was received. - elsif MC_CLR_CMD = '1' then -- Clear done. - GOT_CMD_REG <= '0'; - end if; - end if; - end process P_GOT_CMD; -end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak deleted file mode 100644 index a0ea9e4..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak +++ /dev/null @@ -1,244 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- Control unit and status logic. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- Revision 2K9A 2009/06/20 WF --- CTRL_REG has now synchronous reset to meet preset requirements. --- Process P_DCD has now synchronous reset to meet preset requirements. --- IRQ_In has now synchronous reset to meet preset requirement. --- Revision 2K9B 2009/12/24 WF --- Fixed the interrupt logic. --- Introduced a minor RTSn correction. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_CTRL_STATUS is - port ( - CLK : in bit; - RESETn : in bit; - - CS : in bit_vector(2 downto 0); -- Active if "011". - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - - -- Status register stuff: - RDRF : in bit; -- Receive data register full. - TDRE : in bit; -- Transmit data register empty. - DCDn : in bit; -- Data carrier detect. - CTSn : in bit; -- Clear to send. - FE : in bit; -- Framing error. - OVR : in bit; -- Overrun error. - PE : in bit; -- Parity error. - - -- Control register stuff: - MCLR : buffer bit; -- Master clear (high active). - RTSn : out bit; -- Request to send. - CDS : out bit_vector(1 downto 0); -- Clock control. - WS : out bit_vector(2 downto 0); -- Word select. - TC : out bit_vector(1 downto 0); -- Transmit control. - IRQn : out bit -- Interrupt request. - ); -end entity WF6850IP_CTRL_STATUS; - -architecture BEHAVIOR of WF6850IP_CTRL_STATUS is -signal CTRL_REG : bit_vector(7 downto 0); -signal STATUS_REG : bit_vector(7 downto 0); -signal RIE : bit; -signal IRQ_I : bit; -signal CTS_In : bit; -signal DCD_In : bit; -signal DCD_FLAGn : bit; -begin - P_SAMPLE: process - begin - wait until CLK = '0' and CLK' event; - CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. - DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. - end process P_SAMPLE; - - STATUS_REG(7) <= IRQ_I; - STATUS_REG(6) <= PE; - STATUS_REG(5) <= OVR; - STATUS_REG(4) <= FE; - STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin. - STATUS_REG(2) <= DCD_FLAGn; - STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. - STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. - - DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; - - MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; - RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; - - CDS <= CTRL_REG(1 downto 0); - WS <= CTRL_REG(4 downto 2); - TC <= CTRL_REG(6 downto 5); - RIE <= CTRL_REG(7); - - P_IRQ: process - variable DCD_OVR_LOCK : boolean; - variable DCD_LOCK : boolean; - variable DCD_TRANS : boolean; - begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - DCD_OVR_LOCK := false; - IRQn <= '1'; - IRQ_I <= '0'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then - DCD_OVR_LOCK := false; -- Enable reset by reading the status. - end if; - --- Clear interrupts when disabled. -if CTRL_REG(7) = '0' then - IRQn <= '1'; - IRQ_I <= '0'; -elsif CTRL_REG(6 downto 5) /= "01" then - IRQn <= '1'; - IRQ_I <= '0'; -end if; - - -- Transmitter interrupt: - if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then - IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by writing to the transmit data register. - end if; - - -- Receiver interrupts: - if RDRF = '1' and RIE = '1' and DCD_In = '0' then - IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by reading the receive data register. - end if; - - if OVR = '1' and RIE = '1' then - IRQn <= '0'; - IRQ_I <= '1'; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. - end if; - - if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then - IRQn <= '0'; - IRQ_I <= '1'; - -- DCD_TRANS is used to detect a low to high transition of DCDn. - DCD_TRANS := true; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. - elsif DCD_In = '0' then - DCD_TRANS := false; - end if; - - -- The reset of the IRQ status flag: - -- Clear by writing to the transmit data register. - -- Clear by reading the receive data register. - if CS = "011" and RS = '1' and E = '1' then - IRQ_I <= '0'; - end if; - end process P_IRQ; - - CONTROL: process - begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - CTRL_REG <= "01000000"; - elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then - CTRL_REG <= DATA_IN; - end if; - end process CONTROL; - - P_DCD: process - -- This process is some kind of tricky. Refer to the MC6850 data - -- sheet for more information. - variable READ_LOCK : boolean; - variable DCD_RELEASE : boolean; - begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - DCD_FLAGn <= '0'; -- This interrupt source must initialise low. - READ_LOCK := true; - DCD_RELEASE := false; - elsif MCLR = '1' then - DCD_FLAGn <= DCD_In; - READ_LOCK := true; - elsif DCD_In = '1' then - DCD_FLAGn <= '1'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then - READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then - -- Clear if receiver status register read access. - -- After data register has ben read and READ_LOCK again. - DCD_RELEASE := true; - READ_LOCK := true; - DCD_FLAGn <= DCD_In; - elsif DCD_In = '0' and DCD_RELEASE = true then - DCD_FLAGn <= '0'; - DCD_RELEASE := false; - end if; - end process P_DCD; -end architecture BEHAVIOR; - diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak deleted file mode 100644 index e8c82b2..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak +++ /dev/null @@ -1,415 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- 6850's receiver unit. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_RECEIVE is - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - - RXCLK : in bit; - RXDATA : in bit; - - RDRF : buffer bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end entity WF6850IP_RECEIVE; - -architecture BEHAVIOR of WF6850IP_RECEIVE is -type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); -signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; -signal RXDATA_I : bit; -signal RXDATA_S : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal CLK_STRB : bit; -signal BITCNT : std_logic_vector(2 downto 0); -begin - P_SAMPLE: process - -- This filter provides a synchronisation to the system - -- clock, even for random baud rates of the received data - -- stream. - variable FLT_TMP : integer range 0 to 2; - begin - wait until CLK = '1' and CLK' event; - -- - RXDATA_I <= RXDATA; - -- - if RXDATA_I = '1' and FLT_TMP < 2 then - FLT_TMP := FLT_TMP + 1; - elsif RXDATA_I = '1' then - RXDATA_S <= '1'; - elsif RXDATA_I = '0' and FLT_TMP > 0 then - FLT_TMP := FLT_TMP - 1; - elsif RXDATA_I = '0' then - RXDATA_S <= '0'; - end if; - end process P_SAMPLE; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - wait until CLK = '1' and CLK' event; - if CDS = "00" then -- Divider off. - if RXCLK = '1' and STRB_LOCK = false then - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif RXCLK = '0' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif RCV_STATE = IDLE then - -- Preset the CLKDIV with the start delays. - if CDS = "01" then - CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. - elsif CDS = "10" then - CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. - end if; - CLK_STRB <= '0'; - else - if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - -- - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif RXCLK = '0' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end process CLKDIV; - - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - DATA_REG <= x"00"; - elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= '0' & SHIFT_REG(7 downto 1); - elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= SHIFT_REG; - end if; - end if; - end process DATAREG; ---DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); ---DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; -DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0'); -DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0'; - - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - SHIFT_REG <= x"00"; - elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then - SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; - - P_BITCNT: process - begin - wait until CLK = '1' and CLK' event; - if RCV_STATE = SAMPLE and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif RCV_STATE /= SAMPLE then - BITCNT <= (others => '0'); - end if; - end process P_BITCNT; - - FRAME_ERR: process(RESETn, CLK) - -- This module detects a framing error - -- during stop bit 1 and stop bit 2. - variable FE_I: bit; - begin - if RESETn = '0' then - FE_I := '0'; - FE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - FE_I := '0'; - FE <= '0'; - elsif CLK_STRB = '1' then - if RCV_STATE = STOP1 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP2 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then - FE_I := '0'; -- Error resets when correct data appears. - end if; - end if; - if RCV_STATE = SYNC then - FE <= FE_I; -- Update the FE every SYNC time. - end if; - end if; - end process FRAME_ERR; - - OVERRUN: process(RESETn, CLK) - variable OVR_I : bit; - variable FIRST_READ : boolean; - begin - if RESETn = '0' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK_STRB = '1' and RCV_STATE = STOP1 then - -- Overrun appears if RDRF is '1' in this state. - OVR_I := RDRF; - end if; - if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then - -- If an overrun was detected, the concerning flag is - -- set when the valid data word in the receiver data - -- register is read. Thereafter the RDRF flag is reset - -- and the overrun disappears (OVR_I goes low) after - -- a second read (in time) of the receiver data register. - if FIRST_READ = false then - OVR <= '1'; - FIRST_READ := true; - else - OVR <= '0'; - FIRST_READ := false; - end if; - end if; - end if; - end process OVERRUN; - - PARITY_TEST: process(RESETn, CLK) - variable PAR_TMP : bit; - variable PE_I : bit; - begin - if RESETn = '0' then - PE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - PE <= '0'; - elsif CLK_STRB = '1' then -- Sample parity on clock strobe. - PE_I := '0'; -- Initialise. - if RCV_STATE = PARITY then - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PE_I := PAR_TMP xor RXDATA_S; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PE_I := not PAR_TMP xor RXDATA_S; - else -- No parity for WS = "100" and WS = "101". - PE_I := '0'; - end if; - end if; - end if; - -- Transmit the parity flag together with the data - -- In other words: no parity to the status register - -- when RDRF inhibits the data transfer to the - -- receiver data register. - if RCV_STATE = SYNC and RDRF = '0' then - PE <= PE_I; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - PE <= '0'; -- Clear when reading the data register. - end if; - end if; - end process PARITY_TEST; - - P_RDRF: process(RESETn, CLK) - -- Receive data register full flag. - begin - if RESETn = '0' then - RDRF <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RDRF <= '0'; - elsif RCV_STATE = SYNC then - RDRF <= '1'; -- Data register is full until now! - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - RDRF <= '0'; -- After reading the data register ... - end if; - end if; - end process P_RDRF; - - RCV_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then - RCV_STATE <= IDLE; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RCV_STATE <= IDLE; - else - RCV_STATE <= RCV_NEXT_STATE; - end if; - end if; - end process RCV_STATEREG; - - RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) - begin - case RCV_STATE is - when IDLE => - if RXDATA_S = '0' and CDS = "00" then - RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. - elsif RXDATA_S = '0' and CDS = "01" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. - elsif RXDATA_S = '0' and CDS = "10" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. - else - RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) - end if; - when WAIT_START => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. - else - RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. - end if; - else - RCV_NEXT_STATE <= WAIT_START; -- Stay. - end if; - when SAMPLE => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. - elsif WS = "100" or WS = "101" then - RCV_NEXT_STATE <= STOP1; -- No parity check enabled. - else - RCV_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else - RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. - end if; - when PARITY => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= STOP1; - else - RCV_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SYNC; -- Framing error detected. - elsif WS = "000" or WS = "001" or WS = "100" then - RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. - else - RCV_NEXT_STATE <= SYNC; -- One stop bit selected. - end if; - else - RCV_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= SYNC; - else - RCV_NEXT_STATE <= STOP2; - end if; - when SYNC => - RCV_NEXT_STATE <= IDLE; - end case; - end process RCV_STATEDEC; -end architecture BEHAVIOR; - diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak deleted file mode 100644 index 6f80a67..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak +++ /dev/null @@ -1,252 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- This is the top level file. ---- ----- Top level file for use in systems on programmable chips. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Top level file provided for SOC (systems on programmable chips). --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_TOP_SOC is - port ( - CLK : in bit; - RESETn : in bit; - - CS2n, CS1, CS0 : in bit; - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out bit; - - TXCLK : in bit; - RXCLK : in bit; - RXDATA : in bit; - CTSn : in bit; - DCDn : in bit; - - IRQn : out bit; - TXDATA : out bit; - RTSn : out bit - ); -end entity WF6850IP_TOP_SOC; - -architecture STRUCTURE of WF6850IP_TOP_SOC is -component WF6850IP_CTRL_STATUS - port ( - CLK : in bit; - RESETn : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - RDRF : in bit; - TDRE : in bit; - DCDn : in bit; - CTSn : in bit; - FE : in bit; - OVR : in bit; - PE : in bit; - MCLR : out bit; - RTSn : out bit; - CDS : out bit_vector(1 downto 0); - WS : out bit_vector(2 downto 0); - TC : out bit_vector(1 downto 0); - IRQn : out bit - ); -end component; - -component WF6850IP_RECEIVE - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - RXCLK : in bit; - RXDATA : in bit; - RDRF : out bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end component; - -component WF6850IP_TRANSMIT - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - CTSn : in bit; - TC : in bit_vector(1 downto 0); - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - TXCLK : in bit; - TDRE : out bit; - TXDATA : out bit - ); -end component; -signal DATA_IN_I : bit_vector(7 downto 0); -signal DATA_RX : bit_vector(7 downto 0); -signal DATA_RX_EN : bit; -signal DATA_CTRL : bit_vector(7 downto 0); -signal DATA_CTRL_EN : bit; -signal RDRF_I : bit; -signal TDRE_I : bit; -signal FE_I : bit; -signal OVR_I : bit; -signal PE_I : bit; -signal MCLR_I : bit; -signal CDS_I : bit_vector(1 downto 0); -signal WS_I : bit_vector(2 downto 0); -signal TC_I : bit_vector(1 downto 0); -signal IRQ_In : bit; -begin - DATA_IN_I <= To_BitVector(DATA_IN); - DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; - DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else - To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0'); - - IRQn <= '0' when IRQ_In = '0' else '1'; - - I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS - port map( - CLK => CLK, - RESETn => RESETn, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_IN => DATA_IN_I, - DATA_OUT => DATA_CTRL, - DATA_EN => DATA_CTRL_EN, - RDRF => RDRF_I, - TDRE => TDRE_I, - DCDn => DCDn, - CTSn => CTSn, - FE => FE_I, - OVR => OVR_I, - PE => PE_I, - MCLR => MCLR_I, - RTSn => RTSn, - CDS => CDS_I, - WS => WS_I, - TC => TC_I, - IRQn => IRQ_In - ); - - I_UART_RECEIVE: WF6850IP_RECEIVE - port map ( - CLK => CLK, - RESETn => RESETn, - MCLR => MCLR_I, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_OUT => DATA_RX, - DATA_EN => DATA_RX_EN, - WS => WS_I, - CDS => CDS_I, - RXCLK => RXCLK, - RXDATA => RXDATA, - RDRF => RDRF_I, - OVR => OVR_I, - PE => PE_I, - FE => FE_I - ); - - I_UART_TRANSMIT: WF6850IP_TRANSMIT - port map ( - CLK => CLK, - RESETn => RESETn, - MCLR => MCLR_I, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_IN => DATA_IN_I, - CTSn => CTSn, - TC => TC_I, - WS => WS_I, - CDS => CDS_I, - TDRE => TDRE_I, - TXCLK => TXCLK, - TXDATA => TXDATA - ); -end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak deleted file mode 100644 index bcff094..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak +++ /dev/null @@ -1,339 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- 6850's transmitter unit. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- Revision 2K8B 2008/11/01 WF --- Fixed the T_DRE process concerning the TDRE <= '1' setting. --- Thanks to Lyndon Amsdon finding the bug. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_TRANSMIT is - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in bit_vector(7 downto 0); - - CTSn : in bit; - - TC : in bit_vector(1 downto 0); - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - - TXCLK : in bit; - - TDRE : buffer bit; - TXDATA : out bit - ); -end entity WF6850IP_TRANSMIT; - -architecture BEHAVIOR of WF6850IP_TRANSMIT is -type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); -signal TR_STATE, TR_NEXT_STATE : TR_STATES; -signal CLK_STRB : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal BITCNT : std_logic_vector(2 downto 0); -signal PARITY_I : bit; -begin - -- The default condition in this statement is to ensure - -- to cover all possibilities for example if there is a - -- one hot decoding of the state machine with wrong states - -- (e.g. not one of the given here). - TXDATA <= '1' when TR_STATE = IDLE else - '1' when TR_STATE = LOAD_SHFT else - '0' when TR_STATE = START else - SHIFT_REG(0) when TR_STATE = SHIFTOUT else - PARITY_I when TR_STATE = PARITY else - '1' when TR_STATE = STOP1 else - '1' when TR_STATE = STOP2 else '1'; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - wait until CLK = '1' and CLK' event; - if CDS = "00" then -- divider off - if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif TXCLK = '1' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif TR_STATE = IDLE then - -- preset the CLKDIV with the start delays - if CDS = "01" then - CLK_DIVCNT := "0010000"; -- div by 16 mode - elsif CDS = "10" then - CLK_DIVCNT := "1000000"; -- div by 64 mode - end if; - CLK_STRB <= '0'; - else - -- Works on negative TXCLK edge: - if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif TXCLK = '1' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end process CLKDIV; - - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - DATA_REG <= x"00"; - elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then - DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode. - elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then - DATA_REG <= DATA_IN; -- 8 bit data mode. - end if; - end if; - end process DATAREG; - - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - SHIFT_REG <= x"00"; - elsif TR_STATE = LOAD_SHFT and TDRE = '0' then - -- If during LOAD_SHIFT the transmitter data register - -- is empty (TDRE = '1') the shift register will not - -- be loaded. When additionally TC = "11", the break - -- character (zero data and no stop bits) is sent. - SHIFT_REG <= DATA_REG; - elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then - SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; - - P_BITCNT: process - -- Counter for the data bits transmitted. - begin - wait until CLK = '1' and CLK' event; - if TR_STATE = SHIFTOUT and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif TR_STATE /= SHIFTOUT then - BITCNT <= "000"; - end if; - end process P_BITCNT; - - P_TDRE: process(RESETn, CLK) - -- Transmit data register empty flag. - variable LOCK : boolean; - begin - if RESETn = '0' then - TDRE <= '1'; - LOCK := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - TDRE <= '1'; - elsif TR_NEXT_STATE = START and TR_STATE /= START then - -- Data has been loaded to shift register, thus data register is free again. - -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once - -- entering the state now. - TDRE <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then - LOCK := true; - elsif E = '0' and LOCK = true and CS /= "011" then - -- This construction clears TDRE after the falling edge of E - -- and after the transmit data register has been written to. - TDRE <= '0'; - LOCK := false; - end if; - end if; - end process P_TDRE; - - PARITY_GEN: process - variable PAR_TMP : bit; - begin - wait until CLK = '1' and CLK' event; - if TR_STATE = START then -- Calculate the parity during the start phase. - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PARITY_I <= PAR_TMP; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PARITY_I <= not PAR_TMP; - else -- No parity for WS = "100" and WS = "101". - PARITY_I <= '0'; - end if; - end if; - end process PARITY_GEN; - - TR_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then - TR_STATE <= IDLE; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - TR_STATE <= IDLE; - else - TR_STATE <= TR_NEXT_STATE; - end if; - end if; - end process TR_STATEREG; - - TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) - begin - case TR_STATE is - when IDLE => - if TDRE = '1' and TC = "11" then - TR_NEXT_STATE <= LOAD_SHFT; - elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty. - TR_NEXT_STATE <= LOAD_SHFT; - else - TR_NEXT_STATE <= IDLE; - end if; - when LOAD_SHFT => - TR_NEXT_STATE <= START; - when START => - if CLK_STRB = '1' then - TR_NEXT_STATE <= SHIFTOUT; - else - TR_NEXT_STATE <= START; - end if; - when SHIFTOUT => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then - TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then - TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. - elsif WS = "100" or WS = "101" then - if TDRE = '1' and TC = "11" then - -- Break condition, do not send a stop bit. - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP1; -- No parity check enabled. - end if; - else - TR_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else - TR_NEXT_STATE <= SHIFTOUT; - end if; - when PARITY => - if CLK_STRB = '1' then - if TDRE = '1' and TC = "11" then - -- Break condition, do not send a stop bit. - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP1; -- No parity check enabled. - end if; - else - TR_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then - TR_NEXT_STATE <= STOP2; -- Two stop bits selected. - elsif CLK_STRB = '1' then - TR_NEXT_STATE <= IDLE; -- One stop bits selected. - else - TR_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP2; - end if; - end case; - end process TR_STATEDEC; -end architecture BEHAVIOR; - diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak deleted file mode 100644 index c3ca670..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak +++ /dev/null @@ -1,202 +0,0 @@ --- megafunction wizard: %LPM_FIFO+% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: dcfifo_mixed_widths - --- ============================================================ --- File Name: dcfifo0.vhd --- Megafunction Name(s): --- dcfifo_mixed_widths --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 222 10/21/2009 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY dcfifo0 IS - PORT - ( - aclr : IN STD_LOGIC := '0'; - data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); -END dcfifo0; - - -ARCHITECTURE SYN OF dcfifo0 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); - - - - COMPONENT dcfifo_mixed_widths - GENERIC ( - intended_device_family : STRING; - lpm_numwords : NATURAL; - lpm_showahead : STRING; - lpm_type : STRING; - lpm_width : NATURAL; - lpm_widthu : NATURAL; - lpm_widthu_r : NATURAL; - lpm_width_r : NATURAL; - overflow_checking : STRING; - rdsync_delaypipe : NATURAL; - underflow_checking : STRING; - use_eab : STRING; - write_aclr_synch : STRING; - wrsync_delaypipe : NATURAL - ); - PORT ( - wrclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - aclr : IN STD_LOGIC ; - rdclk : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - wrreq : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - wrusedw <= sub_wire0(4 DOWNTO 0); - q <= sub_wire1(15 DOWNTO 0); - - dcfifo_mixed_widths_component : dcfifo_mixed_widths - GENERIC MAP ( - intended_device_family => "Cyclone III", - lpm_numwords => 32, - lpm_showahead => "OFF", - lpm_type => "dcfifo", - lpm_width => 8, - lpm_widthu => 5, - lpm_widthu_r => 4, - lpm_width_r => 16, - overflow_checking => "ON", - rdsync_delaypipe => 5, - underflow_checking => "ON", - use_eab => "ON", - write_aclr_synch => "OFF", - wrsync_delaypipe => 5 - ) - PORT MAP ( - wrclk => wrclk, - rdreq => rdreq, - aclr => aclr, - rdclk => rdclk, - wrreq => wrreq, - data => data, - wrusedw => sub_wire0, - q => sub_wire1 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" --- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" --- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" --- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" --- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "4" --- Retrieval info: PRIVATE: Depth NUMERIC "32" --- Retrieval info: PRIVATE: Empty NUMERIC "1" --- Retrieval info: PRIVATE: Full NUMERIC "1" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" --- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" --- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" --- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: Optimize NUMERIC "1" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: UsedW NUMERIC "1" --- Retrieval info: PRIVATE: Width NUMERIC "8" --- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" --- Retrieval info: PRIVATE: diff_widths NUMERIC "1" --- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" --- Retrieval info: PRIVATE: output_width NUMERIC "16" --- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: rsFull NUMERIC "0" --- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" --- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" --- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" --- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: wsFull NUMERIC "0" --- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32" --- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" --- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" --- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5" --- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4" --- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16" --- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: USE_EAB STRING "ON" --- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" --- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr --- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] --- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] --- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk --- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq --- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk --- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq --- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0] --- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 --- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 --- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 --- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 --- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 --- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 --- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0 --- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak deleted file mode 100644 index e7c6ae6..0000000 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak +++ /dev/null @@ -1,202 +0,0 @@ --- megafunction wizard: %LPM_FIFO+% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: dcfifo_mixed_widths - --- ============================================================ --- File Name: dcfifo1.vhd --- Megafunction Name(s): --- dcfifo_mixed_widths --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 222 10/21/2009 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY dcfifo1 IS - PORT - ( - aclr : IN STD_LOGIC := '0'; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) - ); -END dcfifo1; - - -ARCHITECTURE SYN OF dcfifo1 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); - - - - COMPONENT dcfifo_mixed_widths - GENERIC ( - intended_device_family : STRING; - lpm_numwords : NATURAL; - lpm_showahead : STRING; - lpm_type : STRING; - lpm_width : NATURAL; - lpm_widthu : NATURAL; - lpm_widthu_r : NATURAL; - lpm_width_r : NATURAL; - overflow_checking : STRING; - rdsync_delaypipe : NATURAL; - underflow_checking : STRING; - use_eab : STRING; - write_aclr_synch : STRING; - wrsync_delaypipe : NATURAL - ); - PORT ( - wrclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - aclr : IN STD_LOGIC ; - rdclk : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - wrreq : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - wrusedw <= sub_wire0(3 DOWNTO 0); - q <= sub_wire1(7 DOWNTO 0); - - dcfifo_mixed_widths_component : dcfifo_mixed_widths - GENERIC MAP ( - intended_device_family => "Cyclone III", - lpm_numwords => 16, - lpm_showahead => "OFF", - lpm_type => "dcfifo", - lpm_width => 16, - lpm_widthu => 4, - lpm_widthu_r => 5, - lpm_width_r => 8, - overflow_checking => "ON", - rdsync_delaypipe => 5, - underflow_checking => "ON", - use_eab => "ON", - write_aclr_synch => "OFF", - wrsync_delaypipe => 5 - ) - PORT MAP ( - wrclk => wrclk, - rdreq => rdreq, - aclr => aclr, - rdclk => rdclk, - wrreq => wrreq, - data => data, - wrusedw => sub_wire0, - q => sub_wire1 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" --- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" --- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" --- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" --- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "4" --- Retrieval info: PRIVATE: Depth NUMERIC "16" --- Retrieval info: PRIVATE: Empty NUMERIC "1" --- Retrieval info: PRIVATE: Full NUMERIC "1" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" --- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" --- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" --- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: Optimize NUMERIC "1" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: UsedW NUMERIC "1" --- Retrieval info: PRIVATE: Width NUMERIC "16" --- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" --- Retrieval info: PRIVATE: diff_widths NUMERIC "1" --- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" --- Retrieval info: PRIVATE: output_width NUMERIC "8" --- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: rsFull NUMERIC "0" --- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" --- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" --- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" --- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: wsFull NUMERIC "0" --- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" --- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" --- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" --- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" --- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5" --- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" --- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: USE_EAB STRING "ON" --- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" --- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr --- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] --- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk --- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq --- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk --- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq --- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0] --- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 --- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 --- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 --- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 --- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 --- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 --- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus_ori/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_quartus_ori/Interrupt_Handler/interrupt_handler.tdf.bak deleted file mode 100644 index e3e49eb..0000000 --- a/FPGA_quartus_ori/Interrupt_Handler/interrupt_handler.tdf.bak +++ /dev/null @@ -1,478 +0,0 @@ -TITLE "INTERRUPT HANDLER UND C1287"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_LONG.inc"; -INCLUDE "lpm_bustri_BYT.inc"; - - --- Parameters Statement (optional) - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - - --- Subdesign Section - -SUBDESIGN interrupt_handler -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - MAIN_CLK : INPUT; - nFB_WR : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - FB_ADR[31..0] : INPUT; - PIC_INT : INPUT; - E0_INT : INPUT; - DVI_INT : INPUT; - nPCI_INTA : INPUT; - nPCI_INTB : INPUT; - nPCI_INTC : INPUT; - nPCI_INTD : INPUT; - nMFP_INT : INPUT; - nFB_OE : INPUT; - DSP_INT : INPUT; - VSYNC : INPUT; - HSYNC : INPUT; - DMA_DRQ : INPUT; - nIRQ[7..2] : OUTPUT; - INT_HANDLER_TA : OUTPUT; - ACP_CONF[31..0] : OUTPUT; - TIN0 : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - FB_B[3..0] :NODE; - INT_CTR[31..0] :DFFE; - INT_CTR_CS :NODE; - INT_LATCH[31..0] :DFF; - INT_LATCH_CS :NODE; - INT_CLEAR[31..0] :DFF; - INT_CLEAR_CS :NODE; - INT_IN[31..0] :NODE; - INT_ENA[31..0] :DFFE; - INT_ENA_CS :NODE; - ACP_CONF[31..0] :DFFE; - ACP_CONF_CS :NODE; - PSEUDO_BUS_ERROR :NODE; - UHR_AS :NODE; - UHR_DS :NODE; - RTC_ADR[5..0] :DFFE; - ACHTELSEKUNDEN[2..0] :DFFE; - WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 - PIC_INT_SYNC[2..0] :DFF; - INC_SEC :NODE; - INC_MIN :NODE; - INC_STD :NODE; - INC_TAG :NODE; - ANZAHL_TAGE_DES_MONATS[7..0]:NODE; - WINTERZEIT :NODE; - SOMMERZEIT :NODE; - INC_MONAT :NODE; - INC_JAHR :NODE; - UPDATE_ON :NODE; - -BEGIN --- BYT SELECT - FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD - # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD - # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD - # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD - # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - --- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN - INT_CTR[].CLK = MAIN_CLK; - INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 - INT_CTR[] = FB_AD[]; - INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR; - INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; - INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; - INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; --- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 - INT_ENA[].CLK = MAIN_CLK; - INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 - INT_ENA[] = FB_AD[]; - INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; - INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; - INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; - INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; --- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR - INT_CLEAR[].CLK = MAIN_CLK; - INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 - INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; - INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; - INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; - INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; --- INTERRUPT LATCH REGISTER READ ONLY - INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 --- INTERRUPT - !nIRQ2 = HSYNC & INT_ENA[26]; - !nIRQ3 = INT_CTR0 & INT_ENA[27]; - !nIRQ4 = VSYNC & INT_ENA[28]; - nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; - !nIRQ6 = !nMFP_INT & INT_ENA[30]; - !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; - -PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC - # FB_ADR[19..4]==H"F8E0" -- VME - # FB_ADR[19..4]==H"F920" -- PADDLE - # FB_ADR[19..4]==H"F921" -- PADDLE - # FB_ADR[19..4]==H"F922" -- PADDLE - # FB_ADR[19..4]==H"FFA8" -- MFP2 - # FB_ADR[19..4]==H"FFA9" -- MFP2 - # FB_ADR[19..4]==H"FFAA" -- MFP2 - # FB_ADR[19..4]==H"FFA8" -- MFP2 - # FB_ADR[19..8]==H"F87" -- TT SCSI - # FB_ADR[19..4]==H"FFC2" -- ST UHR - # FB_ADR[19..4]==H"FFC3" -- ST UHR - # FB_ADR[19..4]==H"F890" -- DMA SOUND - # FB_ADR[19..4]==H"F891" -- DMA SOUND - # FB_ADR[19..4]==H"F892"); -- DMA SOUND --- IF VIDEO ADR CHANGE -TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- VIDEO BASE ADR HIGH 0xFFFF8201/2 - --- INTERRUPT LATCH - INT_LATCH[] = H"FFFFFFFF"; - INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; - INT_LATCH1.CLK = E0_INT & INT_ENA[1]; - INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; - INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; - INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; - INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; - INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; - INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; - INT_LATCH8.CLK = VSYNC & INT_ENA[8]; - INT_LATCH9.CLK = HSYNC & INT_ENA[9]; - --- INTERRUPT CLEAR - INT_LATCH[].CLRN = !INT_CLEAR[]; - --- INT_IN - INT_IN0 = PIC_INT; - INT_IN1 = E0_INT; - INT_IN2 = DVI_INT; - INT_IN3 = !nPCI_INTA; - INT_IN4 = !nPCI_INTB; - INT_IN5 = !nPCI_INTC; - INT_IN6 = !nPCI_INTD; - INT_IN7 = DSP_INT; - INT_IN8 = VSYNC; - INT_IN9 = HSYNC; - INT_IN[25..10] = H"0"; - INT_IN26 = HSYNC; - INT_IN27 = INT_CTR0; - INT_IN28 = VSYNC; - INT_IN29 = INT_LATCH[]!=H"00000000"; - INT_IN30 = !nMFP_INT; - INT_IN31 = DMA_DRQ; ---*************************************************************************************** --- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE - ACP_CONF[].CLK = MAIN_CLK; - ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 - ACP_CONF[] = FB_AD[]; - ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR; - ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; - ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; - ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; ---*************************************************************************************** - --------------------------------------------------------------- --- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR ----------------------------------------------------------- - RTC_ADR[].CLK = MAIN_CLK; - RTC_ADR[] = FB_AD[21..16]; - UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 - UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963 - RTC_ADR[].ENA = UHR_AS & !nFB_WR; - WERTE[][].CLK = MAIN_CLK; - WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR; - WERTE[7..0][1] = FB_AD[23..16]; - WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR; - WERTE[7..0][3] = FB_AD[23..16]; - WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR; - WERTE[7..0][5] = FB_AD[23..16]; - WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR; - WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; - WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; - WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[7..0][10] = FB_AD[23..16]; - WERTE[7..0][11] = FB_AD[23..16]; - WERTE[7..0][12] = FB_AD[23..16]; - WERTE[7..0][13] = FB_AD[23..16]; - WERTE[7..0][14] = FB_AD[23..16]; - WERTE[7..0][15] = FB_AD[23..16]; - WERTE[7..0][16] = FB_AD[23..16]; - WERTE[7..0][17] = FB_AD[23..16]; - WERTE[7..0][18] = FB_AD[23..16]; - WERTE[7..0][19] = FB_AD[23..16]; - WERTE[7..0][20] = FB_AD[23..16]; - WERTE[7..0][21] = FB_AD[23..16]; - WERTE[7..0][22] = FB_AD[23..16]; - WERTE[7..0][23] = FB_AD[23..16]; - WERTE[7..0][24] = FB_AD[23..16]; - WERTE[7..0][25] = FB_AD[23..16]; - WERTE[7..0][26] = FB_AD[23..16]; - WERTE[7..0][27] = FB_AD[23..16]; - WERTE[7..0][28] = FB_AD[23..16]; - WERTE[7..0][29] = FB_AD[23..16]; - WERTE[7..0][30] = FB_AD[23..16]; - WERTE[7..0][31] = FB_AD[23..16]; - WERTE[7..0][32] = FB_AD[23..16]; - WERTE[7..0][33] = FB_AD[23..16]; - WERTE[7..0][34] = FB_AD[23..16]; - WERTE[7..0][35] = FB_AD[23..16]; - WERTE[7..0][36] = FB_AD[23..16]; - WERTE[7..0][37] = FB_AD[23..16]; - WERTE[7..0][38] = FB_AD[23..16]; - WERTE[7..0][39] = FB_AD[23..16]; - WERTE[7..0][40] = FB_AD[23..16]; - WERTE[7..0][41] = FB_AD[23..16]; - WERTE[7..0][42] = FB_AD[23..16]; - WERTE[7..0][43] = FB_AD[23..16]; - WERTE[7..0][44] = FB_AD[23..16]; - WERTE[7..0][45] = FB_AD[23..16]; - WERTE[7..0][46] = FB_AD[23..16]; - WERTE[7..0][47] = FB_AD[23..16]; - WERTE[7..0][48] = FB_AD[23..16]; - WERTE[7..0][49] = FB_AD[23..16]; - WERTE[7..0][50] = FB_AD[23..16]; - WERTE[7..0][51] = FB_AD[23..16]; - WERTE[7..0][52] = FB_AD[23..16]; - WERTE[7..0][53] = FB_AD[23..16]; - WERTE[7..0][54] = FB_AD[23..16]; - WERTE[7..0][55] = FB_AD[23..16]; - WERTE[7..0][56] = FB_AD[23..16]; - WERTE[7..0][57] = FB_AD[23..16]; - WERTE[7..0][58] = FB_AD[23..16]; - WERTE[7..0][59] = FB_AD[23..16]; - WERTE[7..0][60] = FB_AD[23..16]; - WERTE[7..0][61] = FB_AD[23..16]; - WERTE[7..0][62] = FB_AD[23..16]; - WERTE[7..0][63] = FB_AD[23..16]; - WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; - WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; - WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; - WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; - WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; - WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; - WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; - WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; - WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; - WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; - WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; - WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; - WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; - WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; - WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; - WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; - WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; - WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; - WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; - WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; - WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; - WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; - WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; - WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; - WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; - WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; - WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; - WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; - WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; - WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; - WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; - WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; - WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; - WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; - WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; - WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; - WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; - WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; - WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; - WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; - WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; - WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; - WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; - WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; - WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; - WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; - WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; - WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; - WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; - WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; - WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; - WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; - WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; - WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; - WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; - WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; - WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; - WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; - WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; - WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; - WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; - WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; - WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; - PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; - PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; - PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; - UPDATE_ON = !WERTE[7][11]; - WERTE[6][10].CLRN = GND; -- KEIN UIP - UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF - WERTE[2][11] = VCC; -- IMMER BINARY - WERTE[1][11] = VCC; -- IMMER 24H FORMAT - WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR - WERTE[7][13] = VCC; -- IMMER RICHTIG --- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) - SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL - WERTE[0][13] = SOMMERZEIT; - WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); - WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER --- ACHTELSEKUNDEN - ACHTELSEKUNDEN[].CLK = MAIN_CLK; - ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; - ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; --- SEKUNDEN - INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; - WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 - WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); --- MINUTEN - INC_MIN = INC_SEC & WERTE[][0]==59; -- - WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 - WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- --- STUNDEN - INC_STD = INC_MIN & WERTE[][2]==59; - WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 - WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT --- WOCHENTAG UND TAG - INC_TAG = INC_STD & WERTE[][2]==23; - WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 - # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER - WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); - ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) - # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) - # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 - # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; - WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE - # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER - WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- --- MONATE - INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- - WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 - # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER - WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); --- JAHR - INC_JAHR = INC_MONAT & WERTE[][8]==12; -- - WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 - WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); --- TRISTATE OUTPUT - - FB_AD[31..24] = lpm_bustri_BYT( - INT_CTR_CS & INT_CTR[31..24] - # INT_ENA_CS & INT_ENA[31..24] - # INT_LATCH_CS & INT_LATCH[31..24] - # INT_CLEAR_CS & INT_IN[31..24] - # ACP_CONF_CS & ACP_CONF[31..24] - ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[23..16] = lpm_bustri_BYT( - WERTE[][0] & RTC_ADR[]==0 & UHR_DS - # WERTE[][1] & RTC_ADR[]==1 & UHR_DS - # WERTE[][2] & RTC_ADR[]==2 & UHR_DS - # WERTE[][3] & RTC_ADR[]==3 & UHR_DS - # WERTE[][4] & RTC_ADR[]==4 & UHR_DS - # WERTE[][5] & RTC_ADR[]==5 & UHR_DS - # WERTE[][6] & RTC_ADR[]==6 & UHR_DS - # WERTE[][7] & RTC_ADR[]==7 & UHR_DS - # WERTE[][8] & RTC_ADR[]==8 & UHR_DS - # WERTE[][9] & RTC_ADR[]==9 & UHR_DS - # WERTE[][10] & RTC_ADR[]==10 & UHR_DS - # WERTE[][11] & RTC_ADR[]==11 & UHR_DS - # WERTE[][12] & RTC_ADR[]==12 & UHR_DS - # WERTE[][13] & RTC_ADR[]==13 & UHR_DS - # WERTE[][14] & RTC_ADR[]==14 & UHR_DS - # WERTE[][15] & RTC_ADR[]==15 & UHR_DS - # WERTE[][16] & RTC_ADR[]==16 & UHR_DS - # WERTE[][17] & RTC_ADR[]==17 & UHR_DS - # WERTE[][18] & RTC_ADR[]==18 & UHR_DS - # WERTE[][19] & RTC_ADR[]==19 & UHR_DS - # WERTE[][20] & RTC_ADR[]==20 & UHR_DS - # WERTE[][21] & RTC_ADR[]==21 & UHR_DS - # WERTE[][22] & RTC_ADR[]==22 & UHR_DS - # WERTE[][23] & RTC_ADR[]==23 & UHR_DS - # WERTE[][24] & RTC_ADR[]==24 & UHR_DS - # WERTE[][25] & RTC_ADR[]==25 & UHR_DS - # WERTE[][26] & RTC_ADR[]==26 & UHR_DS - # WERTE[][27] & RTC_ADR[]==27 & UHR_DS - # WERTE[][28] & RTC_ADR[]==28 & UHR_DS - # WERTE[][29] & RTC_ADR[]==29 & UHR_DS - # WERTE[][30] & RTC_ADR[]==30 & UHR_DS - # WERTE[][31] & RTC_ADR[]==31 & UHR_DS - # WERTE[][32] & RTC_ADR[]==32 & UHR_DS - # WERTE[][33] & RTC_ADR[]==33 & UHR_DS - # WERTE[][34] & RTC_ADR[]==34 & UHR_DS - # WERTE[][35] & RTC_ADR[]==35 & UHR_DS - # WERTE[][36] & RTC_ADR[]==36 & UHR_DS - # WERTE[][37] & RTC_ADR[]==37 & UHR_DS - # WERTE[][38] & RTC_ADR[]==38 & UHR_DS - # WERTE[][39] & RTC_ADR[]==39 & UHR_DS - # WERTE[][40] & RTC_ADR[]==40 & UHR_DS - # WERTE[][41] & RTC_ADR[]==41 & UHR_DS - # WERTE[][42] & RTC_ADR[]==42 & UHR_DS - # WERTE[][43] & RTC_ADR[]==43 & UHR_DS - # WERTE[][44] & RTC_ADR[]==44 & UHR_DS - # WERTE[][45] & RTC_ADR[]==45 & UHR_DS - # WERTE[][46] & RTC_ADR[]==46 & UHR_DS - # WERTE[][47] & RTC_ADR[]==47 & UHR_DS - # WERTE[][48] & RTC_ADR[]==48 & UHR_DS - # WERTE[][49] & RTC_ADR[]==49 & UHR_DS - # WERTE[][50] & RTC_ADR[]==50 & UHR_DS - # WERTE[][51] & RTC_ADR[]==51 & UHR_DS - # WERTE[][52] & RTC_ADR[]==52 & UHR_DS - # WERTE[][53] & RTC_ADR[]==53 & UHR_DS - # WERTE[][54] & RTC_ADR[]==54 & UHR_DS - # WERTE[][55] & RTC_ADR[]==55 & UHR_DS - # WERTE[][56] & RTC_ADR[]==56 & UHR_DS - # WERTE[][57] & RTC_ADR[]==57 & UHR_DS - # WERTE[][58] & RTC_ADR[]==58 & UHR_DS - # WERTE[][59] & RTC_ADR[]==59 & UHR_DS - # WERTE[][60] & RTC_ADR[]==60 & UHR_DS - # WERTE[][61] & RTC_ADR[]==61 & UHR_DS - # WERTE[][62] & RTC_ADR[]==62 & UHR_DS - # WERTE[][63] & RTC_ADR[]==63 & UHR_DS - # (0,RTC_ADR[]) & UHR_AS - # INT_CTR_CS & INT_CTR[23..16] - # INT_ENA_CS & INT_ENA[23..16] - # INT_LATCH_CS & INT_LATCH[23..16] - # INT_CLEAR_CS & INT_IN[23..16] - # ACP_CONF_CS & ACP_CONF[23..16] - ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[15..8] = lpm_bustri_BYT( - INT_CTR_CS & INT_CTR[15..8] - # INT_ENA_CS & INT_ENA[15..8] - # INT_LATCH_CS & INT_LATCH[15..8] - # INT_CLEAR_CS & INT_IN[15..8] - # ACP_CONF_CS & ACP_CONF[15..8] - ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[7..0] = lpm_bustri_BYT( - INT_CTR_CS & INT_CTR[7..0] - # INT_ENA_CS & INT_ENA[7..0] - # INT_LATCH_CS & INT_LATCH[7..0] - # INT_CLEAR_CS & INT_IN[7..0] - # ACP_CONF_CS & ACP_CONF[7..0] - ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - - INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; -END; - - diff --git a/FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd.bak b/FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd.bak deleted file mode 100644 index f674080..0000000 --- a/FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd.bak +++ /dev/null @@ -1,75 +0,0 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Fri Oct 16 15:40:59 2009 - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - - --- Entity Declaration - -ENTITY BLITTER IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT - ( - nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); - BLITTER_ON : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); - BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); - BLITTER_RUN : OUT STD_LOGIC; - BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); - BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); - BLITTER_SIG : OUT STD_LOGIC; - BLITTER_WR : OUT STD_LOGIC; - BLITTER_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) - ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END BLITTER; - - --- Architecture Body - -ARCHITECTURE BLITTER_architecture OF BLITTER IS - - -BEGIN - BLITTER_RUN <= '0'; - BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; - BLITTER_ADR <= x"FEDCBA9876543210"; - BLITTER_SIG <= '0'; - BLITTER_WR <= '0'; - BLITTER_TA <= '0'; - -END BLITTER_architecture; diff --git a/FPGA_quartus_ori/Video/DDR_CTR.tdf.bak b/FPGA_quartus_ori/Video/DDR_CTR.tdf.bak deleted file mode 100644 index ead66e8..0000000 --- a/FPGA_quartus_ori/Video/DDR_CTR.tdf.bak +++ /dev/null @@ -1,660 +0,0 @@ -TITLE "DDR_CTR"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_BYT.inc"; - --- FIFO WATER MARK -CONSTANT FIFO_LWM = 0; -CONSTANT FIFO_MWM = 200; -CONSTANT FIFO_HWM = 500; - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN DDR_CTR -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nRSTO : INPUT; - MAIN_CLK : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - DDR_SYNC_66M : INPUT; - CLR_FIFO : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - BLITTER_ADR[31..0] : INPUT; - BLITTER_SIG : INPUT; - BLITTER_WR : INPUT; - DDRCLK0 : INPUT; - CLK33M : INPUT; - FIFO_MW[8..0] : INPUT; - VA[12..0] : OUTPUT; - nVWE : OUTPUT; - nVRAS : OUTPUT; - nVCS : OUTPUT; - VCKE : OUTPUT; - nVCAS : OUTPUT; - FB_LE[3..0] : OUTPUT; - FB_VDOE[3..0] : OUTPUT; - CLEAR_FIFO_CNT : OUTPUT; - SR_FIFO_WRE : OUTPUT; - SR_DDR_FB : OUTPUT; - SR_DDR_WR : OUTPUT; - SR_DDRWR_D_SEL : OUTPUT; - SR_VDMP[7..0] : OUTPUT; - VIDEO_DDR_TA : OUTPUT; - SR_BLITTER_DACK : OUTPUT; - BA[1..0] : OUTPUT; - DDRWR_D_SEL1 : OUTPUT; - VDM_SEL[3..0] : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); - DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) - DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG - DS_T4R,DS_T5R, -- READ CPU UND BLITTER, - DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER - DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO - DS_CB6, DS_CB8, -- CLOSE FIFO BANK - DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS - LINE :NODE; - FB_B[3..0] :NODE; - VCAS :NODE; - VRAS :NODE; - VWE :NODE; - VA_P[12..0] :DFF; - BA_P[1..0] :DFF; - VA_S[12..0] :DFF; - BA_S[1..0] :DFF; - MCS[1..0] :DFF; - CPU_DDR_SYNC :DFF; - DDR_SEL :NODE; - DDR_CS :DFFE; - DDR_CONFIG :NODE; - SR_DDR_WR :DFF; - SR_DDRWR_D_SEL :DFF; - SR_VDMP[7..0] :DFF; - CPU_ROW_ADR[12..0] :NODE; - CPU_BA[1..0] :NODE; - CPU_COL_ADR[9..0] :NODE; - CPU_SIG :NODE; - CPU_REQ :DFF; - CPU_AC :DFF; - BUS_CYC :DFF; - BUS_CYC_END :NODE; - BLITTER_REQ :DFF; - BLITTER_AC :DFF; - BLITTER_ROW_ADR[12..0] :NODE; - BLITTER_BA[1..0] :NODE; - BLITTER_COL_ADR[9..0] :NODE; - FIFO_REQ :DFF; - FIFO_AC :DFF; - FIFO_ROW_ADR[12..0] :NODE; - FIFO_BA[1..0] :NODE; - FIFO_COL_ADR[9..0] :NODE; - FIFO_ACTIVE :NODE; - CLR_FIFO_SYNC :DFF; - CLEAR_FIFO_CNT :DFF; - STOP :DFF; - SR_FIFO_WRE :DFF; - FIFO_BANK_OK :DFF; - FIFO_BANK_NOT_OK :NODE; - DDR_REFRESH_ON :NODE; - DDR_REFRESH_CNT[10..0] :DFF; - DDR_REFRESH_REQ :DFF; - DDR_REFRESH_SIG[3..0] :DFFE; - REFRESH_TIME :DFF; - VIDEO_BASE_L_D[7..0] :DFFE; - VIDEO_BASE_L :NODE; - VIDEO_BASE_M_D[7..0] :DFFE; - VIDEO_BASE_M :NODE; - VIDEO_BASE_H_D[7..0] :DFFE; - VIDEO_BASE_H :NODE; - VIDEO_BASE_X_D[2..0] :DFFE; - VIDEO_ADR_CNT[22..0] :DFFE; - VIDEO_CNT_L :NODE; - VIDEO_CNT_M :NODE; - VIDEO_CNT_H :NODE; - VIDEO_BASE_ADR[22..0] :NODE; - VIDEO_ACT_ADR[26..0] :NODE; - -BEGIN - LINE = FB_SIZE0 & FB_SIZE1; --- BYT SELECT - FB_B0 = FB_ADR[1..0]==0 -- ADR==0 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR.CLK = MAIN_CLK; - CASE FB_REGDDR IS - WHEN FR_WAIT => - FB_LE0 = !nFB_WR; - IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - FB_REGDDR = FR_S0; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S0 => - IF DDR_CS THEN - FB_LE0 = !nFB_WR; - VIDEO_DDR_TA = VCC; - IF LINE THEN - FB_VDOE0 = !nFB_OE & !DDR_CONFIG; - FB_REGDDR = FR_S1; - ELSE - BUS_CYC_END = VCC; - FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; - FB_REGDDR = FR_WAIT; - END IF; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S1 => - IF DDR_CS THEN - FB_VDOE1 = !nFB_OE & !DDR_CONFIG; - FB_LE1 = !nFB_WR; - VIDEO_DDR_TA = VCC; - FB_REGDDR = FR_S2; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S2 => - IF DDR_CS THEN - FB_VDOE2 = !nFB_OE & !DDR_CONFIG; - FB_LE2 = !nFB_WR; - IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN - FB_REGDDR = FR_S2; - ELSE - VIDEO_DDR_TA = VCC; - FB_REGDDR = FR_S3; - END IF; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S3 => - IF DDR_CS THEN - FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; - FB_LE3 = !nFB_WR; - VIDEO_DDR_TA = VCC; - BUS_CYC_END = VCC; - FB_REGDDR = FR_WAIT; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - END CASE; --- DDR STEUERUNG ----------------------------------------------------- --- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; - VCKE = VIDEO_RAM_CTR0; - nVCS = !VIDEO_RAM_CTR1; - DDR_REFRESH_ON = VIDEO_RAM_CTR2; - DDR_CONFIG = VIDEO_RAM_CTR3; - FIFO_ACTIVE = VIDEO_RAM_CTR8; --------------------------------- - CPU_ROW_ADR[] = FB_ADR[26..14]; - CPU_BA[] = FB_ADR[13..12]; - CPU_COL_ADR[] = FB_ADR[11..2]; - nVRAS = !VRAS; - nVCAS = !VCAS; - nVWE = !VWE; - SR_DDR_WR.CLK = DDRCLK0; - SR_DDRWR_D_SEL.CLK = DDRCLK0; - SR_VDMP[7..0].CLK = DDRCLK0; - SR_FIFO_WRE.CLK = DDRCLK0; - CPU_AC.CLK = DDRCLK0; - FIFO_AC.CLK = DDRCLK0; - BLITTER_AC.CLK = DDRCLK0; - DDRWR_D_SEL1 = BLITTER_AC; --- SELECT LOGIC - DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; - DDR_CS.CLK = MAIN_CLK; - DDR_CS.ENA = FB_ALE; - DDR_CS = DDR_SEL; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER - CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG - # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS - # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER - CPU_REQ.CLK = DDR_SYNC_66M; - CPU_REQ = CPU_SIG - # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG - BUS_CYC.CLK = DDRCLK0; - BUS_CYC = BUS_CYC & !BUS_CYC_END; - -- STATE MACHINE SYNCHRONISIEREN ----------------- - MCS[].CLK = DDRCLK0; - MCS0 = MAIN_CLK; - MCS1 = MCS0; - CPU_DDR_SYNC.CLK = DDRCLK0; - CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN - --------------------------------------------------- - VA_S[].CLK = DDRCLK0; - BA_S[].CLK = DDRCLK0; - VA[] = VA_S[]; - BA[] = BA_S[]; - VA_P[].CLK = DDRCLK0; - BA_P[].CLK = DDRCLK0; --- DDR STATE MACHINE ----------------------------------------------- - DDR_SM.CLK = DDRCLK0; - CASE DDR_SM IS - WHEN DS_T1 => - IF DDR_REFRESH_REQ THEN - DDR_SM = DS_R2; - ELSE - IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? - IF DDR_CONFIG THEN -- JA - DDR_SM = DS_C2; - ELSE - IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE - VA_S[] = CPU_ROW_ADR[]; - BA_S[] = CPU_BA[]; - CPU_AC = VCC; - BUS_CYC = VCC; - DDR_SM = DS_T2B; - ELSE - IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT - VA_P[] = FIFO_ROW_ADR[]; - BA_P[] = FIFO_BA[]; - FIFO_AC = VCC; -- VORBESETZEN - ELSE - VA_P[] = BLITTER_ROW_ADR[]; - BA_P[] = BLITTER_BA[]; - BLITTER_AC = VCC; -- VORBESETZEN - END IF; - DDR_SM = DS_T2A; - END IF; - END IF; - ELSE - DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN - END IF; - END IF; - - WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - IF DDR_SEL & (nFB_WR # !LINE) THEN - VRAS = VCC; - VA[] = FB_AD[26..14]; - BA[] = FB_AD[13..12]; - VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - ELSE - VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; - VA[] = VA_P[]; - BA[] = BA_P[]; - VA_S[10] = !(FIFO_AC & FIFO_REQ); - FIFO_BANK_OK = FIFO_AC & FIFO_REQ; - FIFO_AC = FIFO_AC & FIFO_REQ; - BLITTER_AC = BLITTER_AC & BLITTER_REQ; - END IF; - DDR_SM = DS_T3; - - WHEN DS_T2B => - VRAS = VCC; - FIFO_BANK_NOT_OK = VCC; - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - DDR_SM = DS_T3; - - WHEN DS_T3 => - CPU_AC = CPU_AC; - FIFO_AC = FIFO_AC; - BLITTER_AC = BLITTER_AC; - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN - DDR_SM = DS_T4W; - ELSE - IF CPU_AC THEN -- CPU? - VA_S[9..0] = CPU_COL_ADR[]; - BA_S[] = CPU_BA[]; - DDR_SM = DS_T4R; - ELSE - IF FIFO_AC THEN -- FIFO? - VA_S[9..0] = FIFO_COL_ADR[]; - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T4F; - ELSE - IF BLITTER_AC THEN - VA_S[9..0] = BLITTER_COL_ADR[]; - BA_S[] = BLITTER_BA[]; - DDR_SM = DS_T4R; - ELSE - DDR_SM = DS_N8; - END IF; - END IF; - END IF; - END IF; --- READ - WHEN DS_T4R => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VCAS = VCC; - SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU - SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN - DDR_SM = DS_T5R; - - WHEN DS_T5R => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK - VA_S[9..0] = FIFO_COL_ADR[]; - VA_S[10] = GND; -- MANUEL PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; - END IF; --- WRITE - WHEN DS_T4W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - DDR_SM = DS_T5W; - - WHEN DS_T5W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VA_S[9..0] = CPU_AC & CPU_COL_ADR[] - # BLITTER_AC & BLITTER_COL_ADR[]; - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - BA_S[] = CPU_AC & CPU_BA[] - # BLITTER_AC & BLITTER_BA[]; - SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE - SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE - DDR_SM = DS_T6W; - - WHEN DS_T6W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VCAS = VCC; - VWE = VCC; - SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV - DDR_SM = DS_T7W; - - WHEN DS_T7W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - DDR_SM = DS_T8W; - - WHEN DS_T8W => - DDR_SM = DS_T9W; - - WHEN DS_T9W => - IF FIFO_REQ & FIFO_BANK_OK THEN - VA_S[9..0] = FIFO_COL_ADR[]; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; - END IF; --- FIFO READ - WHEN DS_T4F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T5F; - - WHEN DS_T5F => - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - ELSE - VA_S[9..0] = FIFO_COL_ADR[]+4; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN - END IF; - - WHEN DS_T6F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T7F; - - WHEN DS_T7F => - IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN - VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - ELSE - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - ELSE - VA_S[9..0] = FIFO_COL_ADR[]+4; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T8F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - END IF; - END IF; - - WHEN DS_T8F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - IF FIFO_MW[] - ELSE - DDR_SM = DS_T9F; - END IF; - - WHEN DS_T9F => - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - ELSE - VA_P[9..0] = FIFO_COL_ADR[]+4; - VA_P[10] = GND; -- NON AUTO PRECHARGE - BA_P[] = FIFO_BA[]; - DDR_SM = DS_T10F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - END IF; - - WHEN DS_T10F => - IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN - VRAS = VCC; - VA[] = FB_AD[26..14]; - BA[] = FB_AD[13..12]; - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK - DDR_SM = DS_T3; - ELSE - VCAS = VCC; - VA[] = VA_P[]; - BA[] = BA_P[]; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T7F; - END IF; - --- CONFIG CYCLUS - WHEN DS_C2 => - DDR_SM = DS_C3; - WHEN DS_C3 => - BUS_CYC = CPU_REQ; - DDR_SM = DS_C4; - WHEN DS_C4 => - IF CPU_REQ THEN - DDR_SM = DS_C5; - ELSE - DDR_SM = DS_T1; - END IF; - WHEN DS_C5 => - DDR_SM = DS_C6; - WHEN DS_C6 => - VA_S[] = FB_AD[12..0]; - BA_S[] = FB_AD[14..13]; - DDR_SM = DS_C7; - WHEN DS_C7 => - VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - DDR_SM = DS_N8; --- CLOSE FIFO BANK - WHEN DS_CB6 => - FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN - VWE = VCC; - DDR_SM = DS_N7; - WHEN DS_CB8 => - FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN - VWE = VCC; - DDR_SM = DS_T1; --- REFRESH 70NS = 10 ZYCLEN - WHEN DS_R2 => - IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN - VRAS = VCC; -- ALLE BANKS SCHLIESSEN - VWE = VCC; - VA[10] = VCC; - FIFO_BANK_NOT_OK = VCC; - DDR_SM = DS_R4; - ELSE - VCAS = VCC; - VRAS = VCC; - DDR_SM = DS_R3; - END IF; - WHEN DS_R3 => - DDR_SM = DS_R4; - WHEN DS_R4 => - DDR_SM = DS_R5; - WHEN DS_R5 => - DDR_SM = DS_R6; - WHEN DS_R6 => - DDR_SM = DS_N5; --- LEERSCHLAUFE - WHEN DS_N5 => - DDR_SM = DS_N6; - WHEN DS_N6 => - DDR_SM = DS_N7; - WHEN DS_N7 => - DDR_SM = DS_N8; - WHEN DS_N8 => - DDR_SM = DS_T1; - END CASE; - ---------------------------------------------------------------- --- BLITTER ---------------------- ------------------------------------------ - BLITTER_REQ.CLK = DDRCLK0; - BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; - BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; - BLITTER_BA1 = BLITTER_ADR13; - BLITTER_BA0 = BLITTER_ADR12; - BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; ------------------------------------------------------------------------------- --- FIFO --------------------------------- --------------------------------------------------------- - FIFO_REQ.CLK = DDRCLK0; - FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS ------------------------------------------------------------------------------------------ - DDR_REFRESH_CNT[].CLK = CLK33M; - DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 - REFRESH_TIME.CLK = DDRCLK0; - REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC - DDR_REFRESH_SIG[].CLK = DDRCLK0; - DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; - DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) - # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT - DDR_REFRESH_REQ.CLK = DDRCLK0; - DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; ------------------------------------------------------------ --- VIDEO REGISTER ----------------------- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D[].CLK = MAIN_CLK; - VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 - VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; - - VIDEO_BASE_M_D[].CLK = MAIN_CLK; - VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 - VIDEO_BASE_M_D[] = FB_AD[23..16]; - VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; - - VIDEO_BASE_H_D[].CLK = MAIN_CLK; - VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 - VIDEO_BASE_H_D[] = FB_AD[23..16]; - VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; - VIDEO_BASE_X_D[].CLK = MAIN_CLK; - VIDEO_BASE_X_D[] = FB_AD[26..24]; - VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; - - VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 - VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 - VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 - - FB_AD[31..24] = lpm_bustri_BYT( - VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) - # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) - ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - - FB_AD[23..16] = lpm_bustri_BYT( - VIDEO_BASE_L & VIDEO_BASE_L_D[] - # VIDEO_BASE_M & VIDEO_BASE_M_D[] - # VIDEO_BASE_H & VIDEO_BASE_H_D[] - # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] - # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] - # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] - ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); -END; - diff --git a/FPGA_quartus_ori/Video/DDR_CTR_BLITTER.tdf.bak b/FPGA_quartus_ori/Video/DDR_CTR_BLITTER.tdf.bak deleted file mode 100644 index 03052b4..0000000 --- a/FPGA_quartus_ori/Video/DDR_CTR_BLITTER.tdf.bak +++ /dev/null @@ -1,352 +0,0 @@ -TITLE "DDR_CTR_BLITTER"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_BYT.inc"; - - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN DDR_CTR_BLITTER -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nRSTO : INPUT; - MAIN_CLK : INPUT; - FIFO_FULL : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - DDR_SYNC_66M : INPUT; - VSYNC : INPUT; - BLITTER_ON : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - VDVZ[127..0] : INPUT; - DDRCLK[3..0] : INPUT; - BA0 : OUTPUT; - BA1 : OUTPUT; - VA[12..0] : OUTPUT; - nVWE : OUTPUT; - nVRAS : OUTPUT; - nVCS : OUTPUT; - VCKE : OUTPUT; - nVCAS : OUTPUT; - FIFO_WRE : OUTPUT; - FB_LE[3..0] : OUTPUT; - FB_VDOE[3..0] : OUTPUT; - START_CYC_RDWR : OUTPUT; - DDR_WR : OUTPUT; - CLEAR_FIFO_CNT : OUTPUT; - BLITTER_RUN : OUTPUT; - BLITTER_DOUT[127..0] : OUTPUT; - BLITTER_LE[3..0] : OUTPUT; - BLITTER_RDE : OUTPUT; - DDRWR_D_SEL[1..0] : OUTPUT; - VDMP[7..0] : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); - DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS); - LINE :NODE; - FB_B[3..0] :NODE; - VCAS :NODE; - VRAS :NODE; - VWE :NODE; - VA[12..0] :NODE; - BA0 :NODE; - BA1 :NODE; - DDR_WR :DFF; - DDR_SEL :NODE; - DDR_CONFIG :NODE; - DDRWR_D_SEL[1..0] :DFF; - CPU_ROW_ADR[12..0] :NODE; - CPU_BA0 :NODE; - CPU_BA1 :NODE; - CPU_COL_ADR[9..0] :NODE; - CPU_SIG :NODE; - CPU_REQ :DFF; - BLITTER_SIG :NODE; - BLITTER_REQ :DFF; - BLITTER_RUN :DFF; - BLITTER_WR :DFF; - BLITTER_ROW_ADR[12..0] :NODE; - BLITTER_BA0 :NODE; - BLITTER_BA1 :NODE; - BLITTER_COL_ADR[9..0] :NODE; - FIFO_SIG :NODE; - FIFO_REQ :DFF; - FIFO_ROW_ADR[12..0] :NODE; - FIFO_BA0 :NODE; - FIFO_BA1 :NODE; - FIFO_COL_ADR[9..0] :NODE; - FIFO_WRE :DFF; - FIFO_ACTIVE :NODE; - CLEAR_FIFO_CNT :DFF; - STOP :DFF; - DDR_REFRESH_ON :NODE; - VIDEO_BASE_L_D[3..0] :DFFE; - VIDEO_BASE_L :NODE; - VIDEO_BASE_M_D[7..0] :DFFE; - VIDEO_BASE_M :NODE; - VIDEO_BASE_H_D[7..0] :DFFE; - VIDEO_BASE_H :NODE; - VIDEO_BASE_X_D[7..0] :DFFE; - VIDEO_ADR_CNT[27..0] :DFFE; - VIDEO_CNT_L :NODE; - VIDEO_CNT_M :NODE; - VIDEO_CNT_H :NODE; - VIDEO_BASE_ADR[27..0] :NODE; - -BEGIN - LINE = FB_SIZE0 & FB_SIZE1; --- BYT SELECT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR.CLK = MAIN_CLK; - CASE FB_REGDDR IS - WHEN FR_WAIT => - IF DDR_SEL THEN - FB_REGDDR = FR_S0; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S0 => - FB_VDOE0 = !nFB_OE & !DDR_CONFIG; - FB_LE0 = !nFB_WR; - IF LINE THEN - FB_REGDDR = FR_S1; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S1 => - FB_VDOE1 = !nFB_OE & !DDR_CONFIG; - FB_LE1 = !nFB_WR; - FB_REGDDR = FR_S2; - WHEN FR_S2 => - FB_VDOE2 = !nFB_OE & !DDR_CONFIG; - FB_LE2 = !nFB_WR; - FB_REGDDR = FR_S3; - WHEN FR_S3 => - FB_VDOE3 = !nFB_OE & !DDR_CONFIG; - FB_LE3 = !nFB_WR; - FB_REGDDR = FR_WAIT; - END CASE; --- DDR STEUERUNG ----------------------------------------------------- --- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE - VCKE = VIDEO_RAM_CTR0; - nVCS = !VIDEO_RAM_CTR1; - FIFO_ACTIVE = VIDEO_RAM_CTR2; - DDR_CONFIG = VIDEO_RAM_CTR3; - DDR_REFRESH_ON = VIDEO_RAM_CTR4; --------------------------------- - CPU_ROW_ADR[] = FB_ADR[26..14]; - CPU_BA1 = FB_ADR13; - CPU_BA0 = FB_ADR12; - CPU_COL_ADR[] = FB_ADR[11..2]; - nVRAS = !VRAS; - nVCAS = !VCAS; - nVWE = !VWE; - DDR_WR.CLK = DDRCLK0; --- SELECT LOGIC - DDR_SEL = FB_ALE & FB_AD[31..29]==B"011"; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER - CPU_SIG = DDR_SEL & nFB_WR & !DDR_CONFIG -- READ SOFORT LOS - # FR_S0 & !nFB_WR -- WRITE SPÄTER AUCH CONFIG - # FR_S3 & !nFB_WR & LINE & !DDR_CONFIG; -- LINE WRITE - CPU_REQ = CPU_SIG; - CPU_REQ.CLK = DDR_SYNC_66M; - DDR_D_SEL[].CLK = DDRCLK3; --- DDR STATE MACHINE ----------------------------------------------- - DDR_SM.CLK = DDRCLK0; - CASE DDR_SM IS - WHEN DS_T1 => - IF MAIN_CLK THEN - DDR_WR = DDR_WR; -- WRITE HALTEN (VON T4) - DDR_SM = DS_T2; - ELSE - DDR_SM = DS_LS; -- SYNCHRONISIEREN - END IF; - WHEN DS_T2 => - IF !DDR_CONFIG THEN - VRAS = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON; - VA[] = CPU_SIG & CPU_ROW_ADR[] - # BLITTER_SIG & BLITTER_ROW_ADR[] - # FIFO_SIG & FIFO_ROW_ADR[]; - BA0 = CPU_SIG & CPU_BA0 - # BLITTER_SIG & BLITTER_BA0 - # FIFO_SIG & FIFO_BA0; - BA1 = CPU_SIG & CPU_BA1 - # BLITTER_SIG & BLITTER_BA1 - # FIFO_SIG & FIFO_BA1; - VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON; -- AUTO REFRESH WENN SONST NICHTS - BLITTER_REQ = BLITTER_SIG; - FIFO_REQ = FIFO_SIG; - END IF; - IF MAIN_CLK THEN - DDR_SM = DS_T3; - ELSE - DDR_SM = DS_LS; - END IF; - WHEN DS_T3 => - IF DDR_CONFIG & CPU_REQ THEN - VRAS = FB_AD18; - VCAS = FB_AD17; - VWE = FB_AD16; - BA1 = FB_AD14; - BA0 = FB_AD13; - VA[] = FB_AD[12..0]; - END IF; - IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN - DDR_SM = DS_LS; - ELSE - BLITTER_REQ = BLITTER_SIG; - FIFO_REQ = FIFO_SIG; - DDR_SM = DS_T4; - END IF; - WHEN DS_T4 => - FIFO_REQ = FIFO_SIG; - VCAS = VCC; - VWE = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; - VA[9..0] = CPU_REQ & CPU_COL_ADR[] - # BLITTER_REQ & BLITTER_COL_ADR[] - # FIFO_REQ & FIFO_COL_ADR[]; - VA10 = VCC; -- AUTO PRECHARGE - BA0 = CPU_REQ & CPU_BA0 - # BLITTER_REQ & BLITTER_BA0 - # FIFO_REQ & FIFO_BA0; - BA1 = CPU_REQ & CPU_BA1 - # BLITTER_REQ & BLITTER_BA1 - # FIFO_REQ & FIFO_BA1; - DDR_WR = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; - FIFO_REQ = FIFO_SIG; - IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? - DDR_SM = DS_T5; -- JA-> - ELSE - DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN - END IF; - WHEN DS_T5 => - FIFO_REQ = FIFO_SIG; - DDR_SM = DS_T6; - WHEN DS_T6 => - IF CPU_SIG THEN -- SOFORT UMSCHALTEN WENN CPU REQ - VRAS = VCC; - VA[] = CPU_ROW_ADR[]; - BA1 = CPU_BA1; - BA0 = CPU_BA0; - DDR_SM = DS_T3; - ELSE - FIFO_REQ = FIFO_SIG; - VCAS = VCC; - VA[9..0] = FIFO_COL_ADR[]; - VA10 = VCC; -- AUTO PRECHARGE - BA0 = FIFO_BA0; - BA1 = FIFO_BA1; - FIFO_WRE = FIFO_REQ; -- ODER FIFO LATCH IN 5 CYC 133 - IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? - DDR_SM = DS_T5; -- JA-> - ELSE - DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN - END IF; - END IF; - WHEN DS_LS => - IF !MAIN_CLK THEN -- LEERSTATE UND SYNC - DDR_SM = DS_T1; - ELSE - DDR_SM = DS_LS; - END IF; - END CASE; ------------------------------------------------------------------------------- --- FIFO --------------------------------- - FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG; - FIFO_REQ.CLK = DDR_SYNC_66M; - FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12]; - FIFO_BA1 = VIDEO_ADR_CNT11; - FIFO_BA0 = VIDEO_ADR_CNT10; - FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0]; - -- ZÄHLER RÜCKSETZEN WENN VSYNC ---------------- - CLEAR_FIFO_CNT.CLK = DDRCLK0; - CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE; - STOP.CLK = DDRCLK0; - STOP = VSYNC # CLEAR_FIFO_CNT; - VIDEO_ADR_CNT[].CLK = DDRCLK0; - VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] -- SET - # !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1); -- NEXT 16 BYTS - VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE; - FIFO_WRE.CLK = DDRCLK0; ---------------------------------------------------------------- --- BLITTER BUS IST 128 BIT BREIT ------ - BLITTER_SIG = GND & !CPU_SIG; - BLITTER_REQ.CLK = DDR_SYNC_66M; - BLITTER_RUN.CLK = DDRCLK0; - BLITTER_RUN = GND; - BLITTER_WR.CLK = DDRCLK0; - BLITTER_WR = GND; - DDRWR_D_SEL1 = BLITTER_WR; - BLITTER_ROW_ADR[] = H"0"; - BLITTER_BA1 = GND; - BLITTER_BA0 = GND; - BLITTER_COL_ADR[] = H"0"; - BLITTER_DOUT[] = H"0"; - BLITTER_LE[] = H"0"; ------------------------------------------------------------ --- VIDEO REGISTER ----------------------- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D[].CLK = MAIN_CLK; - VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; -- 820D/2 - VIDEO_BASE_L_D[] = FB_AD[23..20]; -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; - - VIDEO_BASE_M_D[].CLK = MAIN_CLK; - VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; -- 8203/2 - VIDEO_BASE_M_D[] = FB_AD[23..16]; - VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; - - VIDEO_BASE_H_D[].CLK = MAIN_CLK; - VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100"; -- 8200-1/2 - VIDEO_BASE_H_D[] = FB_AD[23..16]; - VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; - VIDEO_BASE_X_D[].CLK = MAIN_CLK; - VIDEO_BASE_X_D[] = FB_AD[31..24]; - VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; - - VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; -- 8209/2 - VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; -- 8207/2 - VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; -- 8205/2 - - FB_AD[31..24] = lpm_bustri_BYT( - VIDEO_BASE_H & VIDEO_BASE_X_D[] - # VIDEO_CNT_H & VIDEO_ADR_CNT[27..20] - ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - - FB_AD[23..16] = lpm_bustri_BYT( - VIDEO_BASE_L & (VIDEO_BASE_L_D[],B"0000") - # VIDEO_BASE_M & VIDEO_BASE_M_D[] - # VIDEO_BASE_H & VIDEO_BASE_H_D[] - # VIDEO_CNT_L & (VIDEO_ADR_CNT[3..0],B"0000") - # VIDEO_CNT_M & VIDEO_ADR_CNT[11..4] - # VIDEO_CNT_H & VIDEO_ADR_CNT[19..12] - ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); - - VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[]; - VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[]; - VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[]; - VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[]; -END; - diff --git a/FPGA_quartus_ori/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_quartus_ori/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak deleted file mode 100644 index fda03c9..0000000 --- a/FPGA_quartus_ori/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak +++ /dev/null @@ -1,675 +0,0 @@ -TITLE "VIDEO MODUSE UND CLUT CONTROL"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_WORD.inc"; -INCLUDE "lpm_bustri_BYT.inc"; - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN VIDEO_MOD_MUX_CLUTCTR -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - nRSTO : INPUT; - MAIN_CLK : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_WR : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nFB_BURST : INPUT; - FB_ADR[31..0] : INPUT; - CLK33M : INPUT; - CLK25M : INPUT; - BLITTER_RUN : INPUT; - CLK_VIDEO : INPUT; - VR_D[8..0] : INPUT; - VR_BUSY : INPUT; - COLOR8 : OUTPUT; - ACP_CLUT_RD : OUTPUT; - COLOR1 : OUTPUT; - FALCON_CLUT_RDH : OUTPUT; - FALCON_CLUT_RDL : OUTPUT; - FALCON_CLUT_WR[3..0] : OUTPUT; - ST_CLUT_RD : OUTPUT; - ST_CLUT_WR[1..0] : OUTPUT; - CLUT_MUX_ADR[3..0] : OUTPUT; - HSYNC : OUTPUT; - VSYNC : OUTPUT; - nBLANK : OUTPUT; - nSYNC : OUTPUT; - nPD_VGA : OUTPUT; - FIFO_RDE : OUTPUT; - COLOR2 : OUTPUT; - COLOR4 : OUTPUT; - PIXEL_CLK : OUTPUT; - CLUT_OFF[3..0] : OUTPUT; - BLITTER_ON : OUTPUT; - VIDEO_RAM_CTR[15..0] : OUTPUT; - VIDEO_MOD_TA : OUTPUT; - CCR[23..0] : OUTPUT; - CCSEL[2..0] : OUTPUT; - ACP_CLUT_WR[3..0] : OUTPUT; - INTER_ZEI : OUTPUT; - DOP_FIFO_CLR : OUTPUT; - VIDEO_RECONFIG : OUTPUT; - VR_WR : OUTPUT; - VR_RD : OUTPUT; - CLR_FIFO : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - CLK17M :DFF; - CLK13M :DFF; - ACP_CLUT_CS :NODE; - ACP_CLUT :NODE; - VIDEO_PLL_CONFIG_CS :NODE; - VR_WR :DFF; - VR_DOUT[8..0] :DFFE; - VR_FRQ[7..0] :DFFE; - VIDEO_PLL_RECONFIG_CS :NODE; - VIDEO_RECONFIG :DFF; - FALCON_CLUT_CS :NODE; - FALCON_CLUT :NODE; - ST_CLUT_CS :NODE; - ST_CLUT :NODE; - FB_B[3..0] :NODE; - FB_16B[1..0] :NODE; - ST_SHIFT_MODE[1..0] :DFFE; - ST_SHIFT_MODE_CS :NODE; - FALCON_SHIFT_MODE[10..0] :DFFE; - FALCON_SHIFT_MODE_CS :NODE; - CLUT_MUX_ADR[3..0] :DFF; - CLUT_MUX_AV[1..0][3..0] :DFF; - ACP_VCTR_CS :NODE; - ACP_VCTR[31..0] :DFFE; - CCR_CS :NODE; - CCR[23..0] :DFFE; - ACP_VIDEO_ON :NODE; - SYS_CTR[6..0] :DFFE; - SYS_CTR_CS :NODE; - VDL_LOF[15..0] :DFFE; - VDL_LOF_CS :NODE; - VDL_LWD[15..0] :DFFE; - VDL_LWD_CS :NODE; --- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT - HSYNC :DFF; - HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK - HSYNC_START :DFF; - LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT - VSYNC :DFF; - VSYNC_START :DFFE; - VSYNC_I[2..0] :DFFE; - nBLANK :DFF; - DISP_ON :DFF; - DPO_ZL :DFFE; - DPO_ON :DFF; - DPO_OFF :DFF; - VDTRON :DFF; - VDO_ZL :DFFE; - VDO_ON :DFF; - VDO_OFF :DFF; - VHCNT[11..0] :DFF; - SUB_PIXEL_CNT[6..0] :DFFE; - VVCNT[10..0] :DFFE; - VERZ[2..0][9..0] :DFF; - RAND[6..0] :DFF; - RAND_ON :NODE; - FIFO_RDE :DFF; - CLR_FIFO :DFFE; - START_ZEILE :DFFE; - SYNC_PIX :DFF; - SYNC_PIX1 :DFF; - SYNC_PIX2 :DFF; - CCSEL[2..0] :DFF; - COLOR16 :NODE; - COLOR24 :NODE; --- ATARI RESOLUTION - ATARI_SYNC :NODE; - ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 - ATARI_HH_CS :NODE; - ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480 - ATARI_VH_CS :NODE; - ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240 - ATARI_HL_CS :NODE; - ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240 - ATARI_VL_CS :NODE; --- HORIZONTAL - RAND_LINKS[11..0] :NODE; - HDIS_START[11..0] :NODE; - HDIS_END[11..0] :NODE; - RAND_RECHTS[11..0] :NODE; - HS_START[11..0] :NODE; - H_TOTAL[11..0] :NODE; - HDIS_LEN[11..0] :NODE; - MULF[5..0] :NODE; - VDL_HHT[11..0] :DFFE; - VDL_HHT_CS :NODE; - VDL_HBE[11..0] :DFFE; - VDL_HBE_CS :NODE; - VDL_HDB[11..0] :DFFE; - VDL_HDB_CS :NODE; - VDL_HDE[11..0] :DFFE; - VDL_HDE_CS :NODE; - VDL_HBB[11..0] :DFFE; - VDL_HBB_CS :NODE; - VDL_HSS[11..0] :DFFE; - VDL_HSS_CS :NODE; --- VERTIKAL - RAND_OBEN[10..0] :NODE; - VDIS_START[10..0] :NODE; - VDIS_END[10..0] :NODE; - RAND_UNTEN[10..0] :NODE; - VS_START[10..0] :NODE; - V_TOTAL[10..0] :NODE; - FALCON_VIDEO :NODE; - ST_VIDEO :NODE; - INTER_ZEI :DFF; - DOP_ZEI :DFF; - DOP_FIFO_CLR :DFF; - - VDL_VBE[10..0] :DFFE; - VDL_VBE_CS :NODE; - VDL_VDB[10..0] :DFFE; - VDL_VDB_CS :NODE; - VDL_VDE[10..0] :DFFE; - VDL_VDE_CS :NODE; - VDL_VBB[10..0] :DFFE; - VDL_VBB_CS :NODE; - VDL_VSS[10..0] :DFFE; - VDL_VSS_CS :NODE; - VDL_VFT[10..0] :DFFE; - VDL_VFT_CS :NODE; - VDL_VCT[8..0] :DFFE; - VDL_VCT_CS :NODE; - VDL_VMD[3..0] :DFFE; - VDL_VMD_CS :NODE; - -BEGIN --- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0]==0; -- ADR==0 - FB_16B1 = FB_ADR[0]==1 -- ADR==1 - # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT --- ACP CLUT -- - ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 - ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; - ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; - CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; ---FALCON CLUT -- - FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 - FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD - FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD - FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; - FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; --- ST CLUT -- - ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 - ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; - ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; --- ST SHIFT MODE - ST_SHIFT_MODE[].CLK = MAIN_CLK; - ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 - ST_SHIFT_MODE[] = FB_AD[25..24]; - ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO - COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN - COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN --- FALCON SHIFT MODE - FALCON_SHIFT_MODE[].CLK = MAIN_CLK; - FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 - FALCON_SHIFT_MODE[] = FB_AD[26..16]; - FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; - FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; --- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS - ACP_VCTR[].CLK = MAIN_CLK; - ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 - ACP_VCTR[31..8] = FB_AD[31..8]; - ACP_VCTR[5..0] = FB_AD[5..0]; - ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; - ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR; - ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR; - ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; - ACP_VIDEO_ON = ACP_VCTR0; - nPD_VGA = ACP_VCTR1; - -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG - -- HORIZONTAL TIMING 640x480 - ATARI_HH[].CLK = MAIN_CLK; - ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 - ATARI_HH[] = FB_AD[]; - ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; - ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; - ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; - ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 640x480 - ATARI_VH[].CLK = MAIN_CLK; - ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 - ATARI_VH[] = FB_AD[]; - ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; - ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; - ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; - ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - -- HORIZONTAL TIMING 320x240 - ATARI_HL[].CLK = MAIN_CLK; - ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 - ATARI_HL[] = FB_AD[]; - ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; - ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; - ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; - ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 320x240 - ATARI_VL[].CLK = MAIN_CLK; - ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 - ATARI_VL[] = FB_AD[]; - ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; - ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; - ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; - ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; --- VIDEO PLL CONFIG - VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VR_WR.CLK = MAIN_CLK; - VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; - VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; - VR_DOUT[].CLK = MAIN_CLK; - VR_DOUT[].ENA = !VR_BUSY; - VR_DOUT[] = VR_D[]; - VR_FRQ[].CLK = MAIN_CLK; - VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; - VR_FRQ[] = FB_AD[23..16]; --- VIDEO PLL RECONFIG - VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 - VIDEO_RECONFIG.CLK = MAIN_CLK; - VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; ------------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; --------------- COLOR MODE IM ACP SETZEN - COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; - ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; --- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER - ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; - FALCON_VIDEO = ACP_VCTR7; - FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; - ST_VIDEO = ACP_VCTR6; - ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; - CCSEL[].CLK = PIXEL_CLK; - CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION - # B"001" & FALCON_CLUT - # B"100" & ACP_CLUT - # B"101" & COLOR16 - # B"110" & COLOR24 - # B"111" & RAND_ON; --- DIVERSE (VIDEO)-REGISTER ---------------------------- --- RANDFARBE - CCR[].CLK = MAIN_CLK; - CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 - CCR[] = FB_AD[23..0]; - CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; - CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; - CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; ---SYS CTR - SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 - SYS_CTR[].CLK = MAIN_CLK; - SYS_CTR[6..0] = FB_AD[22..16]; - SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; - BLITTER_ON = !SYS_CTR3; ---VDL_LOF - VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 - VDL_LOF[].CLK = MAIN_CLK; - VDL_LOF[] = FB_AD[31..16]; - VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; - VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; ---VDL_LWD - VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 - VDL_LWD[].CLK = MAIN_CLK; - VDL_LWD[] = FB_AD[31..16]; - VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; - VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; --- HORIZONTAL --- VDL_HHT - VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 - VDL_HHT[].CLK = MAIN_CLK; - VDL_HHT[] = FB_AD[27..16]; - VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; - VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; --- VDL_HBE - VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 - VDL_HBE[].CLK = MAIN_CLK; - VDL_HBE[] = FB_AD[27..16]; - VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; - VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; --- VDL_HDB - VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 - VDL_HDB[].CLK = MAIN_CLK; - VDL_HDB[] = FB_AD[27..16]; - VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; - VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; --- VDL_HDE - VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 - VDL_HDE[].CLK = MAIN_CLK; - VDL_HDE[] = FB_AD[27..16]; - VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; - VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; --- VDL_HBB - VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 - VDL_HBB[].CLK = MAIN_CLK; - VDL_HBB[] = FB_AD[27..16]; - VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; - VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; --- VDL_HSS - VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 - VDL_HSS[].CLK = MAIN_CLK; - VDL_HSS[] = FB_AD[27..16]; - VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; - VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; --- VERTIKAL --- VDL_VBE - VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 - VDL_VBE[].CLK = MAIN_CLK; - VDL_VBE[] = FB_AD[26..16]; - VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; - VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; --- VDL_VDB - VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 - VDL_VDB[].CLK = MAIN_CLK; - VDL_VDB[] = FB_AD[26..16]; - VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; - VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; --- VDL_VDE - VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 - VDL_VDE[].CLK = MAIN_CLK; - VDL_VDE[] = FB_AD[26..16]; - VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; - VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; --- VDL_VBB - VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 - VDL_VBB[].CLK = MAIN_CLK; - VDL_VBB[] = FB_AD[26..16]; - VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; - VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; --- VDL_VSS - VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 - VDL_VSS[].CLK = MAIN_CLK; - VDL_VSS[] = FB_AD[26..16]; - VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; - VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; --- VDL_VFT - VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 - VDL_VFT[].CLK = MAIN_CLK; - VDL_VFT[] = FB_AD[26..16]; - VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; - VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; --- VDL_VCT - VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 - VDL_VCT[].CLK = MAIN_CLK; - VDL_VCT[] = FB_AD[24..16]; - VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; - VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; --- VDL_VMD - VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 - VDL_VMD[].CLK = MAIN_CLK; - VDL_VMD[] = FB_AD[19..16]; - VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; ---- REGISTER OUT - FB_AD[31..16] = lpm_bustri_WORD( - ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") - # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) - # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) - # VDL_LOF_CS & VDL_LOF[] - # VDL_LWD_CS & VDL_LWD[] - # VDL_HBE_CS & (0,VDL_HBE[]) - # VDL_HDB_CS & (0,VDL_HDB[]) - # VDL_HDE_CS & (0,VDL_HDE[]) - # VDL_HBB_CS & (0,VDL_HBB[]) - # VDL_HSS_CS & (0,VDL_HSS[]) - # VDL_HHT_CS & (0,VDL_HHT[]) - # VDL_VBE_CS & (0,VDL_VBE[]) - # VDL_VDB_CS & (0,VDL_VDB[]) - # VDL_VDE_CS & (0,VDL_VDE[]) - # VDL_VBB_CS & (0,VDL_VBB[]) - # VDL_VSS_CS & (0,VDL_VSS[]) - # VDL_VFT_CS & (0,VDL_VFT[]) - # VDL_VCT_CS & (0,VDL_VCT[]) - # VDL_VMD_CS & (0,VDL_VMD[]) - # ACP_VCTR_CS & ACP_VCTR[31..16] - # ATARI_HH_CS & ATARI_HH[31..16] - # ATARI_VH_CS & ATARI_VH[31..16] - # ATARI_HL_CS & ATARI_HL[31..16] - # ATARI_VL_CS & ATARI_VL[31..16] - # CCR_CS & (0,CCR[23..16]) - # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) - # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") - ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS - # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS - # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS - # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); - - FB_AD[15..0] = lpm_bustri_WORD( - ACP_VCTR_CS & ACP_VCTR[15..0] - # ATARI_HH_CS & ATARI_HH[15..0] - # ATARI_VH_CS & ATARI_VH[15..0] - # ATARI_HL_CS & ATARI_HL[15..0] - # ATARI_VL_CS & ATARI_VL[15..0] - # CCR_CS & CCR[15..0] - ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); - - VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS - # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS - # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS - # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; - --- VIDEO AUSGABE SETZEN - CLK17M.CLK = CLK33M; - CLK17M = !CLK17M; - CLK13M.CLK = CLK25M; - CLK13M = !CLK13M; - PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) - # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) - # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 - # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 - # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" - # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; --------------------------------------------------------------- --- HORIZONTALE SYNC LÄNGE in PIXEL_CLK ----------------------------------------------------------------- - HSY_LEN[].CLK = MAIN_CLK; - HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) - # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) - # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 - # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 - # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" - # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns - - MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR - # 4 & !ST_VIDEO & !VDL_VMD2 - # 16 & ST_VIDEO & VDL_VMD2 - # 32 & ST_VIDEO & !VDL_VMD2; - - - HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN - # 640 & !VDL_VMD2; - --- DOPPELZEILENMODUS - DOP_ZEI.CLK = MAIN_CLK; - DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS - INTER_ZEI.CLK = PIXEL_CLK; - INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC - # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC - DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START - - RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON - # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON - # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- - HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON - # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- - RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON - # HDIS_END[]+1 & !ACP_VIDEO_ON; -- - HS_START[] = VDL_HSS[] & ACP_VIDEO_ON - # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON - # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - - RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON - # 31 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON - # 32 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON - # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO - # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO - # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON - # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - VS_START[] = VDL_VSS[] & ACP_VIDEO_ON - # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON - # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --- ZÄHLER - LAST.CLK = PIXEL_CLK; - LAST = VHCNT[]==(H_TOTAL[]-2); - VHCNT[].CLK = PIXEL_CLK; - VHCNT[] = (VHCNT[] + 1) & !LAST; - VVCNT[].CLK = PIXEL_CLK; - VVCNT[].ENA = LAST; - VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); --- DISPLAY ON OFF - DPO_ZL.CLK = PIXEL_CLK; - DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[] - -Sample Waveforms for altdpram0.vhd - - -

Sample behavioral waveforms for design file altdpram0.vhd

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The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

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Fig. 1 : Wave showing read operation.

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The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

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Fig. 2 : Waveform showing write operation

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The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

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- - diff --git a/FPGA_quartus_ori/Video/altdpram1_wave0.jpg b/FPGA_quartus_ori/Video/altdpram1_wave0.jpg deleted file mode 100644 index 3ab5c5f..0000000 Binary files a/FPGA_quartus_ori/Video/altdpram1_wave0.jpg and /dev/null differ diff --git a/FPGA_quartus_ori/Video/altdpram1_wave1.jpg b/FPGA_quartus_ori/Video/altdpram1_wave1.jpg deleted file mode 100644 index f2f606b..0000000 Binary files a/FPGA_quartus_ori/Video/altdpram1_wave1.jpg and /dev/null differ diff --git a/FPGA_quartus_ori/Video/altdpram1_waveforms.html b/FPGA_quartus_ori/Video/altdpram1_waveforms.html deleted file mode 100644 index 85b4369..0000000 --- a/FPGA_quartus_ori/Video/altdpram1_waveforms.html +++ /dev/null @@ -1,16 +0,0 @@ - - -Sample Waveforms for altdpram1.vhd - - -

Sample behavioral waveforms for design file altdpram1.vhd

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The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

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Fig. 1 : Wave showing read operation.

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The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

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Fig. 2 : Waveform showing write operation

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The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

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- - diff --git a/FPGA_quartus_ori/Video/altdpram2_wave0.jpg b/FPGA_quartus_ori/Video/altdpram2_wave0.jpg deleted file mode 100644 index 2da3c66..0000000 Binary files a/FPGA_quartus_ori/Video/altdpram2_wave0.jpg and /dev/null differ diff --git a/FPGA_quartus_ori/Video/altdpram2_wave1.jpg b/FPGA_quartus_ori/Video/altdpram2_wave1.jpg deleted file mode 100644 index 829d237..0000000 Binary files a/FPGA_quartus_ori/Video/altdpram2_wave1.jpg and /dev/null differ diff --git a/FPGA_quartus_ori/Video/altdpram2_waveforms.html b/FPGA_quartus_ori/Video/altdpram2_waveforms.html deleted file mode 100644 index a856bf6..0000000 --- a/FPGA_quartus_ori/Video/altdpram2_waveforms.html +++ /dev/null @@ -1,16 +0,0 @@ - - -Sample Waveforms for altdpram2.vhd - - -

Sample behavioral waveforms for design file altdpram2.vhd

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The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

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Fig. 1 : Wave showing read operation.

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The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

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Fig. 2 : Waveform showing write operation

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The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

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- - diff --git a/FPGA_quartus_ori/Video/lpm_compare1_wave0.jpg b/FPGA_quartus_ori/Video/lpm_compare1_wave0.jpg deleted file mode 100644 index 0fbc252..0000000 Binary files a/FPGA_quartus_ori/Video/lpm_compare1_wave0.jpg and /dev/null differ diff --git a/FPGA_quartus_ori/Video/lpm_compare1_waveforms.html b/FPGA_quartus_ori/Video/lpm_compare1_waveforms.html deleted file mode 100644 index e8242d9..0000000 --- a/FPGA_quartus_ori/Video/lpm_compare1_waveforms.html +++ /dev/null @@ -1,13 +0,0 @@ - - -Sample Waveforms for lpm_compare1.vhd - - -

Sample behavioral waveforms for design file lpm_compare1.vhd

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The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator.

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Fig. 1 : Wave showing comparator operation.

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- - diff --git a/FPGA_quartus_ori/Video/lpm_fifoDZ_wave0.jpg b/FPGA_quartus_ori/Video/lpm_fifoDZ_wave0.jpg deleted file mode 100644 index 63d8667..0000000 Binary files a/FPGA_quartus_ori/Video/lpm_fifoDZ_wave0.jpg and /dev/null differ diff --git a/FPGA_quartus_ori/Video/lpm_fifoDZ_waveforms.html b/FPGA_quartus_ori/Video/lpm_fifoDZ_waveforms.html deleted file mode 100644 index 467441f..0000000 --- a/FPGA_quartus_ori/Video/lpm_fifoDZ_waveforms.html +++ /dev/null @@ -1,13 +0,0 @@ - - -Sample Waveforms for "lpm_fifoDZ.vhd" - - -

Sample behavioral waveforms for design file "lpm_fifoDZ.vhd"

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The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd". The design "lpm_fifoDZ.vhd" has a depth of 128 words of 128 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.

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Fig. 1 : Wave showing read and write operation.

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The above waveform shows the behavior of the design under normal read and write conditions with aclr .

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- - diff --git a/FPGA_quartus_ori/Video/lpm_fifo_dc0_wave0.jpg b/FPGA_quartus_ori/Video/lpm_fifo_dc0_wave0.jpg deleted file mode 100644 index e5d0f4b..0000000 Binary files a/FPGA_quartus_ori/Video/lpm_fifo_dc0_wave0.jpg and /dev/null differ diff --git a/FPGA_quartus_ori/Video/lpm_fifo_dc0_waveforms.html b/FPGA_quartus_ori/Video/lpm_fifo_dc0_waveforms.html deleted file mode 100644 index 3f52c1c..0000000 --- a/FPGA_quartus_ori/Video/lpm_fifo_dc0_waveforms.html +++ /dev/null @@ -1,13 +0,0 @@ - - -Sample Waveforms for lpm_fifo_dc0.vhd - - -

Sample behavioral waveforms for design file lpm_fifo_dc0.vhd

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The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.vhd. The design lpm_fifo_dc0.vhd has a depth of 512 words of 128 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

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Fig. 1 : Wave showing read and write operation.

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The above waveform shows the behavior of the design under normal read and write conditions with aclr .

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