diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index 13a6b38..beed306 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -387,67 +387,6 @@ set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS OFF set_global_assignment -name RTLV_SIMPLIFIED_LOGIC OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp.stp -set_global_assignment -name SDC_FILE firebee.sdc -set_global_assignment -name SOURCE_FILE firebee.qsf -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/Firebee.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DDR/DDR_CTRL.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/Video_Top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/RTC/rtc.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DSP/DSP.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/fbee_dma.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Blitter/Blitter_WF.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Interrupt/interrupt.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/VIDEO_CTRL.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/dcfifo1.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/dcfifo0.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Video/lpm_fifoDZ.cmp -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Video/lpm_fifo_dc0.cmp -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll_reconfig1.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll4.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll3.vhd -set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee/altpll3.cmp -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll2.vhd -set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee/altpll2.cmp -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll1.vhd -set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee/altpll1.cmp -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/Firebee_pkg.vhd -set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee/altpll_reconfig1.qip set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top @@ -684,7 +623,6 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[2] set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[3] set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4] set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd set_global_assignment -name EDA_TEST_BENCH_NAME firebee_tb -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME firebee_tb -section_id firebee_tb set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 ms" -section_id firebee_tb @@ -696,4 +634,66 @@ set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_mod set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id firebee_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb +set_global_assignment -name SDC_FILE firebee.sdc +set_global_assignment -name SOURCE_FILE firebee.qsf +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/Firebee.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DDR/DDR_CTRL.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/Video_Top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/RTC/rtc.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DSP/DSP.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/fbee_dma.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Blitter/Blitter_WF.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Interrupt/interrupt.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/VIDEO_CTRL.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/dcfifo1.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/dcfifo0.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Video/lpm_fifoDZ.cmp +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Video/lpm_fifo_dc0.cmp +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll_reconfig1.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll4.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll3.vhd +set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee/altpll3.cmp +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll2.vhd +set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee/altpll2.cmp +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/altpll1.vhd +set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee/altpll1.cmp +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee/Firebee_pkg.vhd +set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee/altpll_reconfig1.qip +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index 303638a..15b9020 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -13,7 +13,7 @@ ---- ---- ---- Author(s): ---- ---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- K ---- +---- ---- ---------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- @@ -25,13 +25,13 @@ ---- version. ---- ---- ---- ---- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; WITHout even the implied ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY OR FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU General Public ---- ----- License along WITH this program; IF not, write to the Free ---- +---- License along with this program; If not, write to the Free ---- ---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ---- Boston, MA 02110-1301, USA. ---- ---- ---- @@ -48,50 +48,50 @@ LIBRARY IEEE; ENTITY DDR_CTRL IS PORT( - clk_main : IN STD_LOGIC; - ddr_sync_66m : IN STD_LOGIC; - fb_adr : IN UNSIGNED (31 DOWNTO 0); - fb_cs1_n : IN STD_LOGIC; - fb_oe_n : IN STD_LOGIC; - fb_size0 : IN STD_LOGIC; - fb_size1 : IN STD_LOGIC; - fb_ale : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; - fifo_clr : IN STD_LOGIC; - video_control_register : IN UNSIGNED (15 DOWNTO 0); - blitter_adr : IN UNSIGNED (31 DOWNTO 0); - blitter_sig : IN STD_LOGIC; - blitter_wr : IN STD_LOGIC; + clk_main : IN std_logic; + ddr_sync_66m : IN std_logic; + fb_adr : IN unsigned(31 DOWNTO 0); + fb_cs1_n : IN std_logic; + fb_oe_n : IN std_logic; + fb_size0 : IN std_logic; + fb_size1 : IN std_logic; + fb_ale : IN std_logic; + fb_wr_n : IN std_logic; + fifo_clr : IN std_logic; + video_control_register : IN unsigned(15 DOWNTO 0); + blitter_adr : IN unsigned(31 DOWNTO 0); + blitter_sig : IN std_logic; + blitter_wr : IN std_logic; - ddrclk0 : IN STD_LOGIC; - clk_33m : IN STD_LOGIC; - fifo_mw : IN UNSIGNED (8 DOWNTO 0); + ddrclk0 : IN std_logic; + clk_33m : IN std_logic; + fifo_mw : IN unsigned(8 DOWNTO 0); - va : OUT UNSIGNED (12 DOWNTO 0); -- video Adress bus at the DDR chips - vwe_n : OUT STD_LOGIC; -- video memory write enable - vras_n : OUT STD_LOGIC; -- video memory RAS - vcs_n : OUT STD_LOGIC; -- video memory chip SELECT - vcke : OUT STD_LOGIC; -- video memory clock enable - vcas_n : OUT STD_LOGIC; -- video memory CAS + va : OUT unsigned(12 DOWNTO 0); -- video Adress bus at the DDR chips + vwe_n : OUT std_logic; -- video memory write enable + vras_n : OUT std_logic; -- video memory RAS + vcs_n : OUT std_logic; -- video memory chip SELECT + vcke : OUT std_logic; -- video memory clock enable + vcas_n : OUT std_logic; -- video memory CAS - fb_le : OUT UNSIGNED (3 DOWNTO 0); - fb_vdoe : OUT UNSIGNED (3 DOWNTO 0); + fb_le : OUT unsigned(3 DOWNTO 0); + fb_vdoe : OUT unsigned(3 DOWNTO 0); - sr_fifo_wre : OUT STD_LOGIC; - sr_ddr_fb : OUT STD_LOGIC; - sr_ddr_wr : OUT STD_LOGIC; - sr_ddrwr_d_sel : OUT STD_LOGIC; - sr_vdmp : OUT UNSIGNED (7 DOWNTO 0); + sr_fifo_wre : OUT std_logic; + sr_ddr_fb : OUT std_logic; + sr_ddr_wr : OUT std_logic; + sr_ddrwr_d_sel : OUT std_logic; + sr_vdmp : OUT unsigned(7 DOWNTO 0); - video_ddr_ta : OUT STD_LOGIC; - sr_blitter_dack : OUT STD_LOGIC; - ba : OUT UNSIGNED (1 DOWNTO 0); - ddrwr_d_sel1 : OUT STD_LOGIC; - vdm_sel : OUT UNSIGNED (3 DOWNTO 0); - data_in : IN UNSIGNED (31 DOWNTO 0); - data_out : OUT UNSIGNED (31 DOWNTO 16); - data_en_h : OUT STD_LOGIC; - data_en_l : OUT STD_LOGIC + video_ddr_ta : OUT std_logic; + sr_blitter_dack : OUT std_logic; + ba : OUT unsigned(1 DOWNTO 0); + ddrwr_d_sel1 : OUT std_logic; + vdm_sel : OUT unsigned(3 DOWNTO 0); + data_in : IN unsigned(31 DOWNTO 0); + data_out : OUT unsigned(31 DOWNTO 16); + data_en_h : OUT std_logic; + data_en_l : OUT std_logic ); END ENTITY DDR_CTRL; @@ -101,7 +101,7 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS CONSTANT FIFO_MWM : INTEGER := 200; -- medium water mark CONSTANT FIFO_HWM : INTEGER := 500; -- high water mark - -- DDR2 RAM controller bits: + -- DDR RAM controller bits: -- $F0000400: -- BIT 0: vcke; -- 1: NOT nVC @@ -114,16 +114,16 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS ALIAS vmem_config_enable IS video_control_register(3); ALIAS vmem_fifo_enable IS video_control_register(8); - TYPE access_width_t IS (long_access, word_access, byte_access); + TYPE access_width_t IS (long_access, word_access, byte_access, line_access); TYPE ddr_access_t IS (ddr_access_cpu, ddr_access_fifo, ddr_access_blitter, ddr_access_none); TYPE fb_regddr_t IS (fr_wait, fr_s0, fr_s1, fr_s2, fr_s3); - TYPE ddr_sm_t IS (ds_t1, ds_t2a, ds_t2b, ds_t3, ds_n5, ds_n6, ds_n7, ds_n8, -- Start (normal 8 cycles total = 60ns). - ds_c2, ds_c3, dc_c4, ds_c5, ds_c6, ds_c7, -- Configuration. - ds_t4r, ds_t5r, -- Read ddr_access_cpu OR ddr_access_blitter. - ds_t4w, ds_t5w, ds_t6w, ds_t7w, ds_t8w, ds_t9w, -- Write ddr_access_cpu OR ddr_access_blitter. - ds_t4f, ds_t5f, ds_t6f, ds_t7f, ds_t8f, ds_t9f, ds_t10f, -- Read ddr_access_fifo. - ds_cb6, ds_cb8, -- Close ddr_access_fifo bank. - ds_r2, ds_r3, ds_r4, ds_r5, ds_r6); -- Refresh: 10 x 7.5ns = 75ns. + TYPE ddr_sm_t IS (ds_t1, ds_t2a, ds_t2b, ds_t3, ds_n5, ds_n6, ds_n7, ds_n8, -- Start (normal 8 cycles total = 60ns). + ds_c2, ds_c3, dc_c4, ds_c5, ds_c6, ds_c7, -- Configuration. + ds_t4r, ds_t5r, -- Read ddr_access_cpu OR ddr_access_blitter. + ds_t4w, ds_t5w, ds_t6w, ds_t7w, ds_t8w, ds_t9w, -- Write ddr_access_cpu OR ddr_access_blitter. + ds_t4f, ds_t5f, ds_t6f, ds_t7f, ds_t8f, ds_t9f, ds_t10f, -- Read ddr_access_fifo. + ds_cb6, ds_cb8, -- Close ddr_access_fifo bank. + ds_r2, ds_r3, ds_r4, ds_r5, ds_r6); -- Refresh: 10 x 7.5ns = 75ns. SIGNAL access_width : access_width_t; SIGNAL fb_regddr : fb_regddr_t; @@ -131,86 +131,92 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS SIGNAL ddr_access : ddr_access_t; SIGNAL ddr_state : ddr_sm_t; SIGNAL ddr_next_state : ddr_sm_t; - SIGNAL byte_sel : UNSIGNED (3 DOWNTO 0); - SIGNAL sr_fifo_wre_i : STD_LOGIC; - SIGNAL vcas : STD_LOGIC; - SIGNAL vras : STD_LOGIC; - SIGNAL vwe : STD_LOGIC; - SIGNAL mcs : UNSIGNED (1 DOWNTO 0); - SIGNAL bus_cyc : STD_LOGIC; - SIGNAL bus_cyc_end : STD_LOGIC; - SIGNAL blitter_req : STD_LOGIC; - SIGNAL blitter_row_adr : UNSIGNED (12 DOWNTO 0); - SIGNAL blitter_ba : UNSIGNED (1 DOWNTO 0); - SIGNAL blitter_col_adr : UNSIGNED (9 DOWNTO 0); - SIGNAL cpu_ddr_sync : STD_LOGIC; - SIGNAL cpu_row_adr : UNSIGNED (12 DOWNTO 0); - SIGNAL cpu_ba : UNSIGNED (1 DOWNTO 0); - SIGNAL cpu_col_adr : UNSIGNED (9 DOWNTO 0); - SIGNAL cpu_req : STD_LOGIC; - SIGNAL ddr_sel : STD_LOGIC; - SIGNAL ddr_cs : STD_LOGIC; - SIGNAL fifo_req : STD_LOGIC; - SIGNAL fifo_row_adr : UNSIGNED (12 DOWNTO 0); - SIGNAL fifo_ba : UNSIGNED (1 DOWNTO 0); + SIGNAL byte_sel : unsigned(3 DOWNTO 0); + SIGNAL sr_fifo_wre_i : std_logic; + SIGNAL vcas : std_logic; + SIGNAL vras : std_logic; + SIGNAL vwe : std_logic; + SIGNAL mcs : unsigned(1 DOWNTO 0); + SIGNAL bus_cyc : std_logic; + SIGNAL bus_cyc_end : std_logic; + SIGNAL blitter_req : std_logic; + SIGNAL blitter_row_adr : unsigned(12 DOWNTO 0); + SIGNAL blitter_ba : unsigned(1 DOWNTO 0); + SIGNAL blitter_col_adr : unsigned(9 DOWNTO 0); + SIGNAL cpu_ddr_sync : std_logic; + SIGNAL cpu_row_adr : unsigned(12 DOWNTO 0); + SIGNAL cpu_ba : unsigned(1 DOWNTO 0); + SIGNAL cpu_col_adr : unsigned(9 DOWNTO 0); + SIGNAL cpu_req : std_logic; + SIGNAL ddr_sel : std_logic; + SIGNAL ddr_cs : std_logic; + SIGNAL fifo_req : std_logic; + SIGNAL fifo_row_adr : unsigned(12 DOWNTO 0); + SIGNAL fifo_ba : unsigned(1 DOWNTO 0); SIGNAL fifo_col_adr : UNSIGNED(9 DOWNTO 0); - SIGNAL fifo_clr_sync : STD_LOGIC; - SIGNAL vdm_sel_i : UNSIGNED (3 DOWNTO 0); - SIGNAL clear_fifo_cnt : STD_LOGIC; - SIGNAL stop : STD_LOGIC; - SIGNAL fifo_bank_ok : STD_LOGIC; + SIGNAL fifo_clr_sync : std_logic; + SIGNAL vdm_sel_i : unsigned(3 DOWNTO 0); + SIGNAL clear_fifo_cnt : std_logic; + SIGNAL stop : std_logic; + SIGNAL fifo_bank_ok : std_logic; SIGNAL ddr_refresh_cnt : UNSIGNED(10 DOWNTO 0) := "00000000000"; - SIGNAL ddr_refresh_req : STD_LOGIC; + SIGNAL ddr_refresh_req : std_logic; SIGNAL ddr_refresh_sig : UNSIGNED(3 DOWNTO 0); - SIGNAL need_refresh : STD_LOGIC; - SIGNAL video_base_l_d : UNSIGNED (7 DOWNTO 0); - SIGNAL video_base_l : STD_LOGIC; - SIGNAL video_base_m_d : UNSIGNED (7 DOWNTO 0); - SIGNAL video_base_m : STD_LOGIC; - SIGNAL video_base_h_d : UNSIGNED (7 DOWNTO 0); - SIGNAL video_base_h : STD_LOGIC; - SIGNAL video_base_x_d : UNSIGNED (2 DOWNTO 0); + SIGNAL need_refresh : std_logic; + SIGNAL video_base_l_d : unsigned(7 DOWNTO 0); + SIGNAL video_base_l : std_logic; + SIGNAL video_base_m_d : unsigned(7 DOWNTO 0); + SIGNAL video_base_m : std_logic; + SIGNAL video_base_h_d : unsigned(7 DOWNTO 0); + SIGNAL video_base_h : std_logic; + SIGNAL video_base_x_d : unsigned(2 DOWNTO 0); SIGNAL video_adr_cnt : UNSIGNED(22 DOWNTO 0); - SIGNAL video_cnt_l : STD_LOGIC; - SIGNAL video_cnt_m : STD_LOGIC; - SIGNAL video_cnt_h : STD_LOGIC; - SIGNAL video_base_adr : UNSIGNED (22 DOWNTO 0); - SIGNAL video_act_adr : UNSIGNED (26 DOWNTO 0); - SIGNAL fb_adr_i : UNSIGNED (32 DOWNTO 0); + SIGNAL video_cnt_l : std_logic; + SIGNAL video_cnt_m : std_logic; + SIGNAL video_cnt_h : std_logic; + SIGNAL video_base_adr : unsigned(22 DOWNTO 0); + SIGNAL video_act_adr : unsigned(26 DOWNTO 0); + SIGNAL fb_adr_i : unsigned(32 DOWNTO 0); - SIGNAL va_s : UNSIGNED (12 DOWNTO 0); - SIGNAL va_p : UNSIGNED (12 DOWNTO 0); - SIGNAL ba_s : UNSIGNED (1 DOWNTO 0) ; - SIGNAL ba_p : UNSIGNED (1 DOWNTO 0); - SIGNAL tsiz : UNSIGNED (1 DOWNTO 0); + SIGNAL va_s : unsigned(12 DOWNTO 0); + SIGNAL va_p : unsigned(12 DOWNTO 0); + SIGNAL ba_s : unsigned(1 DOWNTO 0) ; + SIGNAL ba_p : unsigned(1 DOWNTO 0); BEGIN - tsiz <= fb_size1 & fb_size0; - WITH tsiz SELECT - access_width <= long_access WHEN "11", - word_access WHEN "00", - byte_access WHEN OTHERS; - + access_width <= long_access WHEN fb_size1 = '0' AND fb_size0 = '0' ELSE + word_access WHEN fb_size1 = '1' AND fb_size0 = '0' ELSE + byte_access WHEN fb_size1 = '0' AND fb_size0 = '1' ELSE + line_access; + -- Byte selectors: - byte_sel(0) <= '1' WHEN access_width = long_access OR access_width = word_access ELSE - '1' WHEN fb_adr(1 DOWNTO 0) = "00" ELSE '0'; -- Byte 0. + byte_sel(0) <= '1' WHEN fb_adr(1 DOWNTO 0) = "00" OR + access_width = line_access OR + access_width = long_access + ELSE '0'; - byte_sel(1) <= '1' WHEN access_width = long_access OR access_width = word_access ELSE - '1' WHEN access_width = byte_access AND fb_adr(1) = '0' ELSE -- High word_access. - '1' WHEN fb_adr(1 DOWNTO 0) = "01" ELSE '0'; -- Byte 1. + byte_sel(1) <= '1' WHEN fb_adr(1 DOWNTO 0) = "01" OR + (access_width = word_access AND fb_adr(1) = '0') OR + access_width = line_access OR + access_width = long_access + ELSE '0'; - byte_sel(2) <= '1' WHEN access_width = long_access OR access_width = word_access ELSE - '1' WHEN fb_adr(1 DOWNTO 0) = "10" ELSE '0'; -- Byte 2. - - byte_sel(3) <= '1' WHEN access_width = long_access OR access_width = word_access ELSE - '1' WHEN access_width = byte_access AND fb_adr(1) = '1' ELSE -- Low word_access. - '1' WHEN fb_adr(1 DOWNTO 0) = "11" ELSE '0'; -- Byte 3. + byte_sel(2) <= '1' WHEN fb_adr(1 DOWNTO 0) = "10" OR + access_width = line_access OR + access_width = long_access + ELSE '0'; + byte_sel(3) <= '1' WHEN fb_adr(1 DOWNTO 0) = "11" OR + (access_width = word_access AND fb_adr(1) = '1') OR + access_width = line_access OR + access_width = long_access + ELSE '0'; + --------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------ ddr_access_cpu READ (REG DDR => ddr_access_cpu) AND WRITE (ddr_access_cpu => REG DDR) --------------------------------------------------------------------- fbctrl_reg : PROCESS BEGIN - WAIT UNTIL RISING_EDGE(clk_33m); + WAIT UNTIL rising_edge(clk_main); fb_regddr <= fb_regddr_next; END PROCESS FBCTRL_REG; @@ -283,12 +289,12 @@ BEGIN ------------------------------------------------------ DDR State Machine -------------------------------------------------------------------------------------- ddr_state_reg: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(ddrclk0); + WAIT UNTIL rising_edge(ddrclk0); ddr_state <= ddr_next_state; END PROCESS ddr_state_reg; ddr_state_dec: PROCESS(ddr_state, ddr_refresh_req, cpu_ddr_sync, vmem_config_enable, fb_wr_n, ddr_access, blitter_wr, fifo_req, fifo_bank_ok, - fifo_mw, cpu_req, video_adr_cnt, ddr_sel, tsiz, data_in, fifo_ba, ddr_refresh_sig) + fifo_mw, cpu_req, video_adr_cnt, ddr_sel, data_in, fifo_ba, ddr_refresh_sig) BEGIN CASE ddr_state IS WHEN ds_t1 => @@ -304,7 +310,7 @@ BEGIN ddr_next_state <= ds_t1; -- Synchronize. END IF; - WHEN ds_t2a => -- Fast access, IN this CASE page IS always NOT ok. + WHEN ds_t2a => -- Fast access, in this case page is always not ok. ddr_next_state <= ds_t3; WHEN ds_t2b => @@ -330,7 +336,7 @@ BEGIN ddr_next_state <= ds_t5r; WHEN ds_t5r => - IF fifo_req = '1' AND fifo_bank_ok = '1' THEN -- Insert ddr_access_fifo read, WHEN bank ok. + IF fifo_req = '1' AND fifo_bank_ok = '1' THEN -- Insert ddr_access_fifo read, when bank ok. ddr_next_state <= ds_t6f; ELSE ddr_next_state <= ds_cb6; @@ -401,7 +407,7 @@ BEGIN END IF; WHEN ds_t10f => - IF ddr_sel = '1' AND (fb_wr_n = '1' OR tsiz /= "11") AND data_in(13 DOWNTO 12) /= fifo_ba THEN + IF ddr_sel = '1' AND (fb_wr_n = '1' OR access_width = line_access) AND data_in(13 DOWNTO 12) /= fifo_ba THEN ddr_next_state <= ds_t3; ELSE ddr_next_state <= ds_t7f; @@ -474,7 +480,7 @@ BEGIN p_clk0 : PROCESS BEGIN - WAIT UNTIL RISING_EDGE(ddrclk0); + WAIT UNTIL rising_edge(ddrclk0); -- Default assignments; ddr_access <= ddr_access_none; @@ -592,7 +598,7 @@ BEGIN va_s(9 DOWNTO 0) <= cpu_col_adr; ba_s <= cpu_ba; ELSIF vmem_fifo_enable = '1' THEN - va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr); + va_s(9 DOWNTO 0) <= unsigned(fifo_col_adr); ba_s <= fifo_ba; ELSIF ddr_access = ddr_access_blitter THEN va_s(9 DOWNTO 0) <= blitter_col_adr; @@ -607,7 +613,7 @@ BEGIN END IF; ELSIF ddr_state = ds_t5r AND fifo_req = '1' AND fifo_bank_ok = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr); + va_s(9 DOWNTO 0) <= unsigned(fifo_col_adr); ba_s <= fifo_ba; ELSIF ddr_state = ds_t5r THEN va_s(10) <= '1'; @@ -646,7 +652,7 @@ BEGIN sr_ddrwr_d_sel <= '1'; ELSIF ddr_state = ds_t9w AND fifo_req = '1' AND fifo_bank_ok = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr); + va_s(9 DOWNTO 0) <= unsigned(fifo_col_adr); ba_s <= fifo_ba; ELSIF ddr_state = ds_t9w THEN va_s(10) <= '0'; @@ -656,7 +662,7 @@ BEGIN va_s(10) <= '1'; ELSIF ddr_state = ds_t5f AND fifo_req = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr + "100"); + va_s(9 DOWNTO 0) <= unsigned(fifo_col_adr + "100"); ba_s <= fifo_ba; ELSIF ddr_state = ds_t5f THEN va_s(10) <= '0'; @@ -668,7 +674,7 @@ BEGIN va_s(10) <= '1'; ELSIF ddr_state = ds_t7f AND fifo_req = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr + "100"); + va_s(9 DOWNTO 0) <= unsigned(fifo_col_adr + "100"); ba_s <= fifo_ba; ELSIF ddr_state = ds_t7f THEN va_s(10) <= '1'; @@ -676,7 +682,7 @@ BEGIN va_s(10) <= '1'; ELSIF ddr_state = ds_t9f AND fifo_req = '1' THEN va_p(10) <= '0'; - va_p(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr + "100"); + va_p(9 DOWNTO 0) <= unsigned(fifo_col_adr + "100"); ba_p <= fifo_ba; ELSIF ddr_state = ds_t9f THEN va_s(10) <= '1'; @@ -705,7 +711,7 @@ BEGIN p_ddr_cs: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(clk_main); + WAIT UNTIL rising_edge(clk_main); IF fb_ale = '1' THEN ddr_cs <= ddr_sel; END IF; @@ -713,7 +719,7 @@ BEGIN p_cpu_req: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(ddr_sync_66m); + WAIT UNTIL rising_edge(ddr_sync_66m); IF ddr_sel = '1' AND fb_wr_n = '1' AND vmem_config_enable = '0' THEN cpu_req <= '1'; @@ -721,9 +727,9 @@ BEGIN cpu_req <= '1'; ELSIF ddr_sel = '1' AND vmem_config_enable = '1' THEN -- Config, start immediately. cpu_req <= '1'; - ELSIF fb_regddr = fr_s1 AND fb_wr_n = '0' THEN -- Longword write later. + ELSIF fb_regddr = fr_s1 AND fb_wr_n = '0' THEN -- Longword write later. cpu_req <= '1'; - ELSIF fb_regddr /= fr_s1 AND fb_regddr /= fr_s3 AND bus_cyc_end = '0' AND bus_cyc = '0' THEN -- Halt, bus cycle in progress or ready. + ELSIF fb_regddr /= fr_s1 AND fb_regddr /= fr_s3 AND bus_cyc_end = '0' AND bus_cyc = '0' THEN -- Halt, bus cycle in progress or ready. cpu_req <= '0'; END IF; END PROCESS p_cpu_req; @@ -732,12 +738,22 @@ BEGIN -- Refresh: Always 8 at a time every 7.8us. -- 7.8us x 8 = 62.4us = 2059 -> 2048 @ 33MHz. BEGIN - WAIT UNTIL RISING_EDGE(clk_33m); - ddr_refresh_cnt <= ddr_refresh_cnt + 1; -- Count from 0 to 2047 + WAIT UNTIL rising_edge(clk_33m); + ddr_refresh_cnt <= ddr_refresh_cnt + 1; -- Count from 0 to 2047 END PROCESS p_refresh; sr_fifo_wre <= sr_fifo_wre_i; +-- IF ddr_sel = '1' AND (fb_wr_n = '1' OR access_width = line_access) THEN +-- BEGIN +-- vras <= '1'; +-- va <= data_in(26 DOWNTO 14); +-- ba <= data_in(13 DOWNTO 12); +-- va_s(10) <= '1'; +-- ELSE +-- -- vras = (fifo_ac ) +-- END; + va <= data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' ELSE data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE va_p WHEN ddr_state = ds_t2a ELSE @@ -815,7 +831,7 @@ BEGIN p_video_regs : PROCESS -- Video registers. BEGIN - WAIT UNTIL RISING_EDGE(clk_33m); + WAIT UNTIL rising_edge(clk_main); IF video_base_l = '1' AND fb_wr_n = '0' AND byte_sel(1) = '1' THEN video_base_l_d <= data_in(23 DOWNTO 16); -- 16 byte borders END IF; diff --git a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd index c9740ca..4813736 100644 --- a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd +++ b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd @@ -1,959 +1,959 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This design unit provides the video controller of the 'Fire- ---- ----- bee' computer. It is optimized for the use of an Altera Cyc- ---- ----- lone FPGA (EP3C40F484). This IP-Core is based on the first ---- ----- edition of the Firebee configware originally provided by ---- ----- Fredi Ashwanden AND Wolfgang Förster. This release is IN ---- ----- comparision to the first edition completely written IN VHDL. ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- AND/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed IN the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; IF NOT, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K12B 20120801 WF --- Initial Release of the second edition. - -LIBRARY IEEE; - USE IEEE.std_logic_1164.ALL; - USE ieee.numeric_std.ALL; - -ENTITY video_ctrl IS - PORT( - clk_main : IN STD_LOGIC; - fb_cs_n : IN STD_LOGIC_VECTOR (2 DOWNTO 1); - fb_wr_n : IN STD_LOGIC; - fb_oe_n : IN STD_LOGIC; - fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - fb_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - clk33m : IN STD_LOGIC; - clk25m : IN STD_LOGIC; - blitter_run : IN STD_LOGIC; - clk_video : IN STD_LOGIC; - vr_d : IN UNSIGNED (8 DOWNTO 0); - vr_busy : IN STD_LOGIC; - color8 : OUT STD_LOGIC; - fbee_clut_rd : OUT STD_LOGIC; - COLOR1 : OUT STD_LOGIC; - falcon_clut_rdh : OUT STD_LOGIC; - falcon_clut_rdl : OUT STD_LOGIC; - falcon_clut_wr : OUT UNSIGNED (3 DOWNTO 0); - clut_st_rd : OUT STD_LOGIC; - clut_st_wr : OUT UNSIGNED (1 DOWNTO 0); - clut_mux_adr : OUT UNSIGNED (3 DOWNTO 0); - hsync : OUT STD_LOGIC; - vsync : OUT STD_LOGIC; - blank_n : OUT STD_LOGIC; - sync_n : OUT STD_LOGIC; - pd_vga_n : OUT STD_LOGIC; - fifo_rde : OUT STD_LOGIC; - color2 : OUT STD_LOGIC; - color4 : OUT STD_LOGIC; - clk_pixel : OUT STD_LOGIC; - clut_off : OUT UNSIGNED (3 DOWNTO 0); - blitter_on : OUT STD_LOGIC; - video_ram_ctr : OUT UNSIGNED (15 DOWNTO 0); - video_mod_ta : OUT STD_LOGIC; - ccr : OUT UNSIGNED (23 DOWNTO 0); - ccsel : OUT UNSIGNED (2 DOWNTO 0); - fbee_clut_wr : OUT UNSIGNED (3 DOWNTO 0); - inter_zei : OUT STD_LOGIC; - dop_fifo_clr : OUT STD_LOGIC; - video_reconfig : OUT STD_LOGIC; - vr_wr : OUT STD_LOGIC; - vr_rd : OUT STD_LOGIC; - fifo_clr : OUT STD_LOGIC; - data_in : IN UNSIGNED (31 DOWNTO 0); - data_out : OUT UNSIGNED (31 DOWNTO 0); - data_en_h : OUT STD_LOGIC; - data_en_l : OUT STD_LOGIC - ); -END ENTITY video_ctrl; - -ARCHITECTURE behaviour OF video_ctrl IS - SIGNAL clk17m : STD_LOGIC; - SIGNAL clk13m : STD_LOGIC; - SIGNAL fbee_clut_cs : STD_LOGIC; - SIGNAL fbee_clut : STD_LOGIC; - SIGNAL video_pll_config_cs : STD_LOGIC; - SIGNAL vr_wr_i : STD_LOGIC; - SIGNAL vr_dout : UNSIGNED (8 DOWNTO 0); - SIGNAL vr_frq : UNSIGNED (7 DOWNTO 0); - SIGNAL video_pll_reconfig_cs : STD_LOGIC; - SIGNAL video_reconfig_i : STD_LOGIC; - SIGNAL falcon_clut_cs : STD_LOGIC; - SIGNAL falcon_clut : STD_LOGIC; - SIGNAL st_clut_cs : STD_LOGIC; - SIGNAL st_clut : STD_LOGIC; - SIGNAL fb_b : UNSIGNED (3 DOWNTO 0); - SIGNAL fb_16b : UNSIGNED (1 DOWNTO 0); - SIGNAL st_shift_mode : UNSIGNED (1 DOWNTO 0); - SIGNAL st_shift_mode_cs : STD_LOGIC; - SIGNAL falcon_shift_mode : UNSIGNED (10 DOWNTO 0); - SIGNAL falcon_shift_mode_cs : STD_LOGIC; - SIGNAL clut_mux_av_1 : UNSIGNED (3 DOWNTO 0); - SIGNAL clut_mux_av_0 : UNSIGNED (3 DOWNTO 0); - SIGNAL fbee_vctr_cs : STD_LOGIC; - SIGNAL fbee_vctr : UNSIGNED (31 DOWNTO 0); - SIGNAL ccr_cs : STD_LOGIC; - SIGNAL ccr_i : UNSIGNED (23 DOWNTO 0); - SIGNAL fbee_video_on : STD_LOGIC; - SIGNAL sys_ctr : UNSIGNED (6 DOWNTO 0); - SIGNAL sys_ctr_cs : STD_LOGIC; - SIGNAL vdl_lof : UNSIGNED (15 DOWNTO 0); - SIGNAL vdl_lof_cs : STD_LOGIC; - SIGNAL VDL_LWD : UNSIGNED (15 DOWNTO 0); - SIGNAL VDL_LWD_CS : STD_LOGIC; - - -- Miscellaneous control registers: - SIGNAL clut_ta : STD_LOGIC; -- Requires one wait state. - SIGNAL hsync_i : UNSIGNED (7 DOWNTO 0); - SIGNAL hsync_len : UNSIGNED (7 DOWNTO 0); -- Length of a hsync pulse IN clk_pixel cycles. - SIGNAL hsync_start : STD_LOGIC; - SIGNAL last : STD_LOGIC; -- Last pixel of a line indicator. - SIGNAL vsync_start : STD_LOGIC; - SIGNAL vsync_i : UNSIGNED (2 DOWNTO 0); - SIGNAL blank_i_n : STD_LOGIC; - SIGNAL disp_on : STD_LOGIC; - SIGNAL dpo_zl : STD_LOGIC; - SIGNAL dpo_on : STD_LOGIC; - SIGNAL dpo_off : STD_LOGIC; - SIGNAL vdtron : STD_LOGIC; - SIGNAL vdo_zl : STD_LOGIC; - SIGNAL vdo_on : STD_LOGIC; - SIGNAL vdo_off : STD_LOGIC; - SIGNAL vhcnt : UNSIGNED (11 DOWNTO 0); - SIGNAL sub_pixel_cnt : UNSIGNED (6 DOWNTO 0); - SIGNAL vvcnt : UNSIGNED (10 DOWNTO 0); - SIGNAL verz_2 : UNSIGNED (9 DOWNTO 0); - SIGNAL verz_1 : UNSIGNED (9 DOWNTO 0); - SIGNAL verz_0 : UNSIGNED (9 DOWNTO 0); - SIGNAL border : UNSIGNED (6 DOWNTO 0); - SIGNAL border_on : STD_LOGIC; - SIGNAL start_zeile : STD_LOGIC; - SIGNAL sync_pix : STD_LOGIC; - SIGNAL sync_pix1 : STD_LOGIC; - SIGNAL sync_pix2 : STD_LOGIC; - - -- Legacy ATARI resolutions: - SIGNAL atari_sync : STD_LOGIC; - SIGNAL atari_hh : UNSIGNED (31 DOWNTO 0); -- Horizontal timing 640x480. - SIGNAL atari_hh_cs : STD_LOGIC; - SIGNAL atari_vh : UNSIGNED (31 DOWNTO 0); -- Vertical timing 640x480. - SIGNAL atari_vh_cs : STD_LOGIC; - SIGNAL atari_hl : UNSIGNED (31 DOWNTO 0); -- Horizontal timing 320x240. - SIGNAL atari_hl_cs : STD_LOGIC; - SIGNAL atari_vl : UNSIGNED (31 DOWNTO 0); -- Vertical timing 320x240. - SIGNAL atari_vl_cs : STD_LOGIC; - - -- Horizontal stuff: - SIGNAL border_left : UNSIGNED (11 DOWNTO 0); - SIGNAL hdis_start : UNSIGNED (11 DOWNTO 0); - SIGNAL hdis_end : UNSIGNED (11 DOWNTO 0); - SIGNAL border_right : UNSIGNED (11 DOWNTO 0); - SIGNAL hs_start : UNSIGNED (11 DOWNTO 0); - SIGNAL h_total : UNSIGNED (11 DOWNTO 0); - SIGNAL hdis_len : UNSIGNED (11 DOWNTO 0); - SIGNAL mulf : UNSIGNED (5 DOWNTO 0); - SIGNAL vdl_hht : UNSIGNED (11 DOWNTO 0); - SIGNAL vdl_hht_cs : STD_LOGIC; - SIGNAL vdl_hbe : UNSIGNED (11 DOWNTO 0); - SIGNAL vdl_hbe_cs : STD_LOGIC; - SIGNAL vdl_hdb : UNSIGNED (11 DOWNTO 0); - SIGNAL vdl_hdb_cs : STD_LOGIC; - SIGNAL VDL_HDE : UNSIGNED (11 DOWNTO 0); - SIGNAL vdl_hde_cs : STD_LOGIC; - SIGNAL vdl_hbb : UNSIGNED (11 DOWNTO 0); - SIGNAL vdl_hbb_cs : STD_LOGIC; - SIGNAL vdl_hss : UNSIGNED (11 DOWNTO 0); - SIGNAL vdl_hss_cs : STD_LOGIC; - - -- Vertical stuff: - SIGNAL border_top : UNSIGNED (10 DOWNTO 0); - SIGNAL vdis_start : UNSIGNED (10 DOWNTO 0); - SIGNAL vdis_end : UNSIGNED (10 DOWNTO 0); - SIGNAL border_bottom : UNSIGNED (10 DOWNTO 0); - SIGNAL vs_start : UNSIGNED (10 DOWNTO 0); - SIGNAL v_total : UNSIGNED (10 DOWNTO 0); - SIGNAL falcon_video : STD_LOGIC; - SIGNAL st_video : STD_LOGIC; - SIGNAL inter_zei_i : STD_LOGIC; - SIGNAL dop_zei : STD_LOGIC; - - SIGNAL vdl_vbe : UNSIGNED (10 DOWNTO 0); - SIGNAL vdl_vbe_cs : STD_LOGIC; - SIGNAL vdl_vdb : UNSIGNED (10 DOWNTO 0); - SIGNAL VDL_VDB_CS : STD_LOGIC; - SIGNAL vdl_vde : UNSIGNED (10 DOWNTO 0); - SIGNAL vdl_vde_cs : STD_LOGIC; - SIGNAL vdl_vbb : UNSIGNED (10 DOWNTO 0); - SIGNAL vdl_vbb_cs : STD_LOGIC; - SIGNAL vdl_vss : UNSIGNED (10 DOWNTO 0); - SIGNAL vdl_vss_cs : STD_LOGIC; - SIGNAL vdl_vft : UNSIGNED (10 DOWNTO 0); - SIGNAL vdl_vft_cs : STD_LOGIC; - SIGNAL vdl_vct : UNSIGNED (8 DOWNTO 0); - SIGNAL vdl_vct_cs : STD_LOGIC; - SIGNAL vdl_vmd : UNSIGNED (3 DOWNTO 0); - SIGNAL vdl_vmd_cs : STD_LOGIC; - SIGNAL color1_i : STD_LOGIC; - SIGNAL color2_i : STD_LOGIC; - SIGNAL color4_i : STD_LOGIC; - SIGNAL color8_i : STD_LOGIC; - SIGNAL color16_i : STD_LOGIC; - SIGNAL color24_i : STD_LOGIC; - SIGNAL video_mod_ta_i : STD_LOGIC; - SIGNAL vr_rd_i : STD_LOGIC; - SIGNAL clk_pixel_i : STD_LOGIC; - SIGNAL mul1 : UNSIGNED (16 DOWNTO 0); - SIGNAL mul2 : UNSIGNED (16 DOWNTO 0); - SIGNAL mul3 : UNSIGNED (16 DOWNTO 0) := (OTHERS => 'Z'); -BEGIN - vr_wr <= vr_wr_i; - video_reconfig <= video_reconfig_i; - ccr <= ccr_i; - inter_zei <= inter_zei_i; - video_mod_ta <= video_mod_ta_i; - vr_rd <= vr_rd_i; - clk_pixel <= clk_pixel_i; - - -- Byte selectors: - fb_b(0) <= '1' WHEN fb_adr(1 DOWNTO 0) = "00" ELSE '0'; -- Byte 0. - - fb_b(1) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '0' ELSE -- High word. - '1' WHEN fb_adr(1 DOWNTO 0) = "01" ELSE '0'; -- Byte 1. - - fb_b(2) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. - '1' WHEN fb_adr(1 DOWNTO 0) = "10" ELSE '0'; -- Byte 2. - - fb_b(3) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '1' ELSE -- Low word. - '1' WHEN fb_adr(1 DOWNTO 0) = "11" ELSE '0'; -- Byte 3. - - -- 16 bit selectors: - fb_16b(0) <= NOT fb_adr(0); - fb_16b(1) <= '1'WHEN fb_adr(0) = '1' ELSE - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- No byte. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' ELSE -- No byte. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE '0'; -- No byte. - - -- Firebee CLUT: - fbee_clut_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 10) = "000000000000000000" ELSE '0'; -- 0-3FF/1024 - fbee_clut_rd <= '1' WHEN fbee_clut_cs = '1' AND fb_oe_n = '0' ELSE '0'; - fbee_clut_wr <= fb_b WHEN fbee_clut_cs = '1' AND fb_wr_n = '0' ELSE x"0"; - - p_clut_ta : PROCESS - BEGIN - WAIT UNTIL clk_main = '1' AND clk_main' EVENT; - IF video_mod_ta_i = '0' AND fbee_clut_cs = '1' THEN - clut_ta <= '1'; - ELSIF video_mod_ta_i = '0' AND falcon_clut_cs = '1' THEN - clut_ta <= '1'; - ELSIF video_mod_ta_i = '0' AND st_clut_cs = '1' THEN - clut_ta <= '1'; - ELSE - clut_ta <= '0'; - END IF; - END PROCESS p_clut_ta; - - --Falcon CLUT: - falcon_clut_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 10) = "1111100110" ELSE '0'; -- $F9800/$400 - falcon_clut_rdh <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '0' ELSE '0'; -- High word. - falcon_clut_rdl <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '1' ELSE '0'; -- Low word. - falcon_clut_wr(1 DOWNTO 0) <= fb_16b WHEN fb_adr(1) = '0' AND falcon_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; - falcon_clut_wr(3 DOWNTO 2) <= fb_16b WHEN fb_adr(1) = '1' AND falcon_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; - - -- ST CLUT: - st_clut_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 5) = "111110000010010" ELSE '0'; -- $F8240/$2 - clut_st_rd <= '1' WHEN st_clut_cs = '1' AND fb_oe_n = '0' ELSE '0'; - clut_st_wr <= fb_16b WHEN st_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; - - st_shift_mode_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 1) = "1111100000100110000" ELSE '0'; -- $F8260/$2. - falcon_shift_mode_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 1) = "1111100000100110011" ELSE '0'; -- $F8266/$2. - fbee_vctr_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000000" ELSE '0'; -- $400/$4 - atari_hh_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000100" ELSE '0'; -- $410/4 - atari_vh_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000101" ELSE '0'; -- $414/4 - atari_hl_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000110" ELSE '0'; -- $418/4 - atari_vl_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000111" ELSE '0'; -- $41C/4 - - p_video_control : PROCESS - BEGIN - WAIT UNTIL rising_edge(clk_main); - IF st_shift_mode_cs = '1' AND fb_wr_n = '0' AND fb_b(0) = '1' THEN - st_shift_mode <= data_in(25 DOWNTO 24); - END IF; - - IF falcon_shift_mode_cs = '1' AND fb_wr_n = '0' AND fb_b(2) = '1' THEN - falcon_shift_mode(10 DOWNTO 8) <= data_in(26 DOWNTO 24); - ELSIF falcon_shift_mode_cs = '1' AND fb_wr_n = '0' AND fb_b(3) = '1' THEN - falcon_shift_mode(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- Firebee VIDEO CONTROL: - -- Bit 0 = FBEE VIDEO ON, 1 = POWER ON VIDEO DAC, 2 = FBEE 24BIT, - -- Bit 3 = FBEE 16BIT, 4 = FBEE 8BIT, 5 = FBEE 1BIT, - -- Bit 6 = FALCON SHIFT MODE, 7 = ST SHIFT MODE, 9..8 = VCLK frequency, - -- Bit 15 = SYNC ALLOWED, 31..16 = video_ram_ctr, - -- Bit 25 = RANDFARBE EINSCHALTEN, 26 = STANDARD ATARI SYNCS. - IF fbee_vctr_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - fbee_vctr(31 DOWNTO 24) <= data_in(31 DOWNTO 24); - ELSIF fbee_vctr_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - fbee_vctr(23 DOWNTO 16) <= data_in(23 DOWNTO 16); - ELSIF fbee_vctr_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - fbee_vctr(15 DOWNTO 8) <= data_in(15 DOWNTO 8); - ELSIF fbee_vctr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - fbee_vctr(5 DOWNTO 0) <= data_in(5 DOWNTO 0); - END IF; - - -- ST or Falcon shift mode: assert WHEN X..shift register: - IF falcon_shift_mode_cs = '1' AND fb_wr_n = '0' THEN - fbee_vctr(7) <= falcon_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; - fbee_vctr(6) <= st_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; - END IF; - IF st_shift_mode_cs = '1' AND fb_wr_n = '0' THEN - fbee_vctr(7) <= falcon_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; - fbee_vctr(6) <= st_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; - END IF; - IF fbee_vctr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' AND data_in(0) = '1' THEN - fbee_vctr(7) <= falcon_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; - fbee_vctr(6) <= st_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; - END IF; - - -- ATARI ST mode - -- Horizontal timing 640x480: - IF atari_hh_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - atari_hh(31 DOWNTO 24) <= data_in(31 DOWNTO 24); - ELSIF atari_hh_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - atari_hh(23 DOWNTO 16) <= data_in(23 DOWNTO 16); - ELSIF atari_hh_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - atari_hh(15 DOWNTO 8) <= data_in(15 DOWNTO 8); - ELSIF atari_hh_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - atari_hh(7 DOWNTO 0) <= data_in(7 DOWNTO 0); - END IF; - - -- Vertical timing 640x480: - IF atari_vh_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - atari_vh(31 DOWNTO 24) <= data_in(31 DOWNTO 24); - ELSIF atari_vh_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - atari_vh(23 DOWNTO 16) <= data_in(23 DOWNTO 16); - ELSIF atari_vh_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - atari_vh(15 DOWNTO 8) <= data_in(15 DOWNTO 8); - ELSIF atari_vh_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - atari_vh(7 DOWNTO 0) <= data_in(7 DOWNTO 0); - END IF; - - -- Horizontal timing 320x240: - IF atari_hl_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - atari_hl(31 DOWNTO 24) <= data_in(31 DOWNTO 24); - ELSIF atari_hl_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - atari_hl(23 DOWNTO 16) <= data_in(23 DOWNTO 16); - ELSIF atari_hl_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - atari_hl(15 DOWNTO 8) <= data_in(15 DOWNTO 8); - ELSIF atari_hl_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - atari_hl(7 DOWNTO 0) <= data_in(7 DOWNTO 0); - END IF; - - -- Vertical timing 320x240: - IF atari_vl_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - atari_vl(31 DOWNTO 24) <= data_in(31 DOWNTO 24); - ELSIF atari_vl_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - atari_vl(23 DOWNTO 16) <= data_in(23 DOWNTO 16); - ELSIF atari_vl_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - atari_vl(15 DOWNTO 8) <= data_in(15 DOWNTO 8); - ELSIF atari_vl_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - atari_vl(7 DOWNTO 0) <= data_in(7 DOWNTO 0); - END IF; - END PROCESS p_video_control; - - clut_off <= falcon_shift_mode(3 DOWNTO 0) WHEN color4_i = '1' ELSE x"0"; - pd_vga_n <= fbee_vctr(1); - fbee_video_on <= fbee_vctr(0); - atari_sync <= fbee_vctr(26); -- If 1 -> automatic resolution. - - color1_i <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND st_shift_mode = "10" AND color8_i = '0' ELSE -- ST mono. - '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND falcon_shift_mode(10) = '1' AND color16_i = '0' AND color8_i = '0' ELSE -- Falcon mono. - '1' WHEN fbee_video_on = '1' AND fbee_vctr(5 DOWNTO 2) = "1000" ELSE '0'; -- Firebee mode. - color2_i <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND st_shift_mode = "01" AND color8_i = '0' ELSE '0'; -- ST 4 colours. - color4_i <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND st_shift_mode = "00" AND color8_i = '0' ELSE -- ST 16 colours. - '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND color16_i = '0' AND color8_i = '0' AND color1_i = '0' ELSE '0'; -- Falcon mode. - color8_i <= '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND falcon_shift_mode(4) = '1' AND color16_i = '0' ELSE -- Falcon mode. - '1' WHEN fbee_video_on = '1' AND fbee_vctr(4 DOWNTO 2) = "100" ELSE '0'; -- Firebee mode. - color16_i <= '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND falcon_shift_mode(8) = '1' ELSE -- Falcon mode. - '1' WHEN fbee_video_on = '1' AND fbee_vctr(3 DOWNTO 2) = "10" ELSE '0'; -- Firebee mode. - color24_i <= '1' WHEN fbee_video_on = '1' AND fbee_vctr(2) = '1' ELSE '0'; -- Firebee mode. - - COLOR1 <= color1_i; - color2 <= color2_i; - color4 <= color4_i; - color8 <= color8_i; - - -- VIDEO PLL config AND reconfig: - video_pll_config_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_b(0) = '1' AND fb_b(1) = '1' AND fb_adr(27 DOWNTO 9) = "0000000000000000011" ELSE '0'; -- $(F)000'0600-7FF -> 6/2 word AND long only. - video_pll_reconfig_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_b(0) = '1' AND fb_adr(27 DOWNTO 0) = x"0000800" ELSE '0'; -- $(F)000'0800. - vr_rd_i <= '1' WHEN video_pll_config_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' ELSE '0'; - - p_video_config: PROCESS - variable lock : boolean; - BEGIN - WAIT UNTIL rising_edge(clk_main); - - IF video_pll_config_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' AND vr_wr_i = '0' THEN - vr_wr_i <= '1'; -- This is a strobe. - ELSE - vr_wr_i <= '0'; - END IF; - - IF vr_busy = '1' THEN - vr_dout <= vr_d; - END IF; - - IF vr_wr_i = '1' AND fb_adr(8 DOWNTO 0) = "000000100" THEN - vr_frq <= data_in(23 DOWNTO 16); - END IF; - - IF video_pll_reconfig_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' AND lock = false THEN - video_reconfig_i <= '1'; -- This is a strobe. - lock := true; - ELSIF video_pll_reconfig_cs = '0' or fb_wr_n = '1' or vr_busy = '1' THEN - video_reconfig_i <= '0'; - lock := false; - ELSE - video_reconfig_i <= '0'; - END IF; - END PROCESS p_video_config; - - video_ram_ctr <= fbee_vctr(31 DOWNTO 16); - - -- Firebee colour modi: - fbee_clut <= '1' WHEN fbee_video_on = '1' AND (color1_i = '1' or color8_i = '1') ELSE - '1' WHEN st_video = '1' AND color1_i = '1'; - - falcon_video <= fbee_vctr(7); - falcon_clut <= '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND color16_i = '0' ELSE '0'; - st_video <= fbee_vctr(6); - st_clut <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND falcon_clut = '0' AND color1_i = '0' ELSE '0'; - - -- Several (video)-registers: - ccr_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr = x"f0000404" ELSE '0'; -- $F0000404 - Firebee video border color - sys_ctr_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8008" ELSE '0'; -- $FF8006 - Falcon monitor type register - vdl_lof_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff820e" ELSE '0'; -- $FF820E/F - line-width hi/lo. - VDL_LWD_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8210" ELSE '0'; -- $FF8210/1 - vertical wrap hi/lo. - vdl_hht_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8282" ELSE '0'; -- $FF8282/3 - horizontal hold timer hi/lo. - vdl_hbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8286" ELSE '0'; -- $FF8286/7 - horizontal border END hi/lo. - vdl_hdb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8288" ELSE '0'; -- $FF8288/9 - horizontal display BEGIN hi/lo. - vdl_hde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828a" ELSE '0'; -- $FF828A/B - horizontal display END hi/lo. - vdl_hbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8284" ELSE '0'; -- $FF8284/5 - horizontal border BEGIN hi/lo. - vdl_hss_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828c" ELSE '0'; -- $FF828C/D - position hsync (HSS). - vdl_vft_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a2" ELSE '0'; -- $FF82A2/3 - video frequency timer (VFT). - vdl_vbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a4" ELSE '0'; -- $FF82A4/5 - vertical blank on (IN half line steps). - vdl_vbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a6" ELSE '0'; -- $FF82A6/7 - vertical blank off (IN half line steps). - VDL_VDB_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a8" ELSE '0'; -- $FF82A8/9 - vertical display BEGIN (VDB). - vdl_vde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82aa" ELSE '0'; -- $FF82AA/B - vertical display END (VDE). - vdl_vss_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82ac" ELSE '0'; -- $FF82AC/D - position vsync (VSS). - vdl_vct_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82c0" ELSE '0'; -- $FF82C0/1 - clock control (VCO). - vdl_vmd_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82c2" ELSE '0'; -- $FF82C2/3 - resolution control. - - p_misc_ctrl : PROCESS - BEGIN - WAIT UNTIL rising_edge(clk_main); - - -- Colour of video borders - IF ccr_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - ccr_i(23 DOWNTO 16) <= data_in(23 DOWNTO 16); - ELSIF ccr_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - ccr_i(15 DOWNTO 8) <= data_in(15 DOWNTO 8); - ELSIF ccr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - ccr_i(7 DOWNTO 0) <= data_in(7 DOWNTO 0); - END IF; - - -- SYS CTRL: - IF sys_ctr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - sys_ctr <= data_in(22 DOWNTO 16); - END IF; - - --vdl_lof: - IF vdl_lof_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - vdl_lof(15 DOWNTO 8) <= data_in(31 DOWNTO 24); - ELSIF vdl_lof_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - vdl_lof(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - --VDL_LWD - IF VDL_LWD_CS = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - VDL_LWD(15 DOWNTO 8) <= data_in(31 DOWNTO 24); - ELSIF VDL_LWD_CS = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - VDL_LWD(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- Horizontal: - -- vdl_hht: - IF vdl_hht_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - vdl_hht(11 DOWNTO 8) <= data_in(27 DOWNTO 24); - ELSIF vdl_hht_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - vdl_hht(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_hbe: - IF vdl_hbe_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - vdl_hbe(11 DOWNTO 8) <= data_in(27 DOWNTO 24); - ELSIF vdl_hbe_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - vdl_hbe(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_hdb: - IF vdl_hdb_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - vdl_hdb(11 DOWNTO 8) <= data_in(27 DOWNTO 24); - ELSIF vdl_hdb_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - vdl_hdb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- VDL_HDE: - IF vdl_hde_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - VDL_HDE(11 DOWNTO 8) <= data_in(27 DOWNTO 24); - ELSIF vdl_hde_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - VDL_HDE(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_hbb: - IF vdl_hbb_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - vdl_hbb(11 DOWNTO 8) <= data_in(27 DOWNTO 24); - ELSIF vdl_hbb_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - vdl_hbb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_hss: - IF vdl_hss_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - vdl_hss(11 DOWNTO 8) <= data_in(27 DOWNTO 24); - ELSIF vdl_hss_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - vdl_hss(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- Vertical: - -- vdl_vbe: - IF vdl_vbe_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - vdl_vbe(10 DOWNTO 8) <= data_in(26 DOWNTO 24); - ELSIF vdl_vbe_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - vdl_vbe(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_vdb: - IF VDL_VDB_CS = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - vdl_vdb(10 DOWNTO 8) <= data_in(26 DOWNTO 24); - ELSIF VDL_VDB_CS = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - vdl_vdb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_vde: - IF vdl_vde_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - vdl_vde(10 DOWNTO 8) <= data_in(26 DOWNTO 24); - ELSIF vdl_vde_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - vdl_vde(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_vbb: - IF vdl_vbb_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - vdl_vbb(10 DOWNTO 8) <= data_in(26 DOWNTO 24); - ELSIF vdl_vbb_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - vdl_vbb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_vss - IF vdl_vss_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - vdl_vss(10 DOWNTO 8) <= data_in(26 DOWNTO 24); - ELSIF vdl_vss_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - vdl_vss(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_vft - IF vdl_vft_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN - vdl_vft(10 DOWNTO 8) <= data_in(26 DOWNTO 24); - ELSIF vdl_vft_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - vdl_vft(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_vct(2): 1 = 32MHz clk_pixel, 0 = 25MHZ; vdl_vct(0): 1 = linedoubling. - IF vdl_vct_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - vdl_vct(8) <= data_in(24); - ELSIF vdl_vct_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - vdl_vct(7 DOWNTO 0) <= data_in(23 DOWNTO 16); - END IF; - - -- vdl_vmd(2): 1 = clk_pixel/2. - IF vdl_vmd_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN - vdl_vmd <= data_in(19 DOWNTO 16); - END IF; - END PROCESS p_misc_ctrl; - - blitter_on <= NOT sys_ctr(3); - - -- Register OUT: - data_out(31 DOWNTO 16) <= "000000" & st_shift_mode & x"00" WHEN st_shift_mode_cs = '1' ELSE - "00000" & falcon_shift_mode WHEN falcon_shift_mode_cs = '1' ELSE - "100000000" & sys_ctr(6 DOWNTO 4) & NOT blitter_run & sys_ctr(2 DOWNTO 0) WHEN sys_ctr_cs = '1' ELSE - vdl_lof WHEN vdl_lof_cs = '1' ELSE - VDL_LWD WHEN VDL_LWD_CS = '1' ELSE - x"0" & vdl_hbe WHEN vdl_hbe_cs = '1' ELSE - x"0" & vdl_hdb WHEN vdl_hdb_cs = '1' ELSE - x"0" & VDL_HDE WHEN vdl_hde_cs = '1' ELSE - x"0" & vdl_hbb WHEN vdl_hbb_cs = '1' ELSE - x"0" & vdl_hss WHEN vdl_hss_cs = '1' ELSE - x"0" & vdl_hht WHEN vdl_hht_cs = '1' ELSE - "00000" & vdl_vbe WHEN vdl_vbe_cs = '1' ELSE - "00000" & vdl_vdb WHEN VDL_VDB_CS = '1' ELSE - "00000" & vdl_vde WHEN vdl_vde_cs = '1' ELSE - "00000" & vdl_vbb WHEN vdl_vbb_cs = '1' ELSE - "00000" & vdl_vss WHEN vdl_vss_cs = '1' ELSE - "00000" & vdl_vft WHEN vdl_vft_cs = '1' ELSE - "0000000" & vdl_vct WHEN vdl_vct_cs = '1' ELSE - x"000" & vdl_vmd WHEN vdl_vmd_cs = '1' ELSE - fbee_vctr(31 DOWNTO 16) WHEN fbee_vctr_cs = '1' ELSE - atari_hh(31 DOWNTO 16) WHEN atari_hh_cs = '1' ELSE - atari_vh(31 DOWNTO 16) WHEN atari_vh_cs = '1' ELSE - atari_hl(31 DOWNTO 16) WHEN atari_hl_cs = '1' ELSE - atari_vl(31 DOWNTO 16) WHEN atari_vl_cs = '1' ELSE - x"00" & ccr_i(23 DOWNTO 16) WHEN ccr_cs = '1' ELSE - "0000000" & vr_dout WHEN video_pll_config_cs = '1' ELSE - vr_busy & "0000" & vr_wr_i & vr_rd_i & video_reconfig_i & x"FA" WHEN video_pll_reconfig_cs = '1' ELSE (OTHERS => '0'); - - data_out(15 DOWNTO 0) <= fbee_vctr(15 DOWNTO 0) WHEN fbee_vctr_cs = '1' ELSE - atari_hh(15 DOWNTO 0) WHEN atari_hh_cs = '1' ELSE - atari_vh(15 DOWNTO 0) WHEN atari_vh_cs = '1' ELSE - atari_hl(15 DOWNTO 0) WHEN atari_hl_cs = '1' ELSE - atari_vl(15 DOWNTO 0) WHEN atari_vl_cs = '1' ELSE - ccr_i(15 DOWNTO 0) WHEN ccr_cs = '1' ELSE (OTHERS => '0'); - - data_en_h <= (st_shift_mode_cs or falcon_shift_mode_cs or fbee_vctr_cs or ccr_cs or sys_ctr_cs or vdl_lof_cs or VDL_LWD_CS or - vdl_hbe_cs or vdl_hdb_cs or vdl_hde_cs or vdl_hbb_cs or vdl_hss_cs or vdl_hht_cs or - atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs or video_pll_config_cs or video_pll_reconfig_cs or - vdl_vbe_cs or VDL_VDB_CS or vdl_vde_cs or vdl_vbb_cs or vdl_vss_cs or vdl_vft_cs or vdl_vct_cs or vdl_vmd_cs) AND NOT fb_oe_n; - - data_en_l <= (fbee_vctr_cs or ccr_cs or atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs ) AND NOT fb_oe_n; - - video_mod_ta_i <= clut_ta or st_shift_mode_cs or falcon_shift_mode_cs or fbee_vctr_cs or sys_ctr_cs or vdl_lof_cs or VDL_LWD_CS or - vdl_hbe_cs or vdl_hdb_cs or vdl_hde_cs or vdl_hbb_cs or vdl_hss_cs or vdl_hht_cs or - atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs or - vdl_vbe_cs or VDL_VDB_CS or vdl_vde_cs or vdl_vbb_cs or vdl_vss_cs or vdl_vft_cs or vdl_vct_cs or vdl_vmd_cs; - - p_clk_16m5 : PROCESS - BEGIN - WAIT UNTIL rising_edge(clk33m); - clk17m <= NOT clk17m; - END PROCESS p_clk_16m5; - - p_clk_12m5 : PROCESS - BEGIN - WAIT UNTIL rising_edge(clk25m); - clk13m <= NOT clk13m; - END PROCESS p_clk_12m5; - - clk_pixel_i <= clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' ELSE - clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' ELSE - clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' ELSE - clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' ELSE - clk25m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' ELSE - clk33m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' ELSE - clk25m WHEN fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "00" ELSE - clk33m WHEN fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" ELSE - clk_video WHEN fbee_video_on = '1' AND fbee_vctr(9) = '1' ELSE '0'; - - p_hsyn_len : PROCESS - -- Horizontal SYNC IN clk_pixel: - BEGIN - WAIT UNTIL rising_edge(clk_main); - IF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' THEN - hsync_len <= 8D"14"; - ELSIF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' THEN - hsync_len <= 8D"14"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' THEN - hsync_len <= 8D"16"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' THEN - hsync_len <= 8D"16"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' THEN - hsync_len <= 8D"28"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' THEN - hsync_len <= 8D"32"; - ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "00" THEN - hsync_len <= 8D"28"; - ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" THEN - hsync_len <= 8D"32"; - ELSIF fbee_video_on = '1' AND fbee_vctr(9) = '1' THEN - hsync_len <= 8D"16" + vr_frq / 2; -- hsync pulse length IN pixels = frequency/500ns. - ELSE - hsync_len <= x"00"; - END IF; - END PROCESS p_hsyn_len; - - mulf <= "000010" WHEN st_video = '0' AND vdl_vmd(2) = '1' ELSE -- Multiplier. - "000100" WHEN st_video = '0' AND vdl_vmd(2) = '0' ELSE - "010000" WHEN st_video = '1' AND vdl_vmd(2) = '1' ELSE - "100000" WHEN st_video = '1' AND vdl_vmd(2) = '0' ELSE "000000"; - - hdis_len <= x"140" WHEN vdl_vmd(2) = '1' ELSE x"280"; -- Width IN pixels (320 / 640). - - p_double_line_1 : PROCESS - BEGIN - WAIT UNTIL rising_edge(clk_main); - dop_zei <= vdl_vmd(0) AND st_video; -- Line doubling on off. - END PROCESS p_double_line_1; - - p_double_line_2 : PROCESS - BEGIN - WAIT UNTIL rising_edge(clk_pixel_i); - IF dop_zei = '1' AND vvcnt(0) /= vdis_start(0) AND vvcnt /= "00000000000" AND vhcnt < hdis_end - 1 THEN - inter_zei_i <= '1'; -- Switch insertion line to "double". Line zero due to SYNC. - ELSIF dop_zei = '1' AND vvcnt(0) = vdis_start(0) AND vvcnt /= "00000000000" AND vhcnt > hdis_end - 10 THEN - inter_zei_i <= '1'; -- Switch insertion mode to "normal". Lines AND line zero due to SYNC. - ELSE - inter_zei_i <= '0'; - END IF; - -- - dop_fifo_clr <= inter_zei_i AND hsync_start AND sync_pix; -- Double line info erase at the END of a double line AND at main FIFO start. - END PROCESS p_double_line_2; - - -- The following multiplications change every time the video resolution is changed. - mul1 <= vdl_hbe * mulf(5 DOWNTO 1); - mul2 <= vdl_hht + 1 + vdl_hss * mulf(5 DOWNTO 1); - mul3 <= RESIZE(vdl_hht + 10 * mulf(5 DOWNTO 1), mul3'LENGTH); - - border_left <= vdl_hbe WHEN fbee_video_on = '1' ELSE - x"015" WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - x"02A" WHEN atari_sync = '1' ELSE mul1(16 DOWNTO 5); - hdis_start <= vdl_hdb WHEN fbee_video_on = '1' ELSE border_left + 1; - hdis_end <= VDL_HDE WHEN fbee_video_on = '1' ELSE border_left + hdis_len; - border_right <= vdl_hbb WHEN fbee_video_on = '1' ELSE hdis_end + 1; - hs_start <= vdl_hss WHEN fbee_video_on = '1' ELSE - atari_hl(11 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_hh(11 DOWNTO 0) WHEN vdl_vmd(2) = '1' ELSE mul2(16 DOWNTO 5); - h_total <= vdl_hht WHEN fbee_video_on = '1' ELSE - atari_hl(27 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_hh(27 DOWNTO 16) WHEN atari_sync = '1' ELSE mul3(16 DOWNTO 5); - border_top <= vdl_vbe WHEN fbee_video_on = '1' ELSE - "00000011111" WHEN atari_sync = '1' ELSE '0' & vdl_vbe(10 DOWNTO 1); - vdis_start <= vdl_vdb WHEN fbee_video_on = '1' ELSE - "00000100000" WHEN atari_sync = '1' ELSE '0' & vdl_vdb(10 DOWNTO 1); - vdis_end <= vdl_vde WHEN fbee_video_on = '1' ELSE - "00110101111" WHEN atari_sync = '1' AND st_video = '1' ELSE -- 431. - "00111111111" WHEN atari_sync = '1' ELSE '0' & vdl_vde(10 DOWNTO 1); -- 511. - border_bottom <= vdl_vbb WHEN fbee_video_on = '1' ELSE - vdis_end + 1 WHEN atari_sync = '1' ELSE ('0' & vdl_vbb(10 DOWNTO 1) + 1); - vs_start <= vdl_vss WHEN fbee_video_on = '1' ELSE - atari_vl(10 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_vh(10 DOWNTO 0) WHEN atari_sync = '1' ELSE '0' & vdl_vss(10 DOWNTO 1); - v_total <= vdl_vft WHEN fbee_video_on = '1' ELSE - atari_vl(26 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_vh(26 DOWNTO 16) WHEN atari_sync = '1' ELSE '0' & vdl_vft(10 DOWNTO 1); - - last <= '1' WHEN vhcnt = h_total - 10 ELSE '0'; - - video_clock_domain : PROCESS - BEGIN - WAIT UNTIL rising_edge(clk_pixel_i); - IF st_clut = '1' THEN - ccsel <= "000"; -- For information only. - ELSIF falcon_clut = '1' THEN - ccsel <= "001"; - ELSIF fbee_clut = '1' THEN - ccsel <= "100"; - ELSIF color16_i = '1' THEN - ccsel <= "101"; - ELSIF color24_i = '1' THEN - ccsel <= "110"; - ELSIF border_on = '1' THEN - ccsel <= "111"; - END IF; - - IF last = '0' THEN - vhcnt <= vhcnt + 1; - ELSE - vhcnt <= (OTHERS => '0'); - END IF; - - IF last = '1' AND vvcnt = v_total - 1 THEN - vvcnt <= (OTHERS => '0'); - ELSIF last = '1' THEN - vvcnt <= vvcnt + 1; - END IF; - - -- Display on/off: - IF last = '1' AND vvcnt > border_top - 1 AND vvcnt < border_bottom - 1 THEN - dpo_zl <= '1'; - ELSIF last = '1' THEN - dpo_zl <= '0'; - END IF; - - IF vhcnt = border_left THEN - dpo_on <= '1'; -- BESSER EINZELN WEGEN TIMING - ELSE - dpo_on <= '0'; - END IF; - - IF vhcnt = border_right - 1 THEN - dpo_off <= '1'; - ELSE - dpo_off <= '0'; - END IF; - - disp_on <= (disp_on AND NOT dpo_off) or (dpo_on AND dpo_zl); - - -- Data transfer on/off: - IF vhcnt = hdis_start - 1 THEN - vdo_on <= '1'; -- BESSER EINZELN WEGEN TIMING. - ELSE - vdo_on <= '0'; - END IF; - - IF vhcnt = hdis_end THEN - vdo_off <= '1'; - ELSE - vdo_off <= '0'; - END IF; - - IF last = '1' AND vvcnt >= vdis_start - 1 AND vvcnt < vdis_end THEN - vdo_zl <= '1'; -- Take over at the END of the line. - ELSIF last = '1' THEN - vdo_zl <= '0'; -- 1 ZEILE DAVOR ON OFF - END IF; - - vdtron <= (vdtron AND NOT vdo_off) or (vdo_on AND vdo_zl); - - -- Delay AND SYNC - IF vhcnt = hs_start - 11 THEN - hsync_start <= '1'; - ELSE - hsync_start <= '0'; - END IF; - - IF hsync_start = '1' THEN - hsync_i <= hsync_len; - ELSIF hsync_i > x"00" THEN - hsync_i <= hsync_i - 1; - END IF; - - IF last = '1' AND vvcnt = vs_start - 11 THEN - vsync_start <= '1'; -- start am ende der Zeile vor dem vsync - ELSE - vsync_start <= '0'; - END IF; - - IF last = '1' AND vsync_start = '1' THEN -- Start at the END of the line before vsync. - vsync_i <= "011"; -- 3 lines vsync length. - ELSIF last = '1' AND vsync_i > "000" THEN - vsync_i <= vsync_i - 1; -- Count down. - END IF; - - IF fbee_vctr(15) = '1' AND vdl_vct(5) = '1' AND vsync_i = "000" THEN - verz_2 <= verz_2(8 DOWNTO 0) & '1'; - ELSIF (fbee_vctr(15) = '0' or vdl_vct(5) = '0') AND vsync_i /= "000" THEN - verz_2 <= verz_2(8 DOWNTO 0) & '1'; - ELSE - verz_2 <= verz_2(8 DOWNTO 0) & '0'; - END IF; - - IF hsync_i > x"00" THEN - verz_1 <= verz_1(8 DOWNTO 0) & '1'; - ELSE - verz_1 <= verz_1(8 DOWNTO 0) & '0'; - END IF; - - verz_0 <= verz_0(8 DOWNTO 0) & disp_on; - - blank_n <= verz_0(8); - hsync <= verz_1(9); - vsync <= verz_2(9); - sync_n <= NOT(verz_2(9) or verz_1(9)); - - -- border colours: - border <= border(5 DOWNTO 0) & (disp_on AND NOT vdtron AND fbee_vctr(25)); - border_on <= border(6); - - IF last = '1' AND vvcnt = v_total - 10 THEN - fifo_clr <= '1'; - ELSIF last = '1' THEN - fifo_clr <= '0'; - END IF; - - IF last = '1' AND vvcnt = "00000000000" THEN - start_zeile <= '1'; - ELSIF last = '1' THEN - start_zeile <= '0'; - END IF; - - IF vhcnt = x"003" AND start_zeile = '1' THEN - sync_pix <= '1'; - ELSE - sync_pix <= '0'; - END IF; - - IF vhcnt = x"005" AND start_zeile = '1' THEN - sync_pix1 <= '1'; - ELSE - sync_pix1 <= '0'; - END IF; - - IF vhcnt = x"007" AND start_zeile = '1' THEN - sync_pix2 <= '1'; - ELSE - sync_pix2 <= '0'; - END IF; - - IF vdtron = '1' AND sync_pix = '0' THEN - sub_pixel_cnt <= sub_pixel_cnt + 1; - ELSIF vdtron = '1' THEN - sub_pixel_cnt <= (OTHERS => '0'); - END IF; - - IF vdtron = '1' AND sub_pixel_cnt(6 DOWNTO 0) = "0000001" AND color1_i = '1' THEN - fifo_rde <= '1'; - ELSIF vdtron = '1' AND sub_pixel_cnt(5 DOWNTO 0) = "000001" AND color2_i = '1' THEN - fifo_rde <= '1'; - ELSIF vdtron = '1' AND sub_pixel_cnt(4 DOWNTO 0) = "00001" AND color4_i = '1' THEN - fifo_rde <= '1'; - ELSIF vdtron = '1' AND sub_pixel_cnt(3 DOWNTO 0) = "0001" AND color8_i = '1' THEN - fifo_rde <= '1'; - ELSIF vdtron = '1' AND sub_pixel_cnt(2 DOWNTO 0) = "001" AND color16_i = '1' THEN - fifo_rde <= '1'; - ELSIF vdtron = '1' AND sub_pixel_cnt(1 DOWNTO 0) = "01" AND color24_i = '1' THEN - fifo_rde <= '1'; - ELSIF sync_pix = '1' or sync_pix1 = '1' or sync_pix2 = '1' THEN - fifo_rde <= '1'; -- 3 CLOCK ZUS�TZLICH F�R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION - ELSE - fifo_rde <= '0'; - END IF; - - clut_mux_av_0 <= sub_pixel_cnt(3 DOWNTO 0); - clut_mux_av_1 <= clut_mux_av_0; - clut_mux_adr <= clut_mux_av_1; - END PROCESS video_clock_domain; -END ARCHITECTURE behaviour; +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- +---- ---- +---- Description: ---- +---- This design unit provides the video controller of the 'Fire- ---- +---- bee' computer. It is optimized for the use of an Altera Cyc- ---- +---- lone FPGA (EP3C40F484). This IP-Core is based on the first ---- +---- edition of the Firebee configware originally provided by ---- +---- Fredi Ashwanden AND Wolfgang Förster. This release is IN ---- +---- comparision to the first edition completely written IN VHDL. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- AND/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed IN the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; IF NOT, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K12B 20120801 WF +-- Initial Release of the second edition. + +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + +ENTITY video_ctrl IS + PORT( + clk_main : IN std_logic; + fb_cs_n : IN std_logic_vector(2 DOWNTO 1); + fb_wr_n : IN std_logic; + fb_oe_n : IN std_logic; + fb_size : IN std_logic_vector(1 DOWNTO 0); + fb_adr : IN std_logic_vector(31 DOWNTO 0); + clk33m : IN std_logic; + clk25m : IN std_logic; + blitter_run : IN std_logic; + clk_video : IN std_logic; + vr_d : IN unsigned(8 DOWNTO 0); + vr_busy : IN std_logic; + color8 : OUT std_logic; + fbee_clut_rd : OUT std_logic; + COLOR1 : OUT std_logic; + falcon_clut_rdh : OUT std_logic; + falcon_clut_rdl : OUT std_logic; + falcon_clut_wr : OUT unsigned(3 DOWNTO 0); + clut_st_rd : OUT std_logic; + clut_st_wr : OUT unsigned(1 DOWNTO 0); + clut_mux_adr : OUT unsigned(3 DOWNTO 0); + hsync : OUT std_logic; + vsync : OUT std_logic; + blank_n : OUT std_logic; + sync_n : OUT std_logic; + pd_vga_n : OUT std_logic; + fifo_rde : OUT std_logic; + color2 : OUT std_logic; + color4 : OUT std_logic; + clk_pixel : OUT std_logic; + clut_off : OUT unsigned(3 DOWNTO 0); + blitter_on : OUT std_logic; + video_ram_ctr : OUT unsigned(15 DOWNTO 0); + video_mod_ta : OUT std_logic; + ccr : OUT unsigned(23 DOWNTO 0); + ccsel : OUT unsigned(2 DOWNTO 0); + fbee_clut_wr : OUT unsigned(3 DOWNTO 0); + inter_zei : OUT std_logic; + dop_fifo_clr : OUT std_logic; + video_reconfig : OUT std_logic; + vr_wr : OUT std_logic; + vr_rd : OUT std_logic; + fifo_clr : OUT std_logic; + data_in : IN unsigned(31 DOWNTO 0); + data_out : OUT unsigned(31 DOWNTO 0); + data_en_h : OUT std_logic; + data_en_l : OUT std_logic + ); +END ENTITY video_ctrl; + +ARCHITECTURE behaviour OF video_ctrl IS + SIGNAL clk17m : std_logic; + SIGNAL clk13m : std_logic; + SIGNAL fbee_clut_cs : std_logic; + SIGNAL fbee_clut : std_logic; + SIGNAL video_pll_config_cs : std_logic; + SIGNAL vr_wr_i : std_logic; + SIGNAL vr_dout : unsigned(8 DOWNTO 0); + SIGNAL vr_frq : unsigned(7 DOWNTO 0); + SIGNAL video_pll_reconfig_cs : std_logic; + SIGNAL video_reconfig_i : std_logic; + SIGNAL falcon_clut_cs : std_logic; + SIGNAL falcon_clut : std_logic; + SIGNAL st_clut_cs : std_logic; + SIGNAL st_clut : std_logic; + SIGNAL fb_b : unsigned(3 DOWNTO 0); + SIGNAL fb_16b : unsigned(1 DOWNTO 0); + SIGNAL st_shift_mode : unsigned(1 DOWNTO 0); + SIGNAL st_shift_mode_cs : std_logic; + SIGNAL falcon_shift_mode : unsigned(10 DOWNTO 0); + SIGNAL falcon_shift_mode_cs : std_logic; + SIGNAL clut_mux_av_1 : unsigned(3 DOWNTO 0); + SIGNAL clut_mux_av_0 : unsigned(3 DOWNTO 0); + SIGNAL fbee_vctr_cs : std_logic; + SIGNAL fbee_vctr : unsigned(31 DOWNTO 0); + SIGNAL ccr_cs : std_logic; + SIGNAL ccr_i : unsigned(23 DOWNTO 0); + SIGNAL fbee_video_on : std_logic; + SIGNAL sys_ctr : unsigned(6 DOWNTO 0); + SIGNAL sys_ctr_cs : std_logic; + SIGNAL vdl_lof : unsigned(15 DOWNTO 0); + SIGNAL vdl_lof_cs : std_logic; + SIGNAL VDL_LWD : unsigned(15 DOWNTO 0); + SIGNAL VDL_LWD_CS : std_logic; + + -- Miscellaneous control registers: + SIGNAL clut_ta : std_logic; -- Requires one wait state. + SIGNAL hsync_i : unsigned(7 DOWNTO 0); + SIGNAL hsync_len : unsigned(7 DOWNTO 0); -- Length of a hsync pulse IN clk_pixel cycles. + SIGNAL hsync_start : std_logic; + SIGNAL last : std_logic; -- Last pixel of a line indicator. + SIGNAL vsync_start : std_logic; + SIGNAL vsync_i : unsigned(2 DOWNTO 0); + SIGNAL blank_i_n : std_logic; + SIGNAL disp_on : std_logic; + SIGNAL dpo_zl : std_logic; + SIGNAL dpo_on : std_logic; + SIGNAL dpo_off : std_logic; + SIGNAL vdtron : std_logic; + SIGNAL vdo_zl : std_logic; + SIGNAL vdo_on : std_logic; + SIGNAL vdo_off : std_logic; + SIGNAL vhcnt : unsigned(11 DOWNTO 0); + SIGNAL sub_pixel_cnt : unsigned(6 DOWNTO 0); + SIGNAL vvcnt : unsigned(10 DOWNTO 0); + SIGNAL verz_2 : unsigned(9 DOWNTO 0); + SIGNAL verz_1 : unsigned(9 DOWNTO 0); + SIGNAL verz_0 : unsigned(9 DOWNTO 0); + SIGNAL border : unsigned(6 DOWNTO 0); + SIGNAL border_on : std_logic; + SIGNAL start_zeile : std_logic; + SIGNAL sync_pix : std_logic; + SIGNAL sync_pix1 : std_logic; + SIGNAL sync_pix2 : std_logic; + + -- Legacy ATARI resolutions: + SIGNAL atari_sync : std_logic; + SIGNAL atari_hh : unsigned(31 DOWNTO 0); -- Horizontal timing 640x480. + SIGNAL atari_hh_cs : std_logic; + SIGNAL atari_vh : unsigned(31 DOWNTO 0); -- Vertical timing 640x480. + SIGNAL atari_vh_cs : std_logic; + SIGNAL atari_hl : unsigned(31 DOWNTO 0); -- Horizontal timing 320x240. + SIGNAL atari_hl_cs : std_logic; + SIGNAL atari_vl : unsigned(31 DOWNTO 0); -- Vertical timing 320x240. + SIGNAL atari_vl_cs : std_logic; + + -- Horizontal stuff: + SIGNAL border_left : unsigned(11 DOWNTO 0); + SIGNAL hdis_start : unsigned(11 DOWNTO 0); + SIGNAL hdis_end : unsigned(11 DOWNTO 0); + SIGNAL border_right : unsigned(11 DOWNTO 0); + SIGNAL hs_start : unsigned(11 DOWNTO 0); + SIGNAL h_total : unsigned(11 DOWNTO 0); + SIGNAL hdis_len : unsigned(11 DOWNTO 0); + SIGNAL mulf : unsigned(5 DOWNTO 0); + SIGNAL vdl_hht : unsigned(11 DOWNTO 0); + SIGNAL vdl_hht_cs : std_logic; + SIGNAL vdl_hbe : unsigned(11 DOWNTO 0); + SIGNAL vdl_hbe_cs : std_logic; + SIGNAL vdl_hdb : unsigned(11 DOWNTO 0); + SIGNAL vdl_hdb_cs : std_logic; + SIGNAL VDL_HDE : unsigned(11 DOWNTO 0); + SIGNAL vdl_hde_cs : std_logic; + SIGNAL vdl_hbb : unsigned(11 DOWNTO 0); + SIGNAL vdl_hbb_cs : std_logic; + SIGNAL vdl_hss : unsigned(11 DOWNTO 0); + SIGNAL vdl_hss_cs : std_logic; + + -- Vertical stuff: + SIGNAL border_top : unsigned(10 DOWNTO 0); + SIGNAL vdis_start : unsigned(10 DOWNTO 0); + SIGNAL vdis_end : unsigned(10 DOWNTO 0); + SIGNAL border_bottom : unsigned(10 DOWNTO 0); + SIGNAL vs_start : unsigned(10 DOWNTO 0); + SIGNAL v_total : unsigned(10 DOWNTO 0); + SIGNAL falcon_video : std_logic; + SIGNAL st_video : std_logic; + SIGNAL inter_zei_i : std_logic; + SIGNAL dop_zei : std_logic; + + SIGNAL vdl_vbe : unsigned(10 DOWNTO 0); + SIGNAL vdl_vbe_cs : std_logic; + SIGNAL vdl_vdb : unsigned(10 DOWNTO 0); + SIGNAL VDL_VDB_CS : std_logic; + SIGNAL vdl_vde : unsigned(10 DOWNTO 0); + SIGNAL vdl_vde_cs : std_logic; + SIGNAL vdl_vbb : unsigned(10 DOWNTO 0); + SIGNAL vdl_vbb_cs : std_logic; + SIGNAL vdl_vss : unsigned(10 DOWNTO 0); + SIGNAL vdl_vss_cs : std_logic; + SIGNAL vdl_vft : unsigned(10 DOWNTO 0); + SIGNAL vdl_vft_cs : std_logic; + SIGNAL vdl_vct : unsigned(8 DOWNTO 0); + SIGNAL vdl_vct_cs : std_logic; + SIGNAL vdl_vmd : unsigned(3 DOWNTO 0); + SIGNAL vdl_vmd_cs : std_logic; + SIGNAL color1_i : std_logic; + SIGNAL color2_i : std_logic; + SIGNAL color4_i : std_logic; + SIGNAL color8_i : std_logic; + SIGNAL color16_i : std_logic; + SIGNAL color24_i : std_logic; + SIGNAL video_mod_ta_i : std_logic; + SIGNAL vr_rd_i : std_logic; + SIGNAL clk_pixel_i : std_logic; + SIGNAL mul1 : unsigned(16 DOWNTO 0); + SIGNAL mul2 : unsigned(16 DOWNTO 0); + SIGNAL mul3 : unsigned(16 DOWNTO 0) := (OTHERS => 'Z'); +BEGIN + vr_wr <= vr_wr_i; + video_reconfig <= video_reconfig_i; + ccr <= ccr_i; + inter_zei <= inter_zei_i; + video_mod_ta <= video_mod_ta_i; + vr_rd <= vr_rd_i; + clk_pixel <= clk_pixel_i; + + -- Byte selectors: + fb_b(0) <= '1' WHEN fb_adr(1 DOWNTO 0) = "00" ELSE '0'; -- Byte 0. + + fb_b(1) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '0' ELSE -- High word. + '1' WHEN fb_adr(1 DOWNTO 0) = "01" ELSE '0'; -- Byte 1. + + fb_b(2) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. + '1' WHEN fb_adr(1 DOWNTO 0) = "10" ELSE '0'; -- Byte 2. + + fb_b(3) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '1' ELSE -- Low word. + '1' WHEN fb_adr(1 DOWNTO 0) = "11" ELSE '0'; -- Byte 3. + + -- 16 bit selectors: + fb_16b(0) <= NOT fb_adr(0); + fb_16b(1) <= '1'WHEN fb_adr(0) = '1' ELSE + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- No byte. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' ELSE -- No byte. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE '0'; -- No byte. + + -- Firebee CLUT: + fbee_clut_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 10) = "000000000000000000" ELSE '0'; -- 0-3FF/1024 + fbee_clut_rd <= '1' WHEN fbee_clut_cs = '1' AND fb_oe_n = '0' ELSE '0'; + fbee_clut_wr <= fb_b WHEN fbee_clut_cs = '1' AND fb_wr_n = '0' ELSE x"0"; + + p_clut_ta : PROCESS + BEGIN + WAIT UNTIL clk_main = '1' AND clk_main' EVENT; + IF video_mod_ta_i = '0' AND fbee_clut_cs = '1' THEN + clut_ta <= '1'; + ELSIF video_mod_ta_i = '0' AND falcon_clut_cs = '1' THEN + clut_ta <= '1'; + ELSIF video_mod_ta_i = '0' AND st_clut_cs = '1' THEN + clut_ta <= '1'; + ELSE + clut_ta <= '0'; + END IF; + END PROCESS p_clut_ta; + + --Falcon CLUT: + falcon_clut_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 10) = "1111100110" ELSE '0'; -- $F9800/$400 + falcon_clut_rdh <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '0' ELSE '0'; -- High word. + falcon_clut_rdl <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '1' ELSE '0'; -- Low word. + falcon_clut_wr(1 DOWNTO 0) <= fb_16b WHEN fb_adr(1) = '0' AND falcon_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; + falcon_clut_wr(3 DOWNTO 2) <= fb_16b WHEN fb_adr(1) = '1' AND falcon_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; + + -- ST CLUT: + st_clut_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 5) = "111110000010010" ELSE '0'; -- $F8240/$2 + clut_st_rd <= '1' WHEN st_clut_cs = '1' AND fb_oe_n = '0' ELSE '0'; + clut_st_wr <= fb_16b WHEN st_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; + + st_shift_mode_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 1) = "1111100000100110000" ELSE '0'; -- $F8260/$2. + falcon_shift_mode_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 1) = "1111100000100110011" ELSE '0'; -- $F8266/$2. + fbee_vctr_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000000" ELSE '0'; -- $400/$4 + atari_hh_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000100" ELSE '0'; -- $410/4 + atari_vh_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000101" ELSE '0'; -- $414/4 + atari_hl_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000110" ELSE '0'; -- $418/4 + atari_vl_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000000000100000111" ELSE '0'; -- $41C/4 + + p_video_control : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk_main); + IF st_shift_mode_cs = '1' AND fb_wr_n = '0' AND fb_b(0) = '1' THEN + st_shift_mode <= data_in(25 DOWNTO 24); + END IF; + + IF falcon_shift_mode_cs = '1' AND fb_wr_n = '0' AND fb_b(2) = '1' THEN + falcon_shift_mode(10 DOWNTO 8) <= data_in(26 DOWNTO 24); + ELSIF falcon_shift_mode_cs = '1' AND fb_wr_n = '0' AND fb_b(3) = '1' THEN + falcon_shift_mode(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- Firebee VIDEO CONTROL: + -- Bit 0 = FBEE VIDEO ON, 1 = POWER ON VIDEO DAC, 2 = FBEE 24BIT, + -- Bit 3 = FBEE 16BIT, 4 = FBEE 8BIT, 5 = FBEE 1BIT, + -- Bit 6 = FALCON SHIFT MODE, 7 = ST SHIFT MODE, 9..8 = VCLK frequency, + -- Bit 15 = SYNC ALLOWED, 31..16 = video_ram_ctr, + -- Bit 25 = RANDFARBE EINSCHALTEN, 26 = STANDARD ATARI SYNCS. + IF fbee_vctr_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + fbee_vctr(31 DOWNTO 24) <= data_in(31 DOWNTO 24); + ELSIF fbee_vctr_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + fbee_vctr(23 DOWNTO 16) <= data_in(23 DOWNTO 16); + ELSIF fbee_vctr_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + fbee_vctr(15 DOWNTO 8) <= data_in(15 DOWNTO 8); + ELSIF fbee_vctr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + fbee_vctr(5 DOWNTO 0) <= data_in(5 DOWNTO 0); + END IF; + + -- ST or Falcon shift mode: assert WHEN X..shift register: + IF falcon_shift_mode_cs = '1' AND fb_wr_n = '0' THEN + fbee_vctr(7) <= falcon_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; + fbee_vctr(6) <= st_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; + END IF; + IF st_shift_mode_cs = '1' AND fb_wr_n = '0' THEN + fbee_vctr(7) <= falcon_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; + fbee_vctr(6) <= st_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; + END IF; + IF fbee_vctr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' AND data_in(0) = '1' THEN + fbee_vctr(7) <= falcon_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; + fbee_vctr(6) <= st_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; + END IF; + + -- ATARI ST mode + -- Horizontal timing 640x480: + IF atari_hh_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + atari_hh(31 DOWNTO 24) <= data_in(31 DOWNTO 24); + ELSIF atari_hh_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + atari_hh(23 DOWNTO 16) <= data_in(23 DOWNTO 16); + ELSIF atari_hh_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + atari_hh(15 DOWNTO 8) <= data_in(15 DOWNTO 8); + ELSIF atari_hh_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + atari_hh(7 DOWNTO 0) <= data_in(7 DOWNTO 0); + END IF; + + -- Vertical timing 640x480: + IF atari_vh_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + atari_vh(31 DOWNTO 24) <= data_in(31 DOWNTO 24); + ELSIF atari_vh_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + atari_vh(23 DOWNTO 16) <= data_in(23 DOWNTO 16); + ELSIF atari_vh_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + atari_vh(15 DOWNTO 8) <= data_in(15 DOWNTO 8); + ELSIF atari_vh_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + atari_vh(7 DOWNTO 0) <= data_in(7 DOWNTO 0); + END IF; + + -- Horizontal timing 320x240: + IF atari_hl_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + atari_hl(31 DOWNTO 24) <= data_in(31 DOWNTO 24); + ELSIF atari_hl_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + atari_hl(23 DOWNTO 16) <= data_in(23 DOWNTO 16); + ELSIF atari_hl_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + atari_hl(15 DOWNTO 8) <= data_in(15 DOWNTO 8); + ELSIF atari_hl_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + atari_hl(7 DOWNTO 0) <= data_in(7 DOWNTO 0); + END IF; + + -- Vertical timing 320x240: + IF atari_vl_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + atari_vl(31 DOWNTO 24) <= data_in(31 DOWNTO 24); + ELSIF atari_vl_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + atari_vl(23 DOWNTO 16) <= data_in(23 DOWNTO 16); + ELSIF atari_vl_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + atari_vl(15 DOWNTO 8) <= data_in(15 DOWNTO 8); + ELSIF atari_vl_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + atari_vl(7 DOWNTO 0) <= data_in(7 DOWNTO 0); + END IF; + END PROCESS p_video_control; + + clut_off <= falcon_shift_mode(3 DOWNTO 0) WHEN color4_i = '1' ELSE x"0"; + pd_vga_n <= fbee_vctr(1); + fbee_video_on <= fbee_vctr(0); + atari_sync <= fbee_vctr(26); -- If 1 -> automatic resolution. + + color1_i <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND st_shift_mode = "10" AND color8_i = '0' ELSE -- ST mono. + '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND falcon_shift_mode(10) = '1' AND color16_i = '0' AND color8_i = '0' ELSE -- Falcon mono. + '1' WHEN fbee_video_on = '1' AND fbee_vctr(5 DOWNTO 2) = "1000" ELSE '0'; -- Firebee mode. + color2_i <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND st_shift_mode = "01" AND color8_i = '0' ELSE '0'; -- ST 4 colours. + color4_i <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND st_shift_mode = "00" AND color8_i = '0' ELSE -- ST 16 colours. + '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND color16_i = '0' AND color8_i = '0' AND color1_i = '0' ELSE '0'; -- Falcon mode. + color8_i <= '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND falcon_shift_mode(4) = '1' AND color16_i = '0' ELSE -- Falcon mode. + '1' WHEN fbee_video_on = '1' AND fbee_vctr(4 DOWNTO 2) = "100" ELSE '0'; -- Firebee mode. + color16_i <= '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND falcon_shift_mode(8) = '1' ELSE -- Falcon mode. + '1' WHEN fbee_video_on = '1' AND fbee_vctr(3 DOWNTO 2) = "10" ELSE '0'; -- Firebee mode. + color24_i <= '1' WHEN fbee_video_on = '1' AND fbee_vctr(2) = '1' ELSE '0'; -- Firebee mode. + + COLOR1 <= color1_i; + color2 <= color2_i; + color4 <= color4_i; + color8 <= color8_i; + + -- VIDEO PLL config AND reconfig: + video_pll_config_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_b(0) = '1' AND fb_b(1) = '1' AND fb_adr(27 DOWNTO 9) = "0000000000000000011" ELSE '0'; -- $(F)000'0600-7FF -> 6/2 word AND long only. + video_pll_reconfig_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_b(0) = '1' AND fb_adr(27 DOWNTO 0) = x"0000800" ELSE '0'; -- $(F)000'0800. + vr_rd_i <= '1' WHEN video_pll_config_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' ELSE '0'; + + p_video_config: PROCESS + variable lock : boolean; + BEGIN + WAIT UNTIL rising_edge(clk_main); + + IF video_pll_config_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' AND vr_wr_i = '0' THEN + vr_wr_i <= '1'; -- This is a strobe. + ELSE + vr_wr_i <= '0'; + END IF; + + IF vr_busy = '1' THEN + vr_dout <= vr_d; + END IF; + + IF vr_wr_i = '1' AND fb_adr(8 DOWNTO 0) = "000000100" THEN + vr_frq <= data_in(23 DOWNTO 16); + END IF; + + IF video_pll_reconfig_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' AND lock = false THEN + video_reconfig_i <= '1'; -- This is a strobe. + lock := true; + ELSIF video_pll_reconfig_cs = '0' or fb_wr_n = '1' or vr_busy = '1' THEN + video_reconfig_i <= '0'; + lock := false; + ELSE + video_reconfig_i <= '0'; + END IF; + END PROCESS p_video_config; + + video_ram_ctr <= fbee_vctr(31 DOWNTO 16); + + -- Firebee colour modi: + fbee_clut <= '1' WHEN fbee_video_on = '1' AND (color1_i = '1' or color8_i = '1') ELSE + '1' WHEN st_video = '1' AND color1_i = '1'; + + falcon_video <= fbee_vctr(7); + falcon_clut <= '1' WHEN falcon_video = '1' AND fbee_video_on = '0' AND color16_i = '0' ELSE '0'; + st_video <= fbee_vctr(6); + st_clut <= '1' WHEN st_video = '1' AND fbee_video_on = '0' AND falcon_clut = '0' AND color1_i = '0' ELSE '0'; + + -- Several (video)-registers: + ccr_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr = x"f0000404" ELSE '0'; -- $F0000404 - Firebee video border color + sys_ctr_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8008" ELSE '0'; -- $FF8006 - Falcon monitor type register + vdl_lof_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff820e" ELSE '0'; -- $FF820E/F - line-width hi/lo. + VDL_LWD_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8210" ELSE '0'; -- $FF8210/1 - vertical wrap hi/lo. + vdl_hht_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8282" ELSE '0'; -- $FF8282/3 - horizontal hold timer hi/lo. + vdl_hbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8286" ELSE '0'; -- $FF8286/7 - horizontal border END hi/lo. + vdl_hdb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8288" ELSE '0'; -- $FF8288/9 - horizontal display BEGIN hi/lo. + vdl_hde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828a" ELSE '0'; -- $FF828A/B - horizontal display END hi/lo. + vdl_hbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8284" ELSE '0'; -- $FF8284/5 - horizontal border BEGIN hi/lo. + vdl_hss_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828c" ELSE '0'; -- $FF828C/D - position hsync (HSS). + vdl_vft_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a2" ELSE '0'; -- $FF82A2/3 - video frequency timer (VFT). + vdl_vbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a4" ELSE '0'; -- $FF82A4/5 - vertical blank on (IN half line steps). + vdl_vbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a6" ELSE '0'; -- $FF82A6/7 - vertical blank off (IN half line steps). + VDL_VDB_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a8" ELSE '0'; -- $FF82A8/9 - vertical display BEGIN (VDB). + vdl_vde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82aa" ELSE '0'; -- $FF82AA/B - vertical display END (VDE). + vdl_vss_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82ac" ELSE '0'; -- $FF82AC/D - position vsync (VSS). + vdl_vct_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82c0" ELSE '0'; -- $FF82C0/1 - clock control (VCO). + vdl_vmd_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82c2" ELSE '0'; -- $FF82C2/3 - resolution control. + + p_misc_ctrl : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk_main); + + -- Colour of video borders + IF ccr_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + ccr_i(23 DOWNTO 16) <= data_in(23 DOWNTO 16); + ELSIF ccr_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + ccr_i(15 DOWNTO 8) <= data_in(15 DOWNTO 8); + ELSIF ccr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + ccr_i(7 DOWNTO 0) <= data_in(7 DOWNTO 0); + END IF; + + -- SYS CTRL: + IF sys_ctr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + sys_ctr <= data_in(22 DOWNTO 16); + END IF; + + --vdl_lof: + IF vdl_lof_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + vdl_lof(15 DOWNTO 8) <= data_in(31 DOWNTO 24); + ELSIF vdl_lof_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + vdl_lof(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + --VDL_LWD + IF VDL_LWD_CS = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + VDL_LWD(15 DOWNTO 8) <= data_in(31 DOWNTO 24); + ELSIF VDL_LWD_CS = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + VDL_LWD(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- Horizontal: + -- vdl_hht: + IF vdl_hht_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + vdl_hht(11 DOWNTO 8) <= data_in(27 DOWNTO 24); + ELSIF vdl_hht_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + vdl_hht(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_hbe: + IF vdl_hbe_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + vdl_hbe(11 DOWNTO 8) <= data_in(27 DOWNTO 24); + ELSIF vdl_hbe_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + vdl_hbe(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_hdb: + IF vdl_hdb_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_hdb(11 DOWNTO 8) <= data_in(27 DOWNTO 24); + ELSIF vdl_hdb_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_hdb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- VDL_HDE: + IF vdl_hde_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + VDL_HDE(11 DOWNTO 8) <= data_in(27 DOWNTO 24); + ELSIF vdl_hde_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + VDL_HDE(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_hbb: + IF vdl_hbb_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_hbb(11 DOWNTO 8) <= data_in(27 DOWNTO 24); + ELSIF vdl_hbb_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_hbb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_hss: + IF vdl_hss_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_hss(11 DOWNTO 8) <= data_in(27 DOWNTO 24); + ELSIF vdl_hss_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_hss(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- Vertical: + -- vdl_vbe: + IF vdl_vbe_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + vdl_vbe(10 DOWNTO 8) <= data_in(26 DOWNTO 24); + ELSIF vdl_vbe_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + vdl_vbe(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_vdb: + IF VDL_VDB_CS = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_vdb(10 DOWNTO 8) <= data_in(26 DOWNTO 24); + ELSIF VDL_VDB_CS = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_vdb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_vde: + IF vdl_vde_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + vdl_vde(10 DOWNTO 8) <= data_in(26 DOWNTO 24); + ELSIF vdl_vde_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + vdl_vde(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_vbb: + IF vdl_vbb_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_vbb(10 DOWNTO 8) <= data_in(26 DOWNTO 24); + ELSIF vdl_vbb_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_vbb(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_vss + IF vdl_vss_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_vss(10 DOWNTO 8) <= data_in(26 DOWNTO 24); + ELSIF vdl_vss_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_vss(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_vft + IF vdl_vft_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + vdl_vft(10 DOWNTO 8) <= data_in(26 DOWNTO 24); + ELSIF vdl_vft_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + vdl_vft(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_vct(2): 1 = 32MHz clk_pixel, 0 = 25MHZ; vdl_vct(0): 1 = linedoubling. + IF vdl_vct_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_vct(8) <= data_in(24); + ELSIF vdl_vct_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_vct(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + END IF; + + -- vdl_vmd(2): 1 = clk_pixel/2. + IF vdl_vmd_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + vdl_vmd <= data_in(19 DOWNTO 16); + END IF; + END PROCESS p_misc_ctrl; + + blitter_on <= NOT sys_ctr(3); + + -- Register OUT: + data_out(31 DOWNTO 16) <= "000000" & st_shift_mode & x"00" WHEN st_shift_mode_cs = '1' ELSE + "00000" & falcon_shift_mode WHEN falcon_shift_mode_cs = '1' ELSE + "100000000" & sys_ctr(6 DOWNTO 4) & NOT blitter_run & sys_ctr(2 DOWNTO 0) WHEN sys_ctr_cs = '1' ELSE + vdl_lof WHEN vdl_lof_cs = '1' ELSE + VDL_LWD WHEN VDL_LWD_CS = '1' ELSE + x"0" & vdl_hbe WHEN vdl_hbe_cs = '1' ELSE + x"0" & vdl_hdb WHEN vdl_hdb_cs = '1' ELSE + x"0" & VDL_HDE WHEN vdl_hde_cs = '1' ELSE + x"0" & vdl_hbb WHEN vdl_hbb_cs = '1' ELSE + x"0" & vdl_hss WHEN vdl_hss_cs = '1' ELSE + x"0" & vdl_hht WHEN vdl_hht_cs = '1' ELSE + "00000" & vdl_vbe WHEN vdl_vbe_cs = '1' ELSE + "00000" & vdl_vdb WHEN VDL_VDB_CS = '1' ELSE + "00000" & vdl_vde WHEN vdl_vde_cs = '1' ELSE + "00000" & vdl_vbb WHEN vdl_vbb_cs = '1' ELSE + "00000" & vdl_vss WHEN vdl_vss_cs = '1' ELSE + "00000" & vdl_vft WHEN vdl_vft_cs = '1' ELSE + "0000000" & vdl_vct WHEN vdl_vct_cs = '1' ELSE + x"000" & vdl_vmd WHEN vdl_vmd_cs = '1' ELSE + fbee_vctr(31 DOWNTO 16) WHEN fbee_vctr_cs = '1' ELSE + atari_hh(31 DOWNTO 16) WHEN atari_hh_cs = '1' ELSE + atari_vh(31 DOWNTO 16) WHEN atari_vh_cs = '1' ELSE + atari_hl(31 DOWNTO 16) WHEN atari_hl_cs = '1' ELSE + atari_vl(31 DOWNTO 16) WHEN atari_vl_cs = '1' ELSE + x"00" & ccr_i(23 DOWNTO 16) WHEN ccr_cs = '1' ELSE + "0000000" & vr_dout WHEN video_pll_config_cs = '1' ELSE + vr_busy & "0000" & vr_wr_i & vr_rd_i & video_reconfig_i & x"FA" WHEN video_pll_reconfig_cs = '1' ELSE (OTHERS => '0'); + + data_out(15 DOWNTO 0) <= fbee_vctr(15 DOWNTO 0) WHEN fbee_vctr_cs = '1' ELSE + atari_hh(15 DOWNTO 0) WHEN atari_hh_cs = '1' ELSE + atari_vh(15 DOWNTO 0) WHEN atari_vh_cs = '1' ELSE + atari_hl(15 DOWNTO 0) WHEN atari_hl_cs = '1' ELSE + atari_vl(15 DOWNTO 0) WHEN atari_vl_cs = '1' ELSE + ccr_i(15 DOWNTO 0) WHEN ccr_cs = '1' ELSE (OTHERS => '0'); + + data_en_h <= (st_shift_mode_cs or falcon_shift_mode_cs or fbee_vctr_cs or ccr_cs or sys_ctr_cs or vdl_lof_cs or VDL_LWD_CS or + vdl_hbe_cs or vdl_hdb_cs or vdl_hde_cs or vdl_hbb_cs or vdl_hss_cs or vdl_hht_cs or + atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs or video_pll_config_cs or video_pll_reconfig_cs or + vdl_vbe_cs or VDL_VDB_CS or vdl_vde_cs or vdl_vbb_cs or vdl_vss_cs or vdl_vft_cs or vdl_vct_cs or vdl_vmd_cs) AND NOT fb_oe_n; + + data_en_l <= (fbee_vctr_cs or ccr_cs or atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs ) AND NOT fb_oe_n; + + video_mod_ta_i <= clut_ta or st_shift_mode_cs or falcon_shift_mode_cs or fbee_vctr_cs or sys_ctr_cs or vdl_lof_cs or VDL_LWD_CS or + vdl_hbe_cs or vdl_hdb_cs or vdl_hde_cs or vdl_hbb_cs or vdl_hss_cs or vdl_hht_cs or + atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs or + vdl_vbe_cs or VDL_VDB_CS or vdl_vde_cs or vdl_vbb_cs or vdl_vss_cs or vdl_vft_cs or vdl_vct_cs or vdl_vmd_cs; + + p_clk_16m5 : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk33m); + clk17m <= NOT clk17m; + END PROCESS p_clk_16m5; + + p_clk_12m5 : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk25m); + clk13m <= NOT clk13m; + END PROCESS p_clk_12m5; + + clk_pixel_i <= clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' ELSE + clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' ELSE + clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' ELSE + clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' ELSE + clk25m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' ELSE + clk33m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' ELSE + clk25m WHEN fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "00" ELSE + clk33m WHEN fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" ELSE + clk_video WHEN fbee_video_on = '1' AND fbee_vctr(9) = '1' ELSE '0'; + + p_hsyn_len : PROCESS + -- Horizontal SYNC IN clk_pixel: + BEGIN + WAIT UNTIL rising_edge(clk_main); + IF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' THEN + hsync_len <= 8D"14"; + ELSIF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' THEN + hsync_len <= 8D"14"; + ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' THEN + hsync_len <= 8D"16"; + ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' THEN + hsync_len <= 8D"16"; + ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' THEN + hsync_len <= 8D"28"; + ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' THEN + hsync_len <= 8D"32"; + ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "00" THEN + hsync_len <= 8D"28"; + ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" THEN + hsync_len <= 8D"32"; + ELSIF fbee_video_on = '1' AND fbee_vctr(9) = '1' THEN + hsync_len <= 8D"16" + vr_frq / 2; -- hsync pulse length IN pixels = frequency/500ns. + ELSE + hsync_len <= x"00"; + END IF; + END PROCESS p_hsyn_len; + + mulf <= "000010" WHEN st_video = '0' AND vdl_vmd(2) = '1' ELSE -- Multiplier. + "000100" WHEN st_video = '0' AND vdl_vmd(2) = '0' ELSE + "010000" WHEN st_video = '1' AND vdl_vmd(2) = '1' ELSE + "100000" WHEN st_video = '1' AND vdl_vmd(2) = '0' ELSE "000000"; + + hdis_len <= x"140" WHEN vdl_vmd(2) = '1' ELSE x"280"; -- Width IN pixels (320 / 640). + + p_double_line_1 : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk_main); + dop_zei <= vdl_vmd(0) AND st_video; -- Line doubling on off. + END PROCESS p_double_line_1; + + p_double_line_2 : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk_pixel_i); + IF dop_zei = '1' AND vvcnt(0) /= vdis_start(0) AND vvcnt /= "00000000000" AND vhcnt < hdis_end - 1 THEN + inter_zei_i <= '1'; -- Switch insertion line to "double". Line zero due to SYNC. + ELSIF dop_zei = '1' AND vvcnt(0) = vdis_start(0) AND vvcnt /= "00000000000" AND vhcnt > hdis_end - 10 THEN + inter_zei_i <= '1'; -- Switch insertion mode to "normal". Lines AND line zero due to SYNC. + ELSE + inter_zei_i <= '0'; + END IF; + -- + dop_fifo_clr <= inter_zei_i AND hsync_start AND sync_pix; -- Double line info erase at the END of a double line AND at main FIFO start. + END PROCESS p_double_line_2; + + -- The following multiplications change every time the video resolution is changed. + mul1 <= vdl_hbe * mulf(5 DOWNTO 1); + mul2 <= vdl_hht + 1 + vdl_hss * mulf(5 DOWNTO 1); + mul3 <= RESIZE(vdl_hht + 10 * mulf(5 DOWNTO 1), mul3'LENGTH); + + border_left <= vdl_hbe WHEN fbee_video_on = '1' ELSE + x"015" WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + x"02A" WHEN atari_sync = '1' ELSE mul1(16 DOWNTO 5); + hdis_start <= vdl_hdb WHEN fbee_video_on = '1' ELSE border_left + 1; + hdis_end <= VDL_HDE WHEN fbee_video_on = '1' ELSE border_left + hdis_len; + border_right <= vdl_hbb WHEN fbee_video_on = '1' ELSE hdis_end + 1; + hs_start <= vdl_hss WHEN fbee_video_on = '1' ELSE + atari_hl(11 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_hh(11 DOWNTO 0) WHEN vdl_vmd(2) = '1' ELSE mul2(16 DOWNTO 5); + h_total <= vdl_hht WHEN fbee_video_on = '1' ELSE + atari_hl(27 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_hh(27 DOWNTO 16) WHEN atari_sync = '1' ELSE mul3(16 DOWNTO 5); + border_top <= vdl_vbe WHEN fbee_video_on = '1' ELSE + "00000011111" WHEN atari_sync = '1' ELSE '0' & vdl_vbe(10 DOWNTO 1); + vdis_start <= vdl_vdb WHEN fbee_video_on = '1' ELSE + "00000100000" WHEN atari_sync = '1' ELSE '0' & vdl_vdb(10 DOWNTO 1); + vdis_end <= vdl_vde WHEN fbee_video_on = '1' ELSE + "00110101111" WHEN atari_sync = '1' AND st_video = '1' ELSE -- 431. + "00111111111" WHEN atari_sync = '1' ELSE '0' & vdl_vde(10 DOWNTO 1); -- 511. + border_bottom <= vdl_vbb WHEN fbee_video_on = '1' ELSE + vdis_end + 1 WHEN atari_sync = '1' ELSE ('0' & vdl_vbb(10 DOWNTO 1) + 1); + vs_start <= vdl_vss WHEN fbee_video_on = '1' ELSE + atari_vl(10 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_vh(10 DOWNTO 0) WHEN atari_sync = '1' ELSE '0' & vdl_vss(10 DOWNTO 1); + v_total <= vdl_vft WHEN fbee_video_on = '1' ELSE + atari_vl(26 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_vh(26 DOWNTO 16) WHEN atari_sync = '1' ELSE '0' & vdl_vft(10 DOWNTO 1); + + last <= '1' WHEN vhcnt = h_total - 10 ELSE '0'; + + video_clock_domain : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk_pixel_i); + IF st_clut = '1' THEN + ccsel <= "000"; -- For information only. + ELSIF falcon_clut = '1' THEN + ccsel <= "001"; + ELSIF fbee_clut = '1' THEN + ccsel <= "100"; + ELSIF color16_i = '1' THEN + ccsel <= "101"; + ELSIF color24_i = '1' THEN + ccsel <= "110"; + ELSIF border_on = '1' THEN + ccsel <= "111"; + END IF; + + IF last = '0' THEN + vhcnt <= vhcnt + 1; + ELSE + vhcnt <= (OTHERS => '0'); + END IF; + + IF last = '1' AND vvcnt = v_total - 1 THEN + vvcnt <= (OTHERS => '0'); + ELSIF last = '1' THEN + vvcnt <= vvcnt + 1; + END IF; + + -- Display on/off: + IF last = '1' AND vvcnt > border_top - 1 AND vvcnt < border_bottom - 1 THEN + dpo_zl <= '1'; + ELSIF last = '1' THEN + dpo_zl <= '0'; + END IF; + + IF vhcnt = border_left THEN + dpo_on <= '1'; -- BESSER EINZELN WEGEN TIMING + ELSE + dpo_on <= '0'; + END IF; + + IF vhcnt = border_right - 1 THEN + dpo_off <= '1'; + ELSE + dpo_off <= '0'; + END IF; + + disp_on <= (disp_on AND NOT dpo_off) or (dpo_on AND dpo_zl); + + -- Data transfer on/off: + IF vhcnt = hdis_start - 1 THEN + vdo_on <= '1'; -- BESSER EINZELN WEGEN TIMING. + ELSE + vdo_on <= '0'; + END IF; + + IF vhcnt = hdis_end THEN + vdo_off <= '1'; + ELSE + vdo_off <= '0'; + END IF; + + IF last = '1' AND vvcnt >= vdis_start - 1 AND vvcnt < vdis_end THEN + vdo_zl <= '1'; -- Take over at the END of the line. + ELSIF last = '1' THEN + vdo_zl <= '0'; -- 1 ZEILE DAVOR ON OFF + END IF; + + vdtron <= (vdtron AND NOT vdo_off) or (vdo_on AND vdo_zl); + + -- Delay AND SYNC + IF vhcnt = hs_start - 11 THEN + hsync_start <= '1'; + ELSE + hsync_start <= '0'; + END IF; + + IF hsync_start = '1' THEN + hsync_i <= hsync_len; + ELSIF hsync_i > x"00" THEN + hsync_i <= hsync_i - 1; + END IF; + + IF last = '1' AND vvcnt = vs_start - 11 THEN + vsync_start <= '1'; -- start am ende der Zeile vor dem vsync + ELSE + vsync_start <= '0'; + END IF; + + IF last = '1' AND vsync_start = '1' THEN -- Start at the END of the line before vsync. + vsync_i <= "011"; -- 3 lines vsync length. + ELSIF last = '1' AND vsync_i > "000" THEN + vsync_i <= vsync_i - 1; -- Count down. + END IF; + + IF fbee_vctr(15) = '1' AND vdl_vct(5) = '1' AND vsync_i = "000" THEN + verz_2 <= verz_2(8 DOWNTO 0) & '1'; + ELSIF (fbee_vctr(15) = '0' or vdl_vct(5) = '0') AND vsync_i /= "000" THEN + verz_2 <= verz_2(8 DOWNTO 0) & '1'; + ELSE + verz_2 <= verz_2(8 DOWNTO 0) & '0'; + END IF; + + IF hsync_i > x"00" THEN + verz_1 <= verz_1(8 DOWNTO 0) & '1'; + ELSE + verz_1 <= verz_1(8 DOWNTO 0) & '0'; + END IF; + + verz_0 <= verz_0(8 DOWNTO 0) & disp_on; + + blank_n <= verz_0(8); + hsync <= verz_1(9); + vsync <= verz_2(9); + sync_n <= NOT(verz_2(9) or verz_1(9)); + + -- border colours: + border <= border(5 DOWNTO 0) & (disp_on AND NOT vdtron AND fbee_vctr(25)); + border_on <= border(6); + + IF last = '1' AND vvcnt = v_total - 10 THEN + fifo_clr <= '1'; + ELSIF last = '1' THEN + fifo_clr <= '0'; + END IF; + + IF last = '1' AND vvcnt = "00000000000" THEN + start_zeile <= '1'; + ELSIF last = '1' THEN + start_zeile <= '0'; + END IF; + + IF vhcnt = x"003" AND start_zeile = '1' THEN + sync_pix <= '1'; + ELSE + sync_pix <= '0'; + END IF; + + IF vhcnt = x"005" AND start_zeile = '1' THEN + sync_pix1 <= '1'; + ELSE + sync_pix1 <= '0'; + END IF; + + IF vhcnt = x"007" AND start_zeile = '1' THEN + sync_pix2 <= '1'; + ELSE + sync_pix2 <= '0'; + END IF; + + IF vdtron = '1' AND sync_pix = '0' THEN + sub_pixel_cnt <= sub_pixel_cnt + 1; + ELSIF vdtron = '1' THEN + sub_pixel_cnt <= (OTHERS => '0'); + END IF; + + IF vdtron = '1' AND sub_pixel_cnt(6 DOWNTO 0) = "0000001" AND color1_i = '1' THEN + fifo_rde <= '1'; + ELSIF vdtron = '1' AND sub_pixel_cnt(5 DOWNTO 0) = "000001" AND color2_i = '1' THEN + fifo_rde <= '1'; + ELSIF vdtron = '1' AND sub_pixel_cnt(4 DOWNTO 0) = "00001" AND color4_i = '1' THEN + fifo_rde <= '1'; + ELSIF vdtron = '1' AND sub_pixel_cnt(3 DOWNTO 0) = "0001" AND color8_i = '1' THEN + fifo_rde <= '1'; + ELSIF vdtron = '1' AND sub_pixel_cnt(2 DOWNTO 0) = "001" AND color16_i = '1' THEN + fifo_rde <= '1'; + ELSIF vdtron = '1' AND sub_pixel_cnt(1 DOWNTO 0) = "01" AND color24_i = '1' THEN + fifo_rde <= '1'; + ELSIF sync_pix = '1' or sync_pix1 = '1' or sync_pix2 = '1' THEN + fifo_rde <= '1'; -- 3 CLOCK ZUS�TZLICH F�R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + ELSE + fifo_rde <= '0'; + END IF; + + clut_mux_av_0 <= sub_pixel_cnt(3 DOWNTO 0); + clut_mux_av_1 <= clut_mux_av_0; + clut_mux_adr <= clut_mux_av_1; + END PROCESS video_clock_domain; +END ARCHITECTURE behaviour;