updated testbench (not functional yet)
This commit is contained in:
Markus Fröschle
@@ -1,47 +1,721 @@
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library work;
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use work.firebee_pkg.all;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY work;
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use std.textio.all;
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PACKAGE ddr2_ram_model_pkg IS
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CONSTANT DM_BITS : INTEGER := 2;
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CONSTANT BA_BITS : INTEGER := 2;
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CONSTANT MEM_BITS : INTEGER := 10; -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024
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CONSTANT AP : INTEGER := 10; -- the address bit that controls auto-precharge and precharge-all
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CONSTANT ADDR_BITS : INTEGER := 13;
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CONSTANT DQ_BITS : INTEGER := 2;
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CONSTANT DQS_BITS : INTEGER := 2;
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CONSTANT TDLLK : INTEGER := 200;
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CONSTANT BUS_DELAY : TIME := 0 ps;
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CONSTANT BANKS : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS));
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CONSTANT ROW_BITS : INTEGER := 13;
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CONSTANT COL_BITS : INTEGER := 10;
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CONSTANT BL_BITS : INTEGER := 3; -- the number of bits required to count to MAX_BL
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CONSTANT BL_MAX : INTEGER := 8;
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CONSTANT BO_BITS : INTEGER := 2; -- the number of burst order bits
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CONSTANT MAX_BITS : INTEGER := BA_BITS + ROW_BITS + COL_BITS - BL_BITS;
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CONSTANT TMRD : TIME := 2 ps; -- load mode register command cycle time
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CONSTANT TRFC_MIN : TIME := 105000 ps; -- refresh to refresh command minimum value
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CONSTANT TRFC_MAX : TIME := 70000000 ps; -- refresh to refresh command maximum value
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CONSTANT TRP : TIME := 13125 ps; -- precharge period
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CONSTANT TRPA : TIME := 13125 ps; -- precharge all period
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CONSTANT TRC : TIME := 54000 ps; -- activate to activate/auto refresh command time
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CONSTANT TRAS_MIN : TIME := 40000 ps; -- minimum active to precharge command time
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CONSTANT TRAS_MAX : TIME := 70000000 ps; -- maximum active to precharge command time
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CONSTANT TRRD : TIME := 10000 ps; -- tRRD: active bank to active bank command time
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-- DDR ram simulation for Firebee video RAM
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CONSTANT RANDOM_SEED : INTEGER := 711689044; -- seed value for random generator
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COMPONENT ddr2_ram_model IS
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GENERIC
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(
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DEBUG : STD_LOGIC := '1';
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DM_BITS : INTEGER := 2;
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BA_BITS : INTEGER := 2;
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ADDR_BITS : INTEGER := 13;
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DQ_BITS : INTEGER := 2;
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DQS_BITS : INTEGER := 2
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);
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PORT
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(
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ck : IN STD_LOGIC;
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ck_n : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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cs_n : IN STD_LOGIC;
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ras_n : IN STD_LOGIC;
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cas_n : IN STD_LOGIC;
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we_n : IN STD_LOGIC;
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dm_rdqs : INOUT STD_LOGIC_VECTOR (DM_BITS - 1 DOWNTO 0);
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ba : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
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addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0);
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dq : INOUT STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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dqs_n : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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rdqs_n : OUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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odt : IN STD_LOGIC
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);
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END COMPONENT;
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END PACKAGE;
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entity ddr_ram_model is
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port (
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signal CK : in std_logic;
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signal CKE : in std_logic;
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signal CSn : in std_logic;
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signal RASn : in std_logic;
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signal CASn : in std_logic;
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signal WEn : in std_logic;
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signal LDM : in std_logic;
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signal UDM : in std_logic;
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signal BA : in std_logic_vector(1 downto 0);
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signal A : in std_logic_vector(12 downto 0);
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signal DQ : inout std_logic_vector(7 downto 0);
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signal LDQS : inout std_logic;
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signal UDQS : inout std_logic
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);
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end entity ddr_ram_model;
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PACKAGE BODY ddr2_ram_model_pkg IS
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END PACKAGE BODY ddr2_ram_model_pkg;
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---------------------------------------------------------------------------------------------------------------------------------------
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architecture behav of ddr_ram_model is
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signal opcode : std_logic_vector(14 downto 0);
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signal command : std_logic_vector(5 downto 0);
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signal OLD_CKE : std_logic := 'X';
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begin
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opcode <= BA & A(10) & A(12 downto 11) & A(9 downto 0);
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command <= OLD_CKE & CKE & CSn & RASn & CASn & WEn;
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clock_hi : process
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begin
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wait until rising_edge(CK) and CK = '1';
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end process;
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clock_lo : process
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begin
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wait until falling_edge(CK) and CK = '0';
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end process;
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end behav;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY work;
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USE work.ddr2_ram_model_pkg.ALL;
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ENTITY ddr2_ram_model IS
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GENERIC
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(
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DEBUG : STD_LOGIC := '1';
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BA_BITS : INTEGER := 2;
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ADDR_BITS : INTEGER := 13;
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DM_BITS : INTEGER := 2;
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DQ_BITS : INTEGER := 16;
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DQS_BITS : INTEGER := 2
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);
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PORT
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(
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ck : IN STD_LOGIC;
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ck_n : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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cs_n : IN STD_LOGIC;
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ras_n : IN STD_LOGIC;
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cas_n : IN STD_LOGIC;
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we_n : IN STD_LOGIC;
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dm_rdqs : INOUT STD_LOGIC_VECTOR (DM_BITS - 1 DOWNTO 0);
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ba : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
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addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0);
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dq : INOUT STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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dqs_n : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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rdqs_n : OUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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odt : IN STD_LOGIC
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);
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END ENTITY ddr2_ram_model;
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ARCHITECTURE rtl OF ddr2_ram_model IS
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CONSTANT DQ_PER_DQS : INTEGER := DQ_BITS / DQS_BITS;
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CONSTANT MAX_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS + ROW_BITS + COL_BITS - BL_BITS));
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CONSTANT MEM_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), MEM_BITS));
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CONSTANT AL_MAX : INTEGER := 6;
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CONSTANT CL_MAX : INTEGER := 7;
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CONSTANT MAX_PIPE : INTEGER := 2 * (AL_MAX + CL_MAX);
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CONSTANT TFAW : INTEGER := 45000;
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CONSTANT TDLLK : INTEGER := 200;
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TYPE time_array_t IS ARRAY (NATURAL RANGE <>) OF TIME;
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-- clock jitter
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SIGNAL tck_avg : REAL;
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SIGNAL tck_sample : time_array_t (TDLLK - 1 DOWNTO 0);
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SIGNAL tch_sample : time_array_t (TDLLK - 1 DOWNTO 0);
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SIGNAL tcl_sample : time_array_t (TDLLK - 1 DOWNTO 0);
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SIGNAL tck_i : TIME;
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SIGNAL tch_i : TIME;
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SIGNAL tcl_i : TIME;
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SIGNAL tch_avg : REAL;
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SIGNAL tcl_avg : REAL;
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SIGNAL tm_ck_pos : TIME;
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SIGNAL tm_ck_neg : TIME;
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SIGNAL tjit_per_rtime : REAL;
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SIGNAL tjit_cc_time : INTEGER;
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SIGNAL terr_nper_rtime : REAL;
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-- clock skew
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SIGNAL out_delay : REAL;
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SIGNAL dqsck : UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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SIGNAL dqsck_min : INTEGER;
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SIGNAL dqsck_max : INTEGER;
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SIGNAL dqsq_min : INTEGER;
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SIGNAL dqsq_max : INTEGER;
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SIGNAL seed : INTEGER;
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-- mode registers
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SIGNAL burst_order : STD_LOGIC;
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SIGNAL burst_length : STD_LOGIC_VECTOR (BL_BITS DOWNTO 0);
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SIGNAL cas_latency : INTEGER;
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SIGNAL additive_latency : INTEGER;
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SIGNAL dll_reset : STD_LOGIC;
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SIGNAL dll_locked : STD_LOGIC;
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SIGNAL dll_en : STD_LOGIC;
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SIGNAL write_recovery : INTEGER;
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SIGNAL low_power : STD_LOGIC;
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SIGNAL odt_rtt : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL odt_en : STD_LOGIC;
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SIGNAL ocd : STD_LOGIC_VECTOR (2 DOWNTO 0);
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SIGNAL dqs_n_en : STD_LOGIC;
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SIGNAL rdqs_en : STD_LOGIC;
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SIGNAL out_en : STD_LOGIC;
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SIGNAL read_latency : INTEGER;
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SIGNAL write_latency : INTEGER;
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TYPE cmd_type_t IS (LOAD_MODE, REFRESH, PRECHARGE, ACTIVATE, WRITE, READ, NOP, PWR_DOWN, SELF_REF);
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TYPE cmd_type_encoding_array_t IS ARRAY(cmd_type_t) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
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CONSTANT cmd_type_encoding : cmd_type_encoding_array_t :=
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(
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"0000", "0001", "0010", "0011",
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"0100", "0101", "0111", "1000",
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"1001"
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);
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TYPE cmd_string_array_t IS ARRAY (INTEGER RANGE <>) OF STRING(1 TO 9);
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CONSTANT cmd_string : cmd_string_array_t(1 TO 9) :=
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( "Load Mode",
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"Refresh ",
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"Precharge",
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"Activate ",
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"Write ",
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"Read ",
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"No OP ",
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"Pwr Down ",
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"Self Ref "
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);
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-- command state
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SIGNAL active_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0);
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SIGNAL auto_precharge_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0);
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SIGNAL write_precharge_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0);
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SIGNAL read_precharge_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0);
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TYPE row_array_t IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0);
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SIGNAL active_row : row_array_t (ROW_BITS - 1 DOWNTO 0);
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SIGNAL in_power_down : STD_LOGIC;
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SIGNAL in_self_refresh : STD_LOGIC;
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SIGNAL init_mode_reg : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL init_done : STD_LOGIC;
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SIGNAL init_step : INTEGER;
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SIGNAL er_trfc_max : STD_LOGIC;
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SIGNAL odt_state : STD_LOGIC;
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SIGNAL pref_odt : STD_LOGIC;
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-- cmd timers/counters
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SIGNAL ref_cntr : INTEGER;
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SIGNAL ck_cntr : TIME;
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SIGNAL ck_load_mode : TIME;
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SIGNAL ck_write : INTEGER;
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SIGNAL ck_read : INTEGER;
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SIGNAL ck_write_ap : INTEGER;
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SIGNAL ck_power_down : INTEGER;
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SIGNAL ck_slow_exit_pd : INTEGER;
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SIGNAL ck_self_refresh : INTEGER;
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SIGNAL ck_cke : INTEGER;
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SIGNAL ck_odt : INTEGER;
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SIGNAL ck_dll_reset : INTEGER;
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TYPE ck_bank_array_t IS ARRAY (NATURAL RANGE <>) OF INTEGER;
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SIGNAL ck_bank_write : ck_bank_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL ck_bank_read : ck_bank_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_refresh : TIME;
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SIGNAL tm_precharge : TIME;
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SIGNAL tm_precharge_all : TIME;
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SIGNAL tm_activate : TIME;
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SIGNAL tm_write_end : TIME;
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SIGNAL tm_self_refresh : TIME;
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SIGNAL tm_odt_en : TIME;
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SIGNAL tm_bank_precharge : time_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_bank_activate : time_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_bank_write_end : time_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_bank_read_end : time_array_t (BANKS - 1 DOWNTO 0);
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-- pipelines
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SIGNAL al_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0);
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SIGNAL wr_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0);
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SIGNAL rd_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0);
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SIGNAL odt_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0);
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TYPE ba_pipeline_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
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SIGNAL ba_pipeline : ba_pipeline_t (MAX_PIPE DOWNTO 0);
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TYPE row_pipeline_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR (ROW_BITS - 1 DOWNTO 0);
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SIGNAL row_pipeline : row_pipeline_t (MAX_PIPE DOWNTO 0);
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TYPE col_pipeline_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR (COL_BITS - 1 DOWNTO 0);
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SIGNAL col_pipeline : col_pipeline_t (MAX_PIPE DOWNTO 0);
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SIGNAL prev_cke : STD_LOGIC;
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-- data state
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SIGNAL memory_data : STD_LOGIC_VECTOR (BL_MAX * DQ_BITS - 1 DOWNTO 0);
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SIGNAL bit_mask : STD_LOGIC_VECTOR (BL_MAX * DQ_BITS - 1 DOWNTO 0);
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SIGNAL burst_position : STD_LOGIC_VECTOR (BL_BITS - 1 DOWNTO 0);
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SIGNAL burst_cntr : STD_LOGIC_VECTOR (BL_BITS DOWNTO 0);
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SIGNAL dq_temp : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
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SIGNAL check_write_postamble: STD_LOGIC_VECTOR (35 DOWNTO 0);
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SIGNAL check_write_preamble : STD_LOGIC_VECTOR (35 DOWNTO 0);
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SIGNAL check_write_dqs_high : STD_LOGIC_VECTOR (35 DOWNTO 0);
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SIGNAL check_write_dqs_low : STD_LOGIC_VECTOR (35 DOWNTO 0);
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SIGNAL check_dm_tdipw : STD_LOGIC_VECTOR (17 DOWNTO 0);
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SIGNAL check_dq_tdipw : STD_LOGIC_VECTOR (17 DOWNTO 0);
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-- data timers/counters
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SIGNAL tm_cke : TIME;
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SIGNAL tm_odt : TIME;
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SIGNAL tm_tdqss : TIME;
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SIGNAL tm_dm : time_array_t (17 DOWNTO 0);
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SIGNAL tm_dqs : time_array_t (17 DOWNTO 0);
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SIGNAL tm_dqs_pos : time_array_t (35 DOWNTO 0);
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SIGNAL tm_dqss_pos : time_array_t (35 DOWNTO 0);
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SIGNAL tm_dqss_neg : time_array_t (35 DOWNTO 0);
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SIGNAL tm_dq : time_array_t (71 DOWNTO 0);
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SIGNAL tm_cmd_addr : time_array_t (22 DOWNTO 0);
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TYPE cmd_addr_array_t IS ARRAY (INTEGER RANGE <>) OF STRING(1 TO 8);
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CONSTANT cmd_addr_string : cmd_addr_array_t(22 DOWNTO 0) :=
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(
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"CS_N ",
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"RAS_N ",
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"CAS_N ",
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"WE_N ",
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"BA 0 ",
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"BA 1 ",
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"BA 2 ",
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"ADDR 0",
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"ADDR 1",
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"ADDR 2",
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"ADDR 3",
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"ADDR 4",
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"ADDR 5",
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"ADDR 6",
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"ADDR 7",
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"ADDR 8",
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"ADDR 9",
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"ADDR 10",
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"ADDR 11",
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"ADDR 12",
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"ADDR 13",
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"ADDR 14",
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"ADDR 15"
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);
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TYPE dqs_string_t IS ARRAY (INTEGER RANGE <>) OF STRING (1 TO 5);
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CONSTANT dqs_string : dqs_string_t (1 DOWNTO 0) :=
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(
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"DQS ",
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"DQS_N"
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);
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-- memory storage
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-- only for MAX_MEM for now
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TYPE mem_t IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (BL_MAX * DQ_BITS - 1 DOWNTO 0);
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SIGNAL memory : mem_t(0 TO MAX_SIZE - 1);
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SIGNAL ck_in : STD_LOGIC;
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SIGNAL ck_n_in : STD_LOGIC;
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SIGNAL cke_in : STD_LOGIC;
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SIGNAL cs_n_in : STD_LOGIC;
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SIGNAL ras_n_in : STD_LOGIC;
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SIGNAL cas_n_in : STD_LOGIC;
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SIGNAL we_n_in : STD_LOGIC;
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SIGNAL dm_in : STD_LOGIC_VECTOR (17 DOWNTO 0);
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SIGNAL ba_in : STD_LOGIC_VECTOR (2 DOWNTO 0);
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SIGNAL addr_in : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL dq_in : STD_LOGIC_VECTOR (71 DOWNTO 0);
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SIGNAL dqs_in : STD_LOGIC_VECTOR (35 DOWNTO 0);
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SIGNAL odt_in : STD_LOGIC;
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SIGNAL dm_in_pos : STD_LOGIC_VECTOR (17 DOWNTO 0);
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SIGNAL dm_in_neg : STD_LOGIC_VECTOR (17 DOWNTO 0);
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SIGNAL dq_in_pos : STD_LOGIC_VECTOR (71 DOWNTO 0);
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SIGNAL dq_in_neg : STD_LOGIC_VECTOR (71 DOWNTO 0);
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SIGNAL dq_in_valid : STD_LOGIC;
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SIGNAL dqs_in_valid : STD_LOGIC;
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SIGNAL wdqs_cntr : INTEGER;
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SIGNAL wdq_cntr : INTEGER;
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TYPE integer_array_t IS ARRAY (NATURAL RANGE <>) OF INTEGER;
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SIGNAL wdqs_pos_cntr : integer_array_t(35 DOWNTO 0);
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SIGNAL b2b_write : STD_LOGIC;
|
||||
SIGNAL prev_dqs_in : STD_LOGIC_VECTOR (35 DOWNTO 0);
|
||||
SIGNAL diff_ck : STD_LOGIC;
|
||||
|
||||
SIGNAL dqs_even : STD_LOGIC_VECTOR (17 DOWNTO 0);
|
||||
SIGNAL dqs_odd : STD_LOGIC_VECTOR (17 DOWNTO 0);
|
||||
SIGNAL cmd_n_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
|
||||
-- transmit
|
||||
SIGNAL dqs_out_en : STD_LOGIC;
|
||||
SIGNAL dqs_out_en_dly : STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dqs_out : STD_LOGIC;
|
||||
SIGNAL dqs_out_dly : STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dq_out_en : STD_LOGIC;
|
||||
SIGNAL dq_out_en_dly : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dq_out : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dq_out_dly : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL rdqsen_cntr : INTEGER;
|
||||
SIGNAL rdqs_cntr : INTEGER;
|
||||
SIGNAL rdqen_cntr : INTEGER;
|
||||
SIGNAL rdq_cntr : INTEGER;
|
||||
|
||||
SIGNAL r : STD_LOGIC := '0';
|
||||
|
||||
PROCEDURE memory_write(
|
||||
SIGNAL bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
|
||||
SIGNAL row : IN UNSIGNED (ROW_BITS - 1 DOWNTO 0);
|
||||
SIGNAL col : IN UNSIGNED (COL_BITS - 1 DOWNTO 0);
|
||||
SIGNAL data : IN UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL addr : INOUT UNSIGNED (MAX_BITS - 1 DOWNTO 0)) IS
|
||||
BEGIN
|
||||
addr <= (bank & row & col) / BL_MAX;
|
||||
-- TODO: only the MAX_MEM defined functionality available here
|
||||
-- memory(addr) <= data;
|
||||
END memory_write;
|
||||
|
||||
PROCEDURE memory_read(
|
||||
SIGNAL bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
|
||||
SIGNAL row : IN UNSIGNED (ROW_BITS - 1 DOWNTO 0);
|
||||
SIGNAL col : IN UNSIGNED (COL_BITS - 1 DOWNTO 0);
|
||||
SIGNAL data : OUT UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL addr : INOUT UNSIGNED (MAX_BITS - 1 DOWNTO 0)) IS
|
||||
BEGIN
|
||||
-- chop off the lowest address bits
|
||||
addr <= (bank & row & col) / BL_MAX;
|
||||
-- TODO: only the MAX_MEM defined functionality defined yet
|
||||
-- data <= memory(addr);
|
||||
END memory_read;
|
||||
|
||||
PROCEDURE cmd_task(
|
||||
cke : IN STD_LOGIC;
|
||||
cmd : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
bank : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
|
||||
addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0)) IS
|
||||
|
||||
VARIABLE i : UNSIGNED (BANKS DOWNTO 0);
|
||||
VARIABLE j : INTEGER;
|
||||
VARIABLE tfaw_cntr : UNSIGNED (BANKS DOWNTO 0);
|
||||
VARIABLE col : UNSIGNED (COL_BITS - 1 DOWNTO 0);
|
||||
BEGIN
|
||||
END cmd_task;
|
||||
|
||||
|
||||
PROCEDURE initialize(
|
||||
SIGNAL mode_reg0 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0);
|
||||
SIGNAL mode_reg1 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0);
|
||||
SIGNAL mode_reg2 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0);
|
||||
SIGNAL mode_reg3 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0)) IS
|
||||
|
||||
CONSTANT AP_BIT : STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(2 ** AP, ADDR_BITS));
|
||||
BEGIN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & "INFO: performing initialization sequence");
|
||||
|
||||
cmd_task('1', cmd_type_encoding(NOP), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
cmd_task('1', cmd_type_encoding(PRECHARGE), (OTHERS => 'X'), AP_BIT);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(3, BA_BITS)), mode_reg3);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(2, BA_BITS)), mode_reg2);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(1, BA_BITS)), mode_reg1);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(0, BA_BITS)), mode_reg0 OR "100"); -- DLL reset
|
||||
cmd_task('1', cmd_type_encoding(PRECHARGE), (OTHERS => 'X'), AP_BIT); -- Precharge all
|
||||
cmd_task('1', cmd_type_encoding(REFRESH), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
cmd_task('1', cmd_type_encoding(REFRESH), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(0, BA_BITS)), mode_reg0);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(1, BA_BITS)), mode_reg1 OR x"380"); -- OCD default
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(1, BA_BITS)), mode_reg1);
|
||||
cmd_task('1', cmd_type_encoding(NOP), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
END initialize;
|
||||
|
||||
FUNCTION abs_value(SIGNAL arg : IN REAL) RETURN REAL IS
|
||||
BEGIN
|
||||
IF arg < 0.0 THEN
|
||||
RETURN -1.0 * arg;
|
||||
END IF;
|
||||
|
||||
RETURN arg;
|
||||
END abs_value;
|
||||
|
||||
BEGIN
|
||||
PROCESS (ck)
|
||||
BEGIN
|
||||
ck_in <= ck AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (ck_n)
|
||||
BEGIN
|
||||
ck_n_in <= ck_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (cke)
|
||||
BEGIN
|
||||
cke_in <= cke AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (cs_n)
|
||||
BEGIN
|
||||
cs_n_in <= cs_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (ras_n)
|
||||
BEGIN
|
||||
ras_n_in <= ras_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (cas_n)
|
||||
BEGIN
|
||||
cas_n_in <= cas_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (we_n)
|
||||
BEGIN
|
||||
we_n_in <= we_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (dm_rdqs)
|
||||
BEGIN
|
||||
dm_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(dm_rdqs), dm_in'LENGTH)) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (ba)
|
||||
BEGIN
|
||||
ba_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(ba), ba_in'LENGTH)) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (addr)
|
||||
BEGIN
|
||||
addr_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(addr), addr_in'LENGTH)) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (dq)
|
||||
BEGIN
|
||||
dq_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(dq), dq_in'LENGTH)) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (dqs, dqs_n)
|
||||
BEGIN
|
||||
dqs_in <= STD_LOGIC_VECTOR(SHIFT_LEFT(RESIZE(UNSIGNED(dqs_n), dqs_in'LENGTH), 18)) OR STD_LOGIC_VECTOR(RESIZE(UNSIGNED(dqs), dqs_in'LENGTH));
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (odt)
|
||||
BEGIN
|
||||
odt_in <= odt AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
-- create internal clock
|
||||
PROCESS
|
||||
BEGIN
|
||||
WAIT UNTIL RISING_EDGE(ck_in);
|
||||
diff_ck <= ck_in;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS
|
||||
BEGIN
|
||||
WAIT UNTIL RISING_EDGE(ck_n_in);
|
||||
diff_ck <= NOT ck_n_in;
|
||||
END PROCESS;
|
||||
|
||||
dqs_even <= dqs_in (17 DOWNTO 0);
|
||||
dqs_odd <= dqs_in (35 DOWNTO 18) WHEN dqs_n_en = '1' ELSE NOT(dqs_in (17 DOWNTO 0));
|
||||
cmd_n_in <= '0' & ras_n_in & cas_n_in & we_n_in WHEN NOT(cs_n_in) ELSE cmd_type_encoding(NOP);
|
||||
|
||||
-- bufif1 buf_dqs
|
||||
dqs <= dqs_out_dly WHEN (dqs_out_en_dly AND STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
|
||||
-- bufif1 buf_dm
|
||||
dm_rdqs <= dqs_out_dly WHEN (dqs_out_en_dly AND
|
||||
STD_LOGIC_VECTOR'(0 TO DM_BITS - 1 => out_en) AND
|
||||
STD_LOGIC_VECTOR'(0 TO DM_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
-- bufif1 buf_dqs_n
|
||||
dqs_n <= NOT dqs_out_dly WHEN (dqs_out_en_dly AND
|
||||
STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => out_en) AND
|
||||
STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => dqs_n_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
-- bufif1 buf_rdqs_n
|
||||
rdqs_n <= NOT dqs_out_dly WHEN (dqs_out_en_dly AND
|
||||
STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => out_en) AND
|
||||
STD_LOGIC_VECTOR'(0 to DQS_BITS - 1 => dqs_n_en) AND
|
||||
STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
|
||||
-- bufif1 buf_dq
|
||||
dq <= dq_out_dly WHEN (dq_out_en_dly AND
|
||||
STD_LOGIC_VECTOR'(0 TO DQ_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
|
||||
-- initial block
|
||||
init : PROCESS
|
||||
BEGIN
|
||||
IF BL_MAX < 2 THEN
|
||||
REPORT("ERROR: BL_MAX parameter must be >= 2. BL_MAX=" & INTEGER'IMAGE(BL_MAX));
|
||||
END IF;
|
||||
|
||||
IF 2 ** BO_BITS > BL_MAX THEN
|
||||
REPORT("ERROR: 2**BO_BITS cannot be greater than BL_MAX parameter");
|
||||
END IF;
|
||||
seed <= RANDOM_SEED;
|
||||
ck_cntr <= 0 ps;
|
||||
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
-- ugly kludge: encapsulate reset_task PROCEDURE into a process to make ModelSim happy
|
||||
reset : PROCESS
|
||||
PROCEDURE reset_task IS
|
||||
-- VARIABLE i : INTEGER;
|
||||
BEGIN
|
||||
-- disable inputs
|
||||
dq_in_valid <= '0';
|
||||
dqs_in_valid <= '0';
|
||||
wdqs_cntr <= 0;
|
||||
wdq_cntr <= 0;
|
||||
|
||||
FOR i IN 0 TO 35 LOOP
|
||||
wdqs_pos_cntr(i) <= 0;
|
||||
END LOOP;
|
||||
|
||||
b2b_write <= '0';
|
||||
|
||||
-- disable outputs
|
||||
out_en <= '0';
|
||||
dqs_n_en <= '0';
|
||||
rdqs_en <= '0';
|
||||
dq_out_en <= '0';
|
||||
rdq_cntr <= 0;
|
||||
dqs_out_en <= '0';
|
||||
rdqs_cntr <= 0;
|
||||
|
||||
-- disable ODT
|
||||
odt_en <= '0';
|
||||
odt_state <= '0';
|
||||
|
||||
-- reset bank state
|
||||
active_bank <= (OTHERS => '1');
|
||||
auto_precharge_bank <= (OTHERS =>'0');
|
||||
read_precharge_bank <= (OTHERS => '0');
|
||||
write_precharge_bank <= (OTHERS =>'0');
|
||||
|
||||
-- require initialization sequence
|
||||
init_done <= '0';
|
||||
init_step <= 0;
|
||||
init_mode_reg <= (OTHERS => '0');
|
||||
|
||||
-- reset DLL
|
||||
dll_en <= '0';
|
||||
dll_reset <= '0';
|
||||
dll_locked <= '0';
|
||||
ocd <= (OTHERS => '0');
|
||||
|
||||
-- exit power down and self refresh
|
||||
in_power_down <= '0';
|
||||
in_self_refresh <= '0';
|
||||
|
||||
-- clear pipelines
|
||||
al_pipeline <= (OTHERS => '0');
|
||||
wr_pipeline <= (OTHERS => '0');
|
||||
rd_pipeline <= (OTHERS => '0');
|
||||
odt_pipeline <= (OTHERS => '0');
|
||||
|
||||
-- clear memory
|
||||
FOR i IN 0 TO MAX_SIZE LOOP
|
||||
memory(i) <= (OTHERS => 'X');
|
||||
END LOOP;
|
||||
|
||||
-- clear maximum timing checks
|
||||
tm_refresh <= 0 ns;
|
||||
FOR i IN 0 TO BANKS - 1 LOOP
|
||||
tm_bank_activate(i) <= 0 ns;
|
||||
END LOOP;
|
||||
END reset_task;
|
||||
BEGIN
|
||||
WAIT UNTIL rising_edge(ck);
|
||||
IF r /= '0' THEN
|
||||
reset_task;
|
||||
r <= '0';
|
||||
END IF;
|
||||
END PROCESS; -- reset
|
||||
|
||||
err : PROCESS
|
||||
PROCEDURE chk_err (
|
||||
samebank : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
bank : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
|
||||
fromcmd : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
cmd : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
|
||||
) IS
|
||||
|
||||
VARIABLE err : STD_LOGIC;
|
||||
BEGIN
|
||||
-- all matching case expression will be evaluated
|
||||
|
||||
CASE? (STD_LOGIC_VECTOR'(samebank & fromcmd & cmd)) IS
|
||||
WHEN "1" & cmd_type_encoding(LOAD_MODE) & "0---" =>
|
||||
IF ck_cntr - ck_load_mode < TMRD THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tMRD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(LOAD_MODE) & "100-" =>
|
||||
IF ck_cntr - ck_load_mode < TMRD THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Load Mode to Reset Condition");
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(REFRESH) & "0---" =>
|
||||
IF NOW - tm_refresh < TRFC_MIN THEN
|
||||
REPORT("tRFC violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(REFRESH) & cmd_type_encoding(PWR_DOWN) => -- 1 tCK_avg
|
||||
WHEN "1" & cmd_type_encoding(REFRESH) & cmd_type_encoding(SELF_REF) =>
|
||||
IF NOW - tm_refresh < TRFC_MIN THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & "INFO: Refresh to Reset condition");
|
||||
END IF;
|
||||
init_done <= '0';
|
||||
WHEN "1" & cmd_type_encoding(PRECHARGE) & "000-" =>
|
||||
IF NOW - tm_precharge_all < TRPA THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRPA violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
IF NOW - tm_precharge < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRP violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PRECHARGE) =>
|
||||
IF DEBUG = '1' AND NOW - tm_precharge_all < TRPA THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge All interruption during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
IF DEBUG = '1' AND NOW - tm_bank_precharge(TO_INTEGER(UNSIGNED(bank))) < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge Bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))) & " interruption during "
|
||||
& cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(ACTIVATE) =>
|
||||
IF NOW - tm_precharge_all < TRPA THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRPA violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
IF NOW - tm_bank_precharge(TO_INTEGER(UNSIGNED(bank))) < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " tRP violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank "
|
||||
& INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PWR_DOWN) =>
|
||||
-- 1 tCK, can be concurrent with auto precharge
|
||||
WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(SELF_REF) =>
|
||||
IF NOW - tm_precharge_all < TRPA OR NOW - tm_precharge < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge to reset condition");
|
||||
init_done <= '0';
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(REFRESH) =>
|
||||
IF NOW - tm_activate < TRC THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRC violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(PRECHARGE) =>
|
||||
IF NOW - tm_bank_activate(TO_INTEGER(UNSIGNED(bank))) > TRAS_MAX AND active_bank(TO_INTEGER(UNSIGNED(bank))) = '1' THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRAS maximum violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
|
||||
END IF;
|
||||
IF NOW - tm_bank_activate(TO_INTEGER(UNSIGNED(bank))) < TRAS_MIN THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRAS minimum violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
|
||||
END IF;
|
||||
WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(ACTIVATE) =>
|
||||
IF NOW - tm_activate < TRRD THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRRD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
|
||||
END IF;
|
||||
WHEN OTHERS => -- do nothing
|
||||
END CASE?;
|
||||
END;
|
||||
BEGIN
|
||||
WAIT UNTIL RISING_EDGE(ck);
|
||||
END PROCESS; -- err
|
||||
END rtl;
|
||||
|
||||
Reference in New Issue
Block a user