updated testbench (not functional yet)
This commit is contained in:
Markus Fröschle
@@ -1,235 +1,176 @@
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library work;
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use work.firebee_pkg.all;
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LIBRARY work;
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USE work.firebee_pkg.ALL;
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USE work.ddr2_ram_model_pkg.ALL;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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USE std.textio.ALL;
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entity ddr_ctlr_tb is
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end ddr_ctlr_tb;
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ENTITY ddr_ctlr_tb IS
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END ddr_ctlr_tb;
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architecture beh of ddr_ctlr_tb is
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signal clock : std_logic := '0'; -- main clock
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signal ddr_clk : std_logic := '0'; -- ddr clock
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ARCHITECTURE beh OF ddr_ctlr_tb IS
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SIGNAL clock : STD_LOGIC := '0'; -- main clock
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SIGNAL ddr_clk : STD_LOGIC := '0'; -- ddr clock
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signal FB_ADR : std_logic_vector(31 downto 0);
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signal DDR_SYNC_66M : std_logic := '0';
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signal FB_CS1n : std_logic;
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signal FB_OEn : std_logic := '1'; -- only write cycles for now
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signal FB_SIZE0 : std_logic := '1';
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signal FB_SIZE1 : std_logic := '1'; -- long word access
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signal FB_ALE : std_logic := 'Z'; -- defined reset state
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signal FB_WRn : std_logic;
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signal FIFO_CLR : std_logic;
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signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0);
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signal BLITTER_ADR : std_logic_vector(31 downto 0);
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signal BLITTER_SIG : std_logic;
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signal BLITTER_WR : std_logic;
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signal DDRCLK0 : std_logic;
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signal CLK_33M : std_logic := '0';
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signal FIFO_MW : std_logic_vector(8 downto 0);
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signal VA : std_logic_vector(12 downto 0);
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signal VWEn : std_logic;
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signal VRASn : std_logic;
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signal VCSn : std_logic;
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signal VCKE : std_logic;
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signal VCASn : std_logic;
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signal FB_LE : std_logic_vector(3 downto 0);
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signal FB_VDOE : std_logic_vector(3 downto 0);
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signal SR_FIFO_WRE : std_logic;
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signal SR_DDR_FB : std_logic;
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signal SR_DDR_WR : std_logic;
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signal SR_DDRWR_D_SEL: std_logic;
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signal SR_VDMP : std_logic_vector(7 downto 0);
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signal VIDEO_DDR_TA : std_logic;
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signal SR_BLITTER_DACK : std_logic;
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signal BA : std_logic_vector(1 downto 0);
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signal DDRWR_D_SEL1 : std_logic;
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signal VDM_SEL : std_logic_vector(3 downto 0);
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signal DATA_IN : std_logic_vector(31 downto 0);
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signal DATA_OUT : std_logic_vector(31 downto 16);
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signal DATA_EN_H : std_logic;
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signal DATA_EN_L : std_logic;
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SIGNAL FB_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL DDR_SYNC_66M : STD_LOGIC := '0';
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SIGNAL FB_CS1_n : STD_LOGIC;
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SIGNAL FB_OE_n : STD_LOGIC := '1'; -- only write cycles for now
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SIGNAL FB_SIZE0 : STD_LOGIC := '1';
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SIGNAL FB_SIZE1 : STD_LOGIC := '1'; -- long word access
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SIGNAL FB_ALE : STD_LOGIC := 'Z'; -- defined reset state
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SIGNAL FB_WRn : STD_LOGIC;
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SIGNAL FIFO_CLR : STD_LOGIC;
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SIGNAL VIDEO_RAM_CTR : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL BLITTER_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL BLITTER_SIG : STD_LOGIC;
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SIGNAL BLITTER_WR : STD_LOGIC;
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SIGNAL ddrclk0 : STD_LOGIC;
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SIGNAL CLK_33M : STD_LOGIC := '0';
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SIGNAL FIFO_MW : STD_LOGIC_VECTOR(8 DOWNTO 0);
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SIGNAL va : STD_LOGIC_VECTOR(12 DOWNTO 0);
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SIGNAL vwe_n : STD_LOGIC;
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SIGNAL vras_n : STD_LOGIC;
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SIGNAL vcs_n : STD_LOGIC;
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SIGNAL vcke : STD_LOGIC;
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SIGNAL vcas_n : STD_LOGIC;
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SIGNAL FB_LE : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL FB_VDOE : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL SR_FIFO_WRE : STD_LOGIC;
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SIGNAL SR_DDR_FB : STD_LOGIC;
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SIGNAL SR_DDR_WR : STD_LOGIC;
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SIGNAL SR_DDRWR_D_SEL : STD_LOGIC;
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SIGNAL sr_vdmp : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL VIDEO_DDR_TA : STD_LOGIC;
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SIGNAL SR_BLITTER_DACK : STD_LOGIC;
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SIGNAL ba : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL DDRWR_D_SEL1 : STD_LOGIC;
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SIGNAL VDM_SEL : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL DATA_IN : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL DATA_OUT : STD_LOGIC_VECTOR(31 DOWNTO 16);
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SIGNAL data_en_h : STD_LOGIC;
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SIGNAL data_en_l : STD_LOGIC;
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type bus_state_type is (S0, S1, S2, S3); -- according to state machine description on p 17-14 of the MCF ref manual
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signal bus_state : bus_state_type := S0;
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component DDR_CTRL_V1
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port(
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CLK_MAIN : in std_logic;
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DDR_SYNC_66M : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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FB_CS1n : in std_logic;
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FB_OEn : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_ALE : in std_logic;
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FB_WRn : in std_logic;
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FIFO_CLR : in std_logic;
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VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
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BLITTER_ADR : in std_logic_vector(31 downto 0);
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BLITTER_SIG : in std_logic;
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BLITTER_WR : in std_logic;
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DDRCLK0 : in std_logic;
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CLK_33M : in std_logic;
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FIFO_MW : in std_logic_vector(8 downto 0);
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VA : out std_logic_vector(12 downto 0);
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VWEn : out std_logic;
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VRASn : out std_logic;
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VCSn : out std_logic;
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VCKE : out std_logic;
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VCASn : out std_logic;
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FB_LE : out std_logic_vector(3 downto 0);
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FB_VDOE : out std_logic_vector(3 downto 0);
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SR_FIFO_WRE : out std_logic;
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SR_DDR_FB : out std_logic;
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SR_DDR_WR : out std_logic;
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SR_DDRWR_D_SEL : out std_logic;
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SR_VDMP : out std_logic_vector(7 downto 0);
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VIDEO_DDR_TA : out std_logic;
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SR_BLITTER_DACK : out std_logic;
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BA : out std_logic_vector(1 downto 0);
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DDRWR_D_SEL1 : out std_logic;
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VDM_SEL : out std_logic_vector(3 downto 0);
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DATA_IN : in std_logic_vector(31 downto 0);
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DATA_OUT : out std_logic_vector(31 downto 16);
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DATA_EN_H : out std_logic;
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DATA_EN_L : out std_logic
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);
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end component;
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component ddr_ram_model
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port (
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signal CK : in std_logic;
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signal CKE : in std_logic;
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signal CSn : in std_logic;
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signal RASn : in std_logic;
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signal CASn : in std_logic;
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signal WEn : in std_logic;
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signal LDM : in std_logic;
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signal UDM : in std_logic;
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signal BA : in std_logic_vector(1 downto 0);
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signal A : in std_logic_vector(12 downto 0);
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signal DQ : inout std_logic_vector(7 downto 0);
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signal LDQS : inout std_logic;
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signal UDQS : inout std_logic
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);
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end component;
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begin
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t : DDR_CTRL_V1
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port map
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TYPE bus_state_t IS (S0, S1, S2, S3); -- according to state machine description on p 17-14 of the MCF ref manual
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SIGNAL bus_state : bus_state_t := S0;
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BEGIN
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t : DDR_CTRL
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PORT map
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(
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CLK_MAIN => clock,
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DDR_SYNC_66M => DDR_SYNC_66M,
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FB_ADR => FB_ADR,
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FB_CS1n => FB_CS1n,
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FB_OEn => FB_OEn,
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FB_CS1_n => fb_cs1_n,
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FB_OE_n => FB_OE_n,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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FB_ALE => FB_ALE,
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FB_WRn => FB_WRn,
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FB_WR_n => FB_WRn,
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FIFO_CLR => FIFO_CLR,
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VIDEO_RAM_CTR => VIDEO_RAM_CTR,
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video_control_register => VIDEO_RAM_CTR,
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BLITTER_ADR => BLITTER_ADR,
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BLITTER_SIG => BLITTER_SIG,
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BLITTER_WR => BLITTER_WR,
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DDRCLK0 => DDRCLK0,
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ddrclk0 => ddrclk0,
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CLK_33M => CLK_33M,
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FIFO_MW => FIFO_MW,
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VA => VA,
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VWEn => VWEn,
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VRASn => VRASn,
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VCSn => VCSn,
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VCKE => VCKE,
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VCASn => VCASn,
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va => va,
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vwe_n => vwe_n,
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vras_n => vras_n,
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vcs_n => vcs_n,
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vcke => vcke,
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vcas_n => vcas_n,
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FB_LE => FB_LE,
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FB_VDOE => FB_VDOE,
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SR_FIFO_WRE => SR_FIFO_WRE,
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SR_DDR_FB => SR_DDR_FB,
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SR_DDR_WR => SR_DDR_WR,
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SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
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SR_VDMP => SR_VDMP,
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sr_vdmp => sr_vdmp,
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VIDEO_DDR_TA => VIDEO_DDR_TA,
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SR_BLITTER_DACK => SR_BLITTER_DACK,
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BA => BA,
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ba => ba,
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DDRWR_D_SEL1 => DDRWR_D_SEL1,
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VDM_SEL => VDM_SEL,
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DATA_IN => DATA_IN,
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DATA_OUT => DATA_OUT,
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DATA_EN_H => DATA_EN_H,
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DATA_EN_L => DATA_EN_L
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data_en_h => data_en_h,
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data_en_l => data_en_l
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);
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d : ddr_ram_model
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port map
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d1 : ddr2_ram_model
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PORT map
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(
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CK => DDRCLK0,
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CKE => VCKE,
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CSn => VCSn,
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RASn => VRASn,
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CASn => VCASn,
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WEn => VWEn,
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LDM => DATA_EN_L,
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UDM => DATA_EN_H,
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BA => BA,
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A => VA,
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DQ => SR_VDMP,
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LDQS => DATA_EN_L,
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UDQS => DATA_EN_H
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ck => ddrclk0,
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ck_n => NOT ddrclk0,
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cke => vcke,
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cs_n => vcs_n,
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ras_n => vras_n,
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cas_n => vcas_n,
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we_n => vwe_n,
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dm_rdqs(0) => data_en_l,
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dm_rdqs(1) => data_en_h,
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ba => ba,
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addr => va (25 DOWNTO 13),
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DQ => sr_vdmp,
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LDQS => data_en_l,
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UDQS => data_en_h
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);
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stimulate_main_clock : process
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begin
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wait for 4.31 ns;
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clock <= not clock;
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end process;
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BEGIN
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WAIT FOR 4.31 ns;
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clock <= NOT clock;
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END process;
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stimulate_33mHz_clock : process
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begin
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wait for 30.3 ns;
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CLK_33M <= not CLK_33M;
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end process;
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BEGIN
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WAIT FOR 30.3 ns;
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CLK_33M <= NOT CLK_33M;
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END process;
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stimulate_66MHz_clock : process
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begin
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wait for 66.6 ns;
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DDR_SYNC_66M <= not DDR_SYNC_66M;
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DDRCLK0 <= DDR_SYNC_66M;
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end process;
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BEGIN
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WAIT FOR 66.6 ns;
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DDR_SYNC_66M <= NOT DDR_SYNC_66M;
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ddrclk0 <= DDR_SYNC_66M;
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END process;
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stimulate : process
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variable adr : std_logic_vector(31 downto 0) := x"00000000";
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begin
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wait until rising_edge(clock) and clock = '1';
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case bus_state is
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when S0 =>
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VARIABLE adr : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
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BEGIN
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WAIT UNTIL RISING_EDGE(clock);
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CASE bus_state IS
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WHEN S0 =>
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-- address phase
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FB_ADR <= adr;
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FB_ALE <= '1';
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FB_WRn <= '0';
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bus_state <= S1;
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when S1 =>
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WHEN S1 =>
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-- data phase
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FB_ALE <= '0';
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FB_CS1n <= '0';
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FB_ADR <= x"47114711";
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if (VIDEO_DDR_TA = '1') then
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bus_state <= S2;
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end if;
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when S2 =>
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END if;
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WHEN S2 =>
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FB_CS1n <= '0';
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bus_state <= S3;
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when S3 =>
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FB_ADR <= std_logic_vector(unsigned(FB_ADR) + 4);
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WHEN S3 =>
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FB_ADR <= STD_LOGIC_VECTOR(UNSIGNED(FB_ADR) + 4);
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bus_state <= S0;
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FB_WRn <= 'Z';
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when others =>
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report("bus_state: ");
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end case;
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end process;
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end beh;
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WHEN others =>
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REPORT("bus_state: ");
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END CASE;
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END process;
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END beh;
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